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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.44 90.58 80.18 89.51 92.51 80.56 85.31


Total test records in report: 949
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T823 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.927801638 Mar 24 03:51:23 PM PDT 24 Mar 24 04:40:47 PM PDT 24 22678806662 ps
T277 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2563914534 Mar 24 03:21:11 PM PDT 24 Mar 24 03:37:15 PM PDT 24 5758607200 ps
T279 /workspace/coverage/default/3.chip_tap_straps_dev.1230920853 Mar 24 03:47:35 PM PDT 24 Mar 24 04:05:18 PM PDT 24 12180320995 ps
T280 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1723411496 Mar 24 03:42:19 PM PDT 24 Mar 24 04:07:25 PM PDT 24 7153038704 ps
T281 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3289728323 Mar 24 03:43:01 PM PDT 24 Mar 24 04:48:04 PM PDT 24 15333845808 ps
T273 /workspace/coverage/default/1.chip_sw_all_escalation_resets.487411664 Mar 24 03:26:07 PM PDT 24 Mar 24 03:33:53 PM PDT 24 5317717320 ps
T282 /workspace/coverage/default/1.chip_sw_aon_timer_irq.400752334 Mar 24 03:31:39 PM PDT 24 Mar 24 03:37:34 PM PDT 24 4163937186 ps
T283 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3618525831 Mar 24 03:29:41 PM PDT 24 Mar 24 04:04:55 PM PDT 24 8207377645 ps
T284 /workspace/coverage/default/87.chip_sw_all_escalation_resets.554735537 Mar 24 03:56:07 PM PDT 24 Mar 24 04:05:57 PM PDT 24 4391435280 ps
T285 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3815608319 Mar 24 03:29:15 PM PDT 24 Mar 24 03:52:32 PM PDT 24 8094464184 ps
T286 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4277720702 Mar 24 03:50:28 PM PDT 24 Mar 24 03:57:13 PM PDT 24 4107802328 ps
T824 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.250760579 Mar 24 03:54:05 PM PDT 24 Mar 24 03:59:16 PM PDT 24 2949297340 ps
T825 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4073247927 Mar 24 03:24:37 PM PDT 24 Mar 24 03:34:16 PM PDT 24 6311145832 ps
T826 /workspace/coverage/default/0.rom_volatile_raw_unlock.857440453 Mar 24 03:25:52 PM PDT 24 Mar 24 03:27:25 PM PDT 24 2212875278 ps
T217 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4038480726 Mar 24 03:39:26 PM PDT 24 Mar 24 03:55:01 PM PDT 24 5821108952 ps
T827 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2684953944 Mar 24 03:37:50 PM PDT 24 Mar 24 03:52:44 PM PDT 24 5442156543 ps
T828 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3512796129 Mar 24 03:25:58 PM PDT 24 Mar 24 03:31:12 PM PDT 24 3444955892 ps
T453 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1306132700 Mar 24 03:49:05 PM PDT 24 Mar 24 03:55:04 PM PDT 24 3497072662 ps
T829 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1953120415 Mar 24 03:30:10 PM PDT 24 Mar 24 03:46:05 PM PDT 24 11107950552 ps
T830 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2225227413 Mar 24 03:46:45 PM PDT 24 Mar 24 03:51:27 PM PDT 24 2464793769 ps
T495 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.375278615 Mar 24 03:50:10 PM PDT 24 Mar 24 03:57:22 PM PDT 24 3124194544 ps
T831 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.571724865 Mar 24 03:50:18 PM PDT 24 Mar 24 04:21:29 PM PDT 24 12984113988 ps
T832 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1800874738 Mar 24 03:40:53 PM PDT 24 Mar 24 03:57:14 PM PDT 24 9334517020 ps
T833 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3045046473 Mar 24 03:57:01 PM PDT 24 Mar 24 04:06:20 PM PDT 24 5098232300 ps
T834 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3003885807 Mar 24 03:29:34 PM PDT 24 Mar 24 04:15:40 PM PDT 24 12193641456 ps
T835 /workspace/coverage/default/1.chip_sw_otbn_randomness.1345361619 Mar 24 03:31:31 PM PDT 24 Mar 24 03:49:56 PM PDT 24 5911255352 ps
T428 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1439622986 Mar 24 03:48:51 PM PDT 24 Mar 24 03:57:59 PM PDT 24 5140152724 ps
T358 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292243456 Mar 24 03:42:08 PM PDT 24 Mar 24 04:05:37 PM PDT 24 22981260664 ps
T836 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3220569614 Mar 24 03:47:52 PM PDT 24 Mar 24 04:18:10 PM PDT 24 14670289265 ps
T837 /workspace/coverage/default/0.chip_sw_example_flash.242382141 Mar 24 03:21:01 PM PDT 24 Mar 24 03:24:39 PM PDT 24 3139108786 ps
T36 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1537320243 Mar 24 03:39:24 PM PDT 24 Mar 24 03:45:54 PM PDT 24 3312235430 ps
T838 /workspace/coverage/default/2.chip_sw_kmac_entropy.2646955266 Mar 24 03:39:46 PM PDT 24 Mar 24 03:43:11 PM PDT 24 2595833030 ps
T839 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.884435663 Mar 24 03:32:16 PM PDT 24 Mar 24 03:42:06 PM PDT 24 3937497728 ps
T840 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2774443119 Mar 24 03:53:33 PM PDT 24 Mar 24 04:17:15 PM PDT 24 8733452079 ps
T482 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181623356 Mar 24 03:50:44 PM PDT 24 Mar 24 03:58:19 PM PDT 24 4138163980 ps
T414 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1535974986 Mar 24 03:45:40 PM PDT 24 Mar 24 03:55:54 PM PDT 24 4236841507 ps
T841 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2800418282 Mar 24 03:28:54 PM PDT 24 Mar 24 03:36:04 PM PDT 24 4049147452 ps
T842 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2292272744 Mar 24 03:20:00 PM PDT 24 Mar 24 03:27:56 PM PDT 24 5941437000 ps
T843 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2330231241 Mar 24 03:26:46 PM PDT 24 Mar 24 03:30:54 PM PDT 24 3007759983 ps
T844 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3109889620 Mar 24 03:47:48 PM PDT 24 Mar 24 04:08:13 PM PDT 24 13309610610 ps
T493 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336623486 Mar 24 03:53:04 PM PDT 24 Mar 24 03:58:11 PM PDT 24 3113252600 ps
T845 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2334885604 Mar 24 03:38:30 PM PDT 24 Mar 24 03:42:45 PM PDT 24 3018107752 ps
T846 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3364494824 Mar 24 03:47:01 PM PDT 24 Mar 24 03:52:59 PM PDT 24 3748423657 ps
T847 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1068345911 Mar 24 03:21:15 PM PDT 24 Mar 24 03:26:31 PM PDT 24 2819769453 ps
T848 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2318514127 Mar 24 03:36:34 PM PDT 24 Mar 24 03:45:36 PM PDT 24 6165652980 ps
T510 /workspace/coverage/default/86.chip_sw_all_escalation_resets.381618123 Mar 24 03:55:59 PM PDT 24 Mar 24 04:05:14 PM PDT 24 5935567774 ps
T849 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.452608815 Mar 24 03:40:36 PM PDT 24 Mar 24 03:49:03 PM PDT 24 3821764192 ps
T850 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1635905677 Mar 24 03:49:38 PM PDT 24 Mar 24 03:53:20 PM PDT 24 2810571720 ps
T851 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922313595 Mar 24 03:52:29 PM PDT 24 Mar 24 04:00:16 PM PDT 24 3709768680 ps
T852 /workspace/coverage/default/0.chip_sw_kmac_app_rom.753530529 Mar 24 03:22:00 PM PDT 24 Mar 24 03:26:23 PM PDT 24 2715215896 ps
T853 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3428150472 Mar 24 03:44:22 PM PDT 24 Mar 24 03:53:39 PM PDT 24 9093875778 ps
T854 /workspace/coverage/default/0.chip_tap_straps_rma.2733615763 Mar 24 03:23:16 PM PDT 24 Mar 24 03:29:45 PM PDT 24 4432731521 ps
T855 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3620221114 Mar 24 03:52:17 PM PDT 24 Mar 24 04:02:29 PM PDT 24 5509634534 ps
T459 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1746296200 Mar 24 03:23:55 PM PDT 24 Mar 24 03:30:07 PM PDT 24 4067448634 ps
T856 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2529338897 Mar 24 03:31:28 PM PDT 24 Mar 24 04:18:41 PM PDT 24 11412351750 ps
T460 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544416225 Mar 24 03:55:51 PM PDT 24 Mar 24 04:01:41 PM PDT 24 3786361848 ps
T857 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3690694585 Mar 24 03:25:33 PM PDT 24 Mar 24 03:30:30 PM PDT 24 2688406330 ps
T480 /workspace/coverage/default/47.chip_sw_all_escalation_resets.1108964777 Mar 24 03:52:03 PM PDT 24 Mar 24 04:04:12 PM PDT 24 5971540624 ps
T78 /workspace/coverage/default/1.chip_sw_alert_test.689871527 Mar 24 03:32:21 PM PDT 24 Mar 24 03:37:32 PM PDT 24 3285930254 ps
T858 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4161372349 Mar 24 03:30:52 PM PDT 24 Mar 24 04:20:21 PM PDT 24 34599781000 ps
T859 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3768232433 Mar 24 03:21:05 PM PDT 24 Mar 24 06:36:35 PM PDT 24 254708065108 ps
T332 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1999041109 Mar 24 03:21:50 PM PDT 24 Mar 24 04:30:59 PM PDT 24 15342475304 ps
T860 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4073243809 Mar 24 03:38:41 PM PDT 24 Mar 24 03:42:15 PM PDT 24 3299762154 ps
T861 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1491408367 Mar 24 03:33:15 PM PDT 24 Mar 24 03:41:53 PM PDT 24 4293446374 ps
T862 /workspace/coverage/default/2.chip_tap_straps_rma.1959776865 Mar 24 03:47:32 PM PDT 24 Mar 24 03:49:55 PM PDT 24 2094167267 ps
T237 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3965130030 Mar 24 03:35:06 PM PDT 24 Mar 24 03:39:10 PM PDT 24 3225369194 ps
T863 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2651598510 Mar 24 03:29:16 PM PDT 24 Mar 24 04:11:03 PM PDT 24 9823409786 ps
T864 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2196190405 Mar 24 03:39:33 PM PDT 24 Mar 24 03:53:47 PM PDT 24 5295168533 ps
T865 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1830931792 Mar 24 03:46:21 PM PDT 24 Mar 24 03:51:35 PM PDT 24 3742596505 ps
T866 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1895116437 Mar 24 03:35:44 PM PDT 24 Mar 24 03:44:32 PM PDT 24 3336696680 ps
T400 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3774073221 Mar 24 03:46:21 PM PDT 24 Mar 24 03:54:36 PM PDT 24 7176504664 ps
T328 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3701399987 Mar 24 03:33:30 PM PDT 24 Mar 24 03:40:14 PM PDT 24 3674696242 ps
T392 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2197426529 Mar 24 03:32:36 PM PDT 24 Mar 24 03:47:10 PM PDT 24 3433409906 ps
T867 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.580024821 Mar 24 03:42:20 PM PDT 24 Mar 24 03:47:36 PM PDT 24 3060598235 ps
T334 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4205105010 Mar 24 03:56:00 PM PDT 24 Mar 24 04:01:32 PM PDT 24 3919952920 ps
T365 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2711239475 Mar 24 03:20:45 PM PDT 24 Mar 24 03:51:44 PM PDT 24 8082751944 ps
T868 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2035790541 Mar 24 03:23:59 PM PDT 24 Mar 24 03:27:44 PM PDT 24 2765947227 ps
T869 /workspace/coverage/default/2.chip_sw_kmac_idle.2214538912 Mar 24 03:43:19 PM PDT 24 Mar 24 03:47:32 PM PDT 24 2518094182 ps
T310 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1048841228 Mar 24 03:47:12 PM PDT 24 Mar 24 03:52:27 PM PDT 24 3126623859 ps
T870 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1192802574 Mar 24 03:18:53 PM PDT 24 Mar 24 04:49:21 PM PDT 24 51880013080 ps
T871 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.274726298 Mar 24 03:20:49 PM PDT 24 Mar 24 03:27:01 PM PDT 24 3871092896 ps
T872 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.615603670 Mar 24 03:22:00 PM PDT 24 Mar 24 03:36:39 PM PDT 24 5858317128 ps
T873 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2211852441 Mar 24 03:54:47 PM PDT 24 Mar 24 04:01:55 PM PDT 24 4652581000 ps
T874 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4082630730 Mar 24 03:38:46 PM PDT 24 Mar 24 03:43:27 PM PDT 24 3213760800 ps
T875 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.583007686 Mar 24 03:45:20 PM PDT 24 Mar 24 03:50:12 PM PDT 24 2859765734 ps
T218 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4178667874 Mar 24 03:20:52 PM PDT 24 Mar 24 03:36:05 PM PDT 24 4424148180 ps
T876 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3916147770 Mar 24 03:21:54 PM PDT 24 Mar 24 03:41:32 PM PDT 24 6003428488 ps
T877 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4238959994 Mar 24 03:23:58 PM PDT 24 Mar 24 03:36:29 PM PDT 24 4427742500 ps
T489 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3961017387 Mar 24 03:51:37 PM PDT 24 Mar 24 04:00:51 PM PDT 24 5096804516 ps
T878 /workspace/coverage/default/4.chip_tap_straps_rma.3382959530 Mar 24 03:47:33 PM PDT 24 Mar 24 03:52:55 PM PDT 24 3826874618 ps
T879 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287674767 Mar 24 03:56:05 PM PDT 24 Mar 24 04:02:54 PM PDT 24 3637393976 ps
T880 /workspace/coverage/default/1.chip_sw_edn_kat.2180850349 Mar 24 03:33:31 PM PDT 24 Mar 24 03:47:47 PM PDT 24 2929447712 ps
T881 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3035569782 Mar 24 03:42:12 PM PDT 24 Mar 24 04:14:06 PM PDT 24 8989744820 ps
T882 /workspace/coverage/default/1.rom_e2e_smoke.2504650530 Mar 24 03:40:12 PM PDT 24 Mar 24 04:14:40 PM PDT 24 9347859456 ps
T883 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3053726743 Mar 24 03:22:51 PM PDT 24 Mar 24 03:37:07 PM PDT 24 4803195580 ps
T884 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.817869022 Mar 24 03:48:14 PM PDT 24 Mar 24 03:52:43 PM PDT 24 2199050000 ps
T885 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3690422224 Mar 24 03:44:47 PM PDT 24 Mar 24 03:53:02 PM PDT 24 3998341037 ps
T886 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3610843298 Mar 24 03:54:46 PM PDT 24 Mar 24 04:02:37 PM PDT 24 4879534704 ps
T486 /workspace/coverage/default/70.chip_sw_all_escalation_resets.1807644219 Mar 24 03:55:20 PM PDT 24 Mar 24 04:05:08 PM PDT 24 6404253908 ps
T467 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.312544140 Mar 24 03:52:58 PM PDT 24 Mar 24 03:58:07 PM PDT 24 3512145020 ps
T887 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3022470669 Mar 24 03:30:23 PM PDT 24 Mar 24 03:40:50 PM PDT 24 4254407048 ps
T474 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.729062 Mar 24 03:52:31 PM PDT 24 Mar 24 03:58:08 PM PDT 24 3868299672 ps
T888 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1519425178 Mar 24 03:33:53 PM PDT 24 Mar 24 04:06:06 PM PDT 24 8101799076 ps
T889 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2184982308 Mar 24 03:42:11 PM PDT 24 Mar 24 04:00:10 PM PDT 24 6188236990 ps
T890 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3437510567 Mar 24 03:19:39 PM PDT 24 Mar 24 04:50:34 PM PDT 24 50277529032 ps
T891 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.276882779 Mar 24 03:40:18 PM PDT 24 Mar 24 03:42:53 PM PDT 24 3439761374 ps
T892 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2464476822 Mar 24 03:20:10 PM PDT 24 Mar 24 03:24:17 PM PDT 24 2875751672 ps
T484 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3207171203 Mar 24 03:53:10 PM PDT 24 Mar 24 04:03:53 PM PDT 24 4254307496 ps
T893 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4221864244 Mar 24 03:21:11 PM PDT 24 Mar 24 03:31:52 PM PDT 24 7045185680 ps
T894 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1413258231 Mar 24 03:40:47 PM PDT 24 Mar 24 03:42:50 PM PDT 24 2434418110 ps
T895 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.349729560 Mar 24 03:38:22 PM PDT 24 Mar 24 03:42:13 PM PDT 24 2475471768 ps
T896 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2859593782 Mar 24 03:21:09 PM PDT 24 Mar 24 03:28:54 PM PDT 24 5324311524 ps
T264 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2896329109 Mar 24 03:35:59 PM PDT 24 Mar 24 03:41:51 PM PDT 24 3479721244 ps
T897 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3700694025 Mar 24 03:22:02 PM PDT 24 Mar 24 03:49:03 PM PDT 24 11874958914 ps
T898 /workspace/coverage/default/0.chip_sw_usbdev_stream.135686564 Mar 24 03:22:04 PM PDT 24 Mar 24 04:31:30 PM PDT 24 18954101112 ps
T375 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703619182 Mar 24 03:24:25 PM PDT 24 Mar 24 03:32:02 PM PDT 24 18819011570 ps
T899 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3356238748 Mar 24 03:27:09 PM PDT 24 Mar 24 03:32:18 PM PDT 24 3167489080 ps
T900 /workspace/coverage/default/0.chip_sw_hmac_enc.3463009060 Mar 24 03:22:03 PM PDT 24 Mar 24 03:27:39 PM PDT 24 2831612830 ps
T50 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.546394143 Mar 24 03:36:49 PM PDT 24 Mar 24 03:46:37 PM PDT 24 3844902760 ps
T901 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2944310401 Mar 24 03:24:10 PM PDT 24 Mar 24 03:29:08 PM PDT 24 3623755781 ps
T902 /workspace/coverage/default/0.chip_sival_flash_info_access.3658288631 Mar 24 03:19:06 PM PDT 24 Mar 24 03:22:40 PM PDT 24 2825076280 ps
T903 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1603618315 Mar 24 03:26:57 PM PDT 24 Mar 24 03:43:29 PM PDT 24 4954536800 ps
T58 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2119295550 Mar 24 03:35:21 PM PDT 24 Mar 24 03:42:50 PM PDT 24 4578038648 ps
T904 /workspace/coverage/default/1.chip_tap_straps_rma.1568366092 Mar 24 03:35:38 PM PDT 24 Mar 24 03:38:23 PM PDT 24 3397425122 ps
T905 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4267675045 Mar 24 03:34:46 PM PDT 24 Mar 24 03:48:50 PM PDT 24 5275885116 ps
T906 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2805007446 Mar 24 03:39:00 PM PDT 24 Mar 24 03:58:53 PM PDT 24 5208102402 ps
T907 /workspace/coverage/default/0.chip_sw_example_concurrency.2800004708 Mar 24 03:21:04 PM PDT 24 Mar 24 03:25:05 PM PDT 24 2949245410 ps
T457 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2406502236 Mar 24 03:56:36 PM PDT 24 Mar 24 04:07:40 PM PDT 24 4690999368 ps
T366 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4066125907 Mar 24 03:43:51 PM PDT 24 Mar 24 04:03:14 PM PDT 24 6248484312 ps
T908 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4193822789 Mar 24 03:44:12 PM PDT 24 Mar 24 03:52:18 PM PDT 24 4415927910 ps
T212 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2421851443 Mar 24 03:19:58 PM PDT 24 Mar 24 03:35:51 PM PDT 24 4666614232 ps
T909 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4149255007 Mar 24 03:32:19 PM PDT 24 Mar 24 04:33:35 PM PDT 24 18049626779 ps
T910 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3832717167 Mar 24 03:27:57 PM PDT 24 Mar 24 03:44:19 PM PDT 24 5624649359 ps
T911 /workspace/coverage/default/1.chip_sw_power_idle_load.2875206354 Mar 24 03:36:35 PM PDT 24 Mar 24 03:48:28 PM PDT 24 4597546724 ps
T912 /workspace/coverage/default/2.chip_sw_example_concurrency.3683177507 Mar 24 03:39:52 PM PDT 24 Mar 24 03:44:06 PM PDT 24 2174059078 ps
T913 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3074823509 Mar 24 03:41:07 PM PDT 24 Mar 24 04:28:04 PM PDT 24 29292627976 ps
T914 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1757833105 Mar 24 03:28:44 PM PDT 24 Mar 24 04:03:48 PM PDT 24 8212137292 ps
T497 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.795583486 Mar 24 03:52:32 PM PDT 24 Mar 24 03:58:30 PM PDT 24 3585376244 ps
T105 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.392867319 Mar 24 03:40:57 PM PDT 24 Mar 24 03:47:45 PM PDT 24 7447625720 ps
T517 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3900881426 Mar 24 03:48:54 PM PDT 24 Mar 24 04:02:27 PM PDT 24 5970242564 ps
T915 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2217408827 Mar 24 03:23:47 PM PDT 24 Mar 24 03:27:55 PM PDT 24 2680592250 ps
T916 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4053227609 Mar 24 03:32:42 PM PDT 24 Mar 24 03:36:03 PM PDT 24 2691784649 ps
T429 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2082366115 Mar 24 03:56:51 PM PDT 24 Mar 24 04:09:20 PM PDT 24 4704722468 ps
T917 /workspace/coverage/default/2.chip_sw_power_idle_load.1582945465 Mar 24 03:46:02 PM PDT 24 Mar 24 04:00:09 PM PDT 24 4581118474 ps
T487 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3704194794 Mar 24 03:52:18 PM PDT 24 Mar 24 04:02:31 PM PDT 24 5340846068 ps
T918 /workspace/coverage/default/64.chip_sw_all_escalation_resets.4249483138 Mar 24 03:53:50 PM PDT 24 Mar 24 04:04:24 PM PDT 24 5360628678 ps
T329 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2653292885 Mar 24 03:43:37 PM PDT 24 Mar 24 03:52:49 PM PDT 24 3690685768 ps
T919 /workspace/coverage/default/68.chip_sw_all_escalation_resets.919164317 Mar 24 03:55:53 PM PDT 24 Mar 24 04:04:29 PM PDT 24 5434013776 ps
T920 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.322645551 Mar 24 03:39:05 PM PDT 24 Mar 24 07:21:15 PM PDT 24 78753745332 ps
T921 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3032969994 Mar 24 03:30:24 PM PDT 24 Mar 24 04:10:02 PM PDT 24 8525425398 ps
T922 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1524351145 Mar 24 03:33:34 PM PDT 24 Mar 24 03:37:27 PM PDT 24 2819165664 ps
T424 /workspace/coverage/default/91.chip_sw_all_escalation_resets.4044203807 Mar 24 03:56:41 PM PDT 24 Mar 24 04:04:32 PM PDT 24 4053286136 ps
T923 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2098238436 Mar 24 03:30:50 PM PDT 24 Mar 24 04:08:52 PM PDT 24 8207562056 ps
T924 /workspace/coverage/default/2.chip_sw_example_manufacturer.1915462038 Mar 24 03:40:07 PM PDT 24 Mar 24 03:43:41 PM PDT 24 3194430100 ps
T925 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.25141064 Mar 24 03:41:15 PM PDT 24 Mar 24 04:30:39 PM PDT 24 20718227060 ps
T66 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.983814700 Mar 24 03:44:34 PM PDT 24 Mar 24 04:06:05 PM PDT 24 18265711400 ps
T926 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.358405035 Mar 24 03:50:37 PM PDT 24 Mar 24 04:00:21 PM PDT 24 3859018205 ps
T490 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3692613755 Mar 24 03:50:43 PM PDT 24 Mar 24 04:03:32 PM PDT 24 5072788388 ps
T518 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3957938224 Mar 24 03:55:48 PM PDT 24 Mar 24 04:05:12 PM PDT 24 5369284676 ps
T927 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2402550349 Mar 24 03:33:19 PM PDT 24 Mar 24 03:41:18 PM PDT 24 3788037570 ps
T928 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.993490591 Mar 24 03:21:04 PM PDT 24 Mar 24 03:41:10 PM PDT 24 8869855136 ps
T186 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1804566576 Mar 24 03:19:51 PM PDT 24 Mar 24 03:23:05 PM PDT 24 3130538289 ps
T509 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.178279642 Mar 24 03:51:48 PM PDT 24 Mar 24 03:58:39 PM PDT 24 3378245936 ps
T235 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4176780454 Mar 24 03:30:26 PM PDT 24 Mar 24 03:34:41 PM PDT 24 2685724708 ps
T929 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909044307 Mar 24 03:54:21 PM PDT 24 Mar 24 04:00:10 PM PDT 24 3831163830 ps
T930 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.705993336 Mar 24 03:45:42 PM PDT 24 Mar 24 03:55:32 PM PDT 24 4559259844 ps
T931 /workspace/coverage/default/1.chip_sw_flash_init.3973675721 Mar 24 03:27:36 PM PDT 24 Mar 24 04:04:58 PM PDT 24 23853271300 ps
T488 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238282058 Mar 24 03:53:21 PM PDT 24 Mar 24 03:59:58 PM PDT 24 4073106600 ps
T932 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4028687481 Mar 24 03:41:03 PM PDT 24 Mar 24 03:50:42 PM PDT 24 5617720584 ps
T124 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1242012856 Mar 24 03:21:00 PM PDT 24 Mar 24 05:10:43 PM PDT 24 31655969460 ps
T933 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1722495997 Mar 24 03:29:55 PM PDT 24 Mar 24 03:46:02 PM PDT 24 5586461456 ps
T172 /workspace/coverage/default/1.chip_plic_all_irqs_0.2624755285 Mar 24 03:38:51 PM PDT 24 Mar 24 04:01:05 PM PDT 24 6555113700 ps
T934 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3190397145 Mar 24 03:27:28 PM PDT 24 Mar 24 03:35:33 PM PDT 24 6084398042 ps
T367 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.767697758 Mar 24 03:33:54 PM PDT 24 Mar 24 04:02:39 PM PDT 24 7425854350 ps
T935 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4228390953 Mar 24 03:43:24 PM PDT 24 Mar 24 03:50:14 PM PDT 24 3140118920 ps
T520 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800474109 Mar 24 03:50:29 PM PDT 24 Mar 24 03:56:01 PM PDT 24 3207799976 ps
T936 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2261806167 Mar 24 03:22:18 PM PDT 24 Mar 24 03:33:12 PM PDT 24 5093176680 ps
T378 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.853060643 Mar 24 03:29:19 PM PDT 24 Mar 24 03:38:32 PM PDT 24 4562341008 ps
T937 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2103657553 Mar 24 03:26:37 PM PDT 24 Mar 24 03:32:54 PM PDT 24 2846664056 ps
T938 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.658995966 Mar 24 03:43:50 PM PDT 24 Mar 24 03:51:59 PM PDT 24 3669891528 ps
T939 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456362447 Mar 24 03:53:27 PM PDT 24 Mar 24 03:58:43 PM PDT 24 4120575708 ps
T940 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2222622376 Mar 24 03:50:05 PM PDT 24 Mar 24 03:59:30 PM PDT 24 4943428300 ps
T485 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686118535 Mar 24 03:55:14 PM PDT 24 Mar 24 04:01:15 PM PDT 24 3802366384 ps
T941 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.52515700 Mar 24 03:38:44 PM PDT 24 Mar 24 03:47:47 PM PDT 24 5035353528 ps
T278 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2175244304 Mar 24 03:48:52 PM PDT 24 Mar 24 03:58:30 PM PDT 24 5985579764 ps
T942 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.857722692 Mar 24 03:48:51 PM PDT 24 Mar 24 03:53:56 PM PDT 24 2692115256 ps
T943 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2321710464 Mar 24 03:45:02 PM PDT 24 Mar 24 03:50:16 PM PDT 24 2671423214 ps
T944 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3399008579 Mar 24 03:56:12 PM PDT 24 Mar 24 04:04:05 PM PDT 24 4396198364 ps
T945 /workspace/coverage/default/2.chip_sw_edn_kat.3774053308 Mar 24 03:41:49 PM PDT 24 Mar 24 03:53:08 PM PDT 24 3677265178 ps
T27 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2942050370 Mar 24 03:12:22 PM PDT 24 Mar 24 03:17:51 PM PDT 24 4501824868 ps
T28 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2479904493 Mar 24 03:12:22 PM PDT 24 Mar 24 03:17:01 PM PDT 24 5777253875 ps
T29 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3897033507 Mar 24 03:12:24 PM PDT 24 Mar 24 03:18:17 PM PDT 24 4701275016 ps
T33 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3120781847 Mar 24 03:12:26 PM PDT 24 Mar 24 03:16:24 PM PDT 24 3661062240 ps
T419 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.416558801 Mar 24 03:12:25 PM PDT 24 Mar 24 03:15:28 PM PDT 24 4209247538 ps
T420 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2468304837 Mar 24 03:12:26 PM PDT 24 Mar 24 03:16:22 PM PDT 24 4077925984 ps
T946 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.544977679 Mar 24 03:12:25 PM PDT 24 Mar 24 03:17:32 PM PDT 24 4922084510 ps
T947 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.438458084 Mar 24 03:12:21 PM PDT 24 Mar 24 03:16:32 PM PDT 24 4556687520 ps
T948 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1337577864 Mar 24 03:12:27 PM PDT 24 Mar 24 03:19:29 PM PDT 24 4844723098 ps
T949 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4245583464 Mar 24 03:12:24 PM PDT 24 Mar 24 03:16:56 PM PDT 24 5364260376 ps

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1285879573
Short name T1
Test name
Test status
Simulation time 22387913580 ps
CPU time 1719.09 seconds
Started Mar 24 03:21:34 PM PDT 24
Finished Mar 24 03:50:14 PM PDT 24
Peak memory 601332 kb
Host smart-ef35e11a-4af7-4239-9ce8-9f4d6422b811
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1285879573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1285879573
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.3816684808
Short name T76
Test name
Test status
Simulation time 3105987464 ps
CPU time 392.68 seconds
Started Mar 24 03:41:04 PM PDT 24
Finished Mar 24 03:47:37 PM PDT 24
Peak memory 600004 kb
Host smart-1bdf6ac7-c398-40bb-bd3c-03f7aa53a59d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816684808 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.chip_sw_alert_test.3816684808
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.4021436106
Short name T91
Test name
Test status
Simulation time 5723223300 ps
CPU time 1039.34 seconds
Started Mar 24 03:21:15 PM PDT 24
Finished Mar 24 03:38:35 PM PDT 24
Peak memory 599928 kb
Host smart-80d802d3-41dd-44c9-af96-86c83511cd34
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021436106 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_0.4021436106
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.3481682834
Short name T42
Test name
Test status
Simulation time 17365471861 ps
CPU time 2082.84 seconds
Started Mar 24 03:27:56 PM PDT 24
Finished Mar 24 04:02:39 PM PDT 24
Peak memory 594284 kb
Host smart-62085645-395b-4891-a68d-dd7de53129e3
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481682834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c
hip_jtag_csr_rw.3481682834
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2479904493
Short name T28
Test name
Test status
Simulation time 5777253875 ps
CPU time 278.81 seconds
Started Mar 24 03:12:22 PM PDT 24
Finished Mar 24 03:17:01 PM PDT 24
Peak memory 637612 kb
Host smart-76c10e96-ac5a-42eb-80fc-3947aa102f37
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479904493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.2479904493
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1348443953
Short name T7
Test name
Test status
Simulation time 2852267853 ps
CPU time 317.44 seconds
Started Mar 24 03:38:13 PM PDT 24
Finished Mar 24 03:43:31 PM PDT 24
Peak memory 599552 kb
Host smart-f3368c42-1374-4c86-adc0-30f86bc186ed
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348
443953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1348443953
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1169811508
Short name T4
Test name
Test status
Simulation time 5048522500 ps
CPU time 516.17 seconds
Started Mar 24 03:41:55 PM PDT 24
Finished Mar 24 03:50:32 PM PDT 24
Peak memory 600284 kb
Host smart-d6b59851-ec0d-4772-84f0-4333fa2ba161
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11
69811508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1169811508
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3386010877
Short name T120
Test name
Test status
Simulation time 50175821700 ps
CPU time 5976.92 seconds
Started Mar 24 03:30:12 PM PDT 24
Finished Mar 24 05:09:50 PM PDT 24
Peak memory 607360 kb
Host smart-0066e3e4-8514-401c-8a9d-a9843a6745d0
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386010877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi
p_sw_lc_walkthrough_prod.3386010877
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2162516780
Short name T68
Test name
Test status
Simulation time 3324642200 ps
CPU time 242.02 seconds
Started Mar 24 03:20:56 PM PDT 24
Finished Mar 24 03:24:59 PM PDT 24
Peak memory 599956 kb
Host smart-ab9eeec7-7bdd-4bc1-abbb-ddae822cab3b
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2162516780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2162516780
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3303118295
Short name T318
Test name
Test status
Simulation time 4102163150 ps
CPU time 509.7 seconds
Started Mar 24 03:45:30 PM PDT 24
Finished Mar 24 03:54:00 PM PDT 24
Peak memory 600464 kb
Host smart-898d1299-631c-47ef-8fc9-bd5fe7a2d2e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
18295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3303118295
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.2806547947
Short name T175
Test name
Test status
Simulation time 5008143100 ps
CPU time 804.24 seconds
Started Mar 24 03:35:55 PM PDT 24
Finished Mar 24 03:49:20 PM PDT 24
Peak memory 599996 kb
Host smart-9a64940a-2f63-477d-8a54-5a7610123e5f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806547947 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.2806547947
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.4014856101
Short name T15
Test name
Test status
Simulation time 4115088520 ps
CPU time 263.27 seconds
Started Mar 24 03:20:00 PM PDT 24
Finished Mar 24 03:24:24 PM PDT 24
Peak memory 599876 kb
Host smart-37a25067-5fd2-4228-9499-deb59c95253e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014856101 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.4014856101
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2966622841
Short name T55
Test name
Test status
Simulation time 11366123090 ps
CPU time 1701.11 seconds
Started Mar 24 03:32:51 PM PDT 24
Finished Mar 24 04:01:13 PM PDT 24
Peak memory 601148 kb
Host smart-7a9ffeba-b02b-4259-9182-82000cdcad5c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966622841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.2966622841
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.3223104277
Short name T146
Test name
Test status
Simulation time 4148686552 ps
CPU time 918.5 seconds
Started Mar 24 03:21:15 PM PDT 24
Finished Mar 24 03:36:34 PM PDT 24
Peak memory 600060 kb
Host smart-20c6ea8f-2684-40c2-8f82-31448487d24e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223104277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
auto_mode.3223104277
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.4122055265
Short name T60
Test name
Test status
Simulation time 5348953000 ps
CPU time 355.43 seconds
Started Mar 24 03:39:36 PM PDT 24
Finished Mar 24 03:45:32 PM PDT 24
Peak memory 599924 kb
Host smart-91c178e9-1b44-4b02-9041-1f271abe0c8f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122055265
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.4122055265
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1934892979
Short name T64
Test name
Test status
Simulation time 4862523700 ps
CPU time 426.27 seconds
Started Mar 24 03:21:50 PM PDT 24
Finished Mar 24 03:28:57 PM PDT 24
Peak memory 600208 kb
Host smart-6c2c2155-8c08-4f79-a13a-3007b6a3142a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934892979
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1934892979
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1995126303
Short name T6
Test name
Test status
Simulation time 8671730946 ps
CPU time 2431.22 seconds
Started Mar 24 03:29:44 PM PDT 24
Finished Mar 24 04:10:16 PM PDT 24
Peak memory 599860 kb
Host smart-57045220-2ee0-4a01-835f-bf8bb7839533
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995126303 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1995126303
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.337948571
Short name T89
Test name
Test status
Simulation time 4492967702 ps
CPU time 660.93 seconds
Started Mar 24 03:44:09 PM PDT 24
Finished Mar 24 03:55:11 PM PDT 24
Peak memory 600024 kb
Host smart-d6863c47-ec90-4732-b7de-938c1c00a28f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337948571 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_10.337948571
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2846978373
Short name T347
Test name
Test status
Simulation time 9500927797 ps
CPU time 1309.74 seconds
Started Mar 24 03:21:14 PM PDT 24
Finished Mar 24 03:43:05 PM PDT 24
Peak memory 600444 kb
Host smart-a00a5716-3c66-4828-9d89-b36b458eb8c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846
978373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2846978373
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.132934956
Short name T12
Test name
Test status
Simulation time 2840928446 ps
CPU time 318.27 seconds
Started Mar 24 03:39:18 PM PDT 24
Finished Mar 24 03:44:37 PM PDT 24
Peak memory 598944 kb
Host smart-f947883c-004b-45a2-ad09-f5d87c5d5934
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132934956 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.132934956
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3022819196
Short name T253
Test name
Test status
Simulation time 6081950176 ps
CPU time 691.44 seconds
Started Mar 24 03:45:33 PM PDT 24
Finished Mar 24 03:57:05 PM PDT 24
Peak memory 600104 kb
Host smart-3a52ecc5-e2af-4516-9dd5-df526675df95
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022819196 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3022819196
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.3865917945
Short name T24
Test name
Test status
Simulation time 3977528390 ps
CPU time 553.9 seconds
Started Mar 24 03:39:49 PM PDT 24
Finished Mar 24 03:49:03 PM PDT 24
Peak memory 599856 kb
Host smart-6f3f43f3-7741-418e-b7b0-10ecbc1bb2f9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865917945 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_gpio.3865917945
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.229769287
Short name T46
Test name
Test status
Simulation time 3899846208 ps
CPU time 365.47 seconds
Started Mar 24 03:20:58 PM PDT 24
Finished Mar 24 03:27:05 PM PDT 24
Peak memory 607048 kb
Host smart-1876a805-4d1a-4379-90c9-27e0153ce721
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
29769287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.229769287
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3422554305
Short name T9
Test name
Test status
Simulation time 2479431044 ps
CPU time 231.59 seconds
Started Mar 24 03:21:36 PM PDT 24
Finished Mar 24 03:25:28 PM PDT 24
Peak memory 599592 kb
Host smart-9e6df661-735b-4e94-96fb-0ca8dd1eea0a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422
554305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3422554305
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3086489570
Short name T159
Test name
Test status
Simulation time 6891883500 ps
CPU time 1002.96 seconds
Started Mar 24 03:35:31 PM PDT 24
Finished Mar 24 03:52:14 PM PDT 24
Peak memory 600056 kb
Host smart-8de102b1-58e0-4e14-877d-9a765178a352
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864895
70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3086489570
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.869041479
Short name T74
Test name
Test status
Simulation time 42785531972 ps
CPU time 5023.65 seconds
Started Mar 24 03:27:55 PM PDT 24
Finished Mar 24 04:51:40 PM PDT 24
Peak memory 607324 kb
Host smart-79baa44e-5dc3-4ec7-af4c-d8a216c56ccf
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=869041479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.869041479
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1093876105
Short name T152
Test name
Test status
Simulation time 4611464480 ps
CPU time 413.36 seconds
Started Mar 24 03:21:18 PM PDT 24
Finished Mar 24 03:28:11 PM PDT 24
Peak memory 600048 kb
Host smart-18cfc758-30be-4979-9c1c-d5f459d2057e
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10938761
05 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1093876105
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.470953587
Short name T8
Test name
Test status
Simulation time 2958303154 ps
CPU time 367.01 seconds
Started Mar 24 03:29:25 PM PDT 24
Finished Mar 24 03:35:33 PM PDT 24
Peak memory 599844 kb
Host smart-6c4caabc-07d9-4f3e-bdca-b35620b02d96
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4709
53587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.470953587
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1606811196
Short name T111
Test name
Test status
Simulation time 5314035449 ps
CPU time 816.93 seconds
Started Mar 24 03:38:23 PM PDT 24
Finished Mar 24 03:52:02 PM PDT 24
Peak memory 600428 kb
Host smart-a936d5ec-999b-4a73-8c37-6db6ea434ff4
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606811196 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1606811196
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.295766277
Short name T258
Test name
Test status
Simulation time 4753062650 ps
CPU time 510.96 seconds
Started Mar 24 03:53:14 PM PDT 24
Finished Mar 24 04:01:46 PM PDT 24
Peak memory 636212 kb
Host smart-3e11c8b7-47ad-49e2-849a-27cb7bddf373
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
295766277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.295766277
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.1745819555
Short name T190
Test name
Test status
Simulation time 5197953208 ps
CPU time 607.87 seconds
Started Mar 24 03:53:25 PM PDT 24
Finished Mar 24 04:03:33 PM PDT 24
Peak memory 607368 kb
Host smart-a9339e74-9ff8-49d3-9a87-57e1244cfd81
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1745819555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1745819555
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.3092981783
Short name T70
Test name
Test status
Simulation time 9287627878 ps
CPU time 950.8 seconds
Started Mar 24 03:13:17 PM PDT 24
Finished Mar 24 03:29:08 PM PDT 24
Peak memory 593324 kb
Host smart-09694c85-46ac-4ed9-bc4c-eaa1f04e34c4
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092981783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_jtag_csr_rw.3092981783
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2913710822
Short name T382
Test name
Test status
Simulation time 2473484112 ps
CPU time 200.48 seconds
Started Mar 24 03:47:01 PM PDT 24
Finished Mar 24 03:50:23 PM PDT 24
Peak memory 631084 kb
Host smart-c580416a-08f1-4bcc-abaa-639ede6c1473
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913710822 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2913710822
Directory /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.2847329879
Short name T230
Test name
Test status
Simulation time 4402273510 ps
CPU time 643.09 seconds
Started Mar 24 03:51:54 PM PDT 24
Finished Mar 24 04:02:37 PM PDT 24
Peak memory 636548 kb
Host smart-66e224ce-a6ef-4621-ba51-76d9b04200ad
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2847329879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2847329879
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.167460345
Short name T126
Test name
Test status
Simulation time 3717007080 ps
CPU time 393.6 seconds
Started Mar 24 03:51:36 PM PDT 24
Finished Mar 24 03:58:10 PM PDT 24
Peak memory 636468 kb
Host smart-00837ef9-2b7c-439a-8249-6d26dd192636
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167460345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s
w_alert_handler_lpg_sleep_mode_alerts.167460345
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.2725648639
Short name T69
Test name
Test status
Simulation time 4950167680 ps
CPU time 465.13 seconds
Started Mar 24 03:59:27 PM PDT 24
Finished Mar 24 04:07:13 PM PDT 24
Peak memory 635672 kb
Host smart-e34330e3-0bf7-4532-8b3b-59a516a2a24d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2725648639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2725648639
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3451992755
Short name T47
Test name
Test status
Simulation time 5487916676 ps
CPU time 449.55 seconds
Started Mar 24 03:22:52 PM PDT 24
Finished Mar 24 03:30:22 PM PDT 24
Peak memory 607116 kb
Host smart-6cc69c4c-6111-46ab-8db3-2985ab13b0b3
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345199
2755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3451992755
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2344346753
Short name T98
Test name
Test status
Simulation time 5491765934 ps
CPU time 703.27 seconds
Started Mar 24 03:32:57 PM PDT 24
Finished Mar 24 03:44:40 PM PDT 24
Peak memory 600332 kb
Host smart-223cc9c8-eb48-4065-922d-519d68436524
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344346753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr
ng_lc_hw_debug_en_test.2344346753
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.1707558977
Short name T238
Test name
Test status
Simulation time 4033505120 ps
CPU time 358.26 seconds
Started Mar 24 03:36:23 PM PDT 24
Finished Mar 24 03:42:21 PM PDT 24
Peak memory 599540 kb
Host smart-372320e8-3585-4321-8cfb-23cd224430a6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707558977 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1707558977
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.365927413
Short name T48
Test name
Test status
Simulation time 8998433515 ps
CPU time 1138.03 seconds
Started Mar 24 03:37:38 PM PDT 24
Finished Mar 24 03:56:37 PM PDT 24
Peak memory 593040 kb
Host smart-2a308506-ba80-4b70-96f1-22517357ac14
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365927413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch
ip_jtag_csr_rw.365927413
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824097943
Short name T178
Test name
Test status
Simulation time 3301269856 ps
CPU time 339.11 seconds
Started Mar 24 03:51:39 PM PDT 24
Finished Mar 24 03:57:19 PM PDT 24
Peak memory 636040 kb
Host smart-96e69c7b-8788-4a1e-ad04-a3a3e1235a7d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824097943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1824097943
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/83.chip_sw_all_escalation_resets.3470510290
Short name T73
Test name
Test status
Simulation time 4628962930 ps
CPU time 534.97 seconds
Started Mar 24 03:55:48 PM PDT 24
Finished Mar 24 04:04:43 PM PDT 24
Peak memory 636236 kb
Host smart-5c3a746f-08d5-45fc-ad20-91d78c32837e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3470510290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3470510290
Directory /workspace/83.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086271153
Short name T240
Test name
Test status
Simulation time 3849056122 ps
CPU time 363.82 seconds
Started Mar 24 03:51:35 PM PDT 24
Finished Mar 24 03:57:39 PM PDT 24
Peak memory 636376 kb
Host smart-3d65a37b-73f5-488b-beb3-ee35a166b6b2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086271153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2086271153
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.1688643293
Short name T52
Test name
Test status
Simulation time 4204465670 ps
CPU time 519.82 seconds
Started Mar 24 03:52:26 PM PDT 24
Finished Mar 24 04:01:05 PM PDT 24
Peak memory 634948 kb
Host smart-1ffa1fc0-42bc-4891-ac11-f0e1243c67d1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1688643293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1688643293
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.596407705
Short name T115
Test name
Test status
Simulation time 5198726336 ps
CPU time 561.9 seconds
Started Mar 24 03:59:14 PM PDT 24
Finished Mar 24 04:08:36 PM PDT 24
Peak memory 636332 kb
Host smart-faea1c86-7d31-46aa-9f32-a68574822215
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
596407705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.596407705
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_all_escalation_resets.3395186789
Short name T362
Test name
Test status
Simulation time 5155787760 ps
CPU time 565.02 seconds
Started Mar 24 03:55:01 PM PDT 24
Finished Mar 24 04:04:27 PM PDT 24
Peak memory 635460 kb
Host smart-3585a812-57c1-4232-a603-a3090231a38b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3395186789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3395186789
Directory /workspace/72.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.4077950190
Short name T228
Test name
Test status
Simulation time 5090945428 ps
CPU time 664.93 seconds
Started Mar 24 03:51:55 PM PDT 24
Finished Mar 24 04:03:01 PM PDT 24
Peak memory 636584 kb
Host smart-0abc0ffe-f24d-4563-bff2-b2e60748a47c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4077950190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.4077950190
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1746296200
Short name T459
Test name
Test status
Simulation time 4067448634 ps
CPU time 371.36 seconds
Started Mar 24 03:23:55 PM PDT 24
Finished Mar 24 03:30:07 PM PDT 24
Peak memory 636048 kb
Host smart-6d1528a3-0851-46ce-907a-47211506f5a0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746296200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1746296200
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.715150638
Short name T421
Test name
Test status
Simulation time 4746264504 ps
CPU time 497.18 seconds
Started Mar 24 03:20:02 PM PDT 24
Finished Mar 24 03:28:20 PM PDT 24
Peak memory 636356 kb
Host smart-bfcf2cca-bc98-4dd1-9910-b47c44e23b1f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
715150638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.715150638
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1332247950
Short name T454
Test name
Test status
Simulation time 3424395576 ps
CPU time 401.74 seconds
Started Mar 24 03:33:11 PM PDT 24
Finished Mar 24 03:39:54 PM PDT 24
Peak memory 635880 kb
Host smart-39a2d8ee-7137-4c21-b681-e0ca64feaf0f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332247950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1332247950
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.487411664
Short name T273
Test name
Test status
Simulation time 5317717320 ps
CPU time 465.44 seconds
Started Mar 24 03:26:07 PM PDT 24
Finished Mar 24 03:33:53 PM PDT 24
Peak memory 636384 kb
Host smart-ede3e012-fe34-4cd1-bd2f-7b3386f68ab2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
487411664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.487411664
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.564156283
Short name T445
Test name
Test status
Simulation time 3871903562 ps
CPU time 368.78 seconds
Started Mar 24 03:49:59 PM PDT 24
Finished Mar 24 03:56:08 PM PDT 24
Peak memory 636248 kb
Host smart-9bc961d5-e955-48ff-9f57-043da18ee5a7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564156283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s
w_alert_handler_lpg_sleep_mode_alerts.564156283
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.101224916
Short name T208
Test name
Test status
Simulation time 5588658100 ps
CPU time 718.27 seconds
Started Mar 24 03:49:21 PM PDT 24
Finished Mar 24 04:01:19 PM PDT 24
Peak memory 636332 kb
Host smart-44efb0c3-f9ca-4a37-b3d1-ca071164a942
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
101224916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.101224916
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800474109
Short name T520
Test name
Test status
Simulation time 3207799976 ps
CPU time 331.87 seconds
Started Mar 24 03:50:29 PM PDT 24
Finished Mar 24 03:56:01 PM PDT 24
Peak memory 636044 kb
Host smart-05904f50-1549-47f7-b3bd-f3658ad0b619
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800474109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2800474109
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.1439622986
Short name T428
Test name
Test status
Simulation time 5140152724 ps
CPU time 547.83 seconds
Started Mar 24 03:48:51 PM PDT 24
Finished Mar 24 03:57:59 PM PDT 24
Peak memory 636216 kb
Host smart-4139f50d-65d9-4b2b-93a8-9cbc97fe27ab
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1439622986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1439622986
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414278767
Short name T207
Test name
Test status
Simulation time 3945801960 ps
CPU time 366.61 seconds
Started Mar 24 03:50:51 PM PDT 24
Finished Mar 24 03:56:58 PM PDT 24
Peak memory 636116 kb
Host smart-f46781d5-695b-420d-b70f-2197f650f8f0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414278767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3414278767
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.356698347
Short name T478
Test name
Test status
Simulation time 5612986248 ps
CPU time 561.44 seconds
Started Mar 24 03:50:42 PM PDT 24
Finished Mar 24 04:00:04 PM PDT 24
Peak memory 636336 kb
Host smart-436a042b-8da0-4540-8ef0-8e80d87cbd06
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
356698347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.356698347
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.375278615
Short name T495
Test name
Test status
Simulation time 3124194544 ps
CPU time 431.64 seconds
Started Mar 24 03:50:10 PM PDT 24
Finished Mar 24 03:57:22 PM PDT 24
Peak memory 635900 kb
Host smart-6b5cdf46-d9c8-459a-b65f-c65e4c8383e1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375278615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s
w_alert_handler_lpg_sleep_mode_alerts.375278615
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4239137083
Short name T257
Test name
Test status
Simulation time 3828872722 ps
CPU time 534.23 seconds
Started Mar 24 03:51:27 PM PDT 24
Finished Mar 24 04:00:22 PM PDT 24
Peak memory 636108 kb
Host smart-01804f08-cf7a-436a-bda0-ff836caa302a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239137083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4239137083
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.3692613755
Short name T490
Test name
Test status
Simulation time 5072788388 ps
CPU time 768.91 seconds
Started Mar 24 03:50:43 PM PDT 24
Finished Mar 24 04:03:32 PM PDT 24
Peak memory 636384 kb
Host smart-5117741d-3993-457c-a03a-8b793db3a496
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3692613755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3692613755
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.510163091
Short name T450
Test name
Test status
Simulation time 3981977460 ps
CPU time 357.59 seconds
Started Mar 24 03:51:27 PM PDT 24
Finished Mar 24 03:57:25 PM PDT 24
Peak memory 636232 kb
Host smart-1c53e4ee-8258-435d-9e79-19da68ae6739
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510163091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s
w_alert_handler_lpg_sleep_mode_alerts.510163091
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.4157104570
Short name T164
Test name
Test status
Simulation time 5784909350 ps
CPU time 477.4 seconds
Started Mar 24 03:51:11 PM PDT 24
Finished Mar 24 03:59:09 PM PDT 24
Peak memory 635356 kb
Host smart-aa87916f-7f5b-49ac-aeb5-1f931aca71a9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4157104570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.4157104570
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373807856
Short name T512
Test name
Test status
Simulation time 3568867526 ps
CPU time 433.46 seconds
Started Mar 24 03:52:33 PM PDT 24
Finished Mar 24 03:59:46 PM PDT 24
Peak memory 636120 kb
Host smart-0fe3ee12-ae63-42a3-a8bf-0d90a2bfb577
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373807856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3373807856
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.3377729971
Short name T432
Test name
Test status
Simulation time 4116112148 ps
CPU time 576.82 seconds
Started Mar 24 03:51:14 PM PDT 24
Finished Mar 24 04:00:51 PM PDT 24
Peak memory 635892 kb
Host smart-1af0bd9c-e077-4fc8-9893-2ae3edcdaea5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3377729971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3377729971
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715266075
Short name T477
Test name
Test status
Simulation time 3751115270 ps
CPU time 344.35 seconds
Started Mar 24 03:50:00 PM PDT 24
Finished Mar 24 03:55:45 PM PDT 24
Peak memory 635952 kb
Host smart-234e13e8-db91-452f-9225-1e566da9f510
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715266075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1715266075
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.3704194794
Short name T487
Test name
Test status
Simulation time 5340846068 ps
CPU time 613.15 seconds
Started Mar 24 03:52:18 PM PDT 24
Finished Mar 24 04:02:31 PM PDT 24
Peak memory 635116 kb
Host smart-30c88a54-7ea2-474d-a10e-018a998503a8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3704194794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3704194794
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.688636758
Short name T813
Test name
Test status
Simulation time 4734745960 ps
CPU time 510.74 seconds
Started Mar 24 03:39:26 PM PDT 24
Finished Mar 24 03:47:58 PM PDT 24
Peak memory 636200 kb
Host smart-51a3b23b-d786-4991-a651-7c4869b2a022
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
688636758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.688636758
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181623356
Short name T482
Test name
Test status
Simulation time 4138163980 ps
CPU time 454.97 seconds
Started Mar 24 03:50:44 PM PDT 24
Finished Mar 24 03:58:19 PM PDT 24
Peak memory 636116 kb
Host smart-f6e9a9c1-d020-428f-b880-f44a09c8383c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181623356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4181623356
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679624986
Short name T496
Test name
Test status
Simulation time 3062757980 ps
CPU time 353.82 seconds
Started Mar 24 03:50:30 PM PDT 24
Finished Mar 24 03:56:24 PM PDT 24
Peak memory 636116 kb
Host smart-4fc7dccb-9e43-4938-bb00-88dbd77d4177
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679624986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3679624986
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.2480166511
Short name T370
Test name
Test status
Simulation time 4565693930 ps
CPU time 570.29 seconds
Started Mar 24 03:51:51 PM PDT 24
Finished Mar 24 04:01:22 PM PDT 24
Peak memory 636308 kb
Host smart-eb629686-8cb7-4b8a-8c52-9ea36c9498e0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2480166511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2480166511
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.806948203
Short name T452
Test name
Test status
Simulation time 5399152240 ps
CPU time 633.53 seconds
Started Mar 24 03:50:39 PM PDT 24
Finished Mar 24 04:01:13 PM PDT 24
Peak memory 635172 kb
Host smart-8a67a285-0c4e-46d0-a625-d33198a5435a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
806948203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.806948203
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.2835672725
Short name T270
Test name
Test status
Simulation time 5952085064 ps
CPU time 534.48 seconds
Started Mar 24 03:52:30 PM PDT 24
Finished Mar 24 04:01:25 PM PDT 24
Peak memory 636644 kb
Host smart-040776f3-a9cb-42d5-b684-2e0d314bd809
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2835672725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2835672725
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188441237
Short name T468
Test name
Test status
Simulation time 3916037488 ps
CPU time 387.27 seconds
Started Mar 24 03:52:36 PM PDT 24
Finished Mar 24 03:59:03 PM PDT 24
Peak memory 636076 kb
Host smart-33ea1b5f-fd48-47f5-b983-09ff6127ad88
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188441237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2188441237
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.3825738196
Short name T516
Test name
Test status
Simulation time 5537162398 ps
CPU time 710.15 seconds
Started Mar 24 03:51:58 PM PDT 24
Finished Mar 24 04:03:49 PM PDT 24
Peak memory 636264 kb
Host smart-139d9bc2-d20a-45a8-88bd-ae1ce189db0d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3825738196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3825738196
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.661819136
Short name T472
Test name
Test status
Simulation time 6192581464 ps
CPU time 595.07 seconds
Started Mar 24 03:52:33 PM PDT 24
Finished Mar 24 04:02:29 PM PDT 24
Peak memory 636276 kb
Host smart-e9e14141-5b84-4a19-83a0-84ad11d40748
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
661819136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.661819136
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203482068
Short name T171
Test name
Test status
Simulation time 4118381920 ps
CPU time 427 seconds
Started Mar 24 03:52:45 PM PDT 24
Finished Mar 24 03:59:52 PM PDT 24
Peak memory 636332 kb
Host smart-6fe4711c-1c78-49e4-8b62-bc7e5f461180
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203482068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3203482068
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.765030416
Short name T466
Test name
Test status
Simulation time 4183925176 ps
CPU time 528.55 seconds
Started Mar 24 03:51:24 PM PDT 24
Finished Mar 24 04:00:13 PM PDT 24
Peak memory 636244 kb
Host smart-a75c89f0-0ed4-404b-9980-a892d293088b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
765030416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.765030416
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189972802
Short name T356
Test name
Test status
Simulation time 4064508320 ps
CPU time 546.12 seconds
Started Mar 24 03:49:05 PM PDT 24
Finished Mar 24 03:58:12 PM PDT 24
Peak memory 636132 kb
Host smart-628f7f38-2dfb-44a3-b8a8-948663e61618
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189972802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3189972802
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.2761627574
Short name T470
Test name
Test status
Simulation time 4813648952 ps
CPU time 403.58 seconds
Started Mar 24 03:50:52 PM PDT 24
Finished Mar 24 03:57:36 PM PDT 24
Peak memory 636164 kb
Host smart-cda0a359-1906-4593-a6ee-ffda558af11f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2761627574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2761627574
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784027897
Short name T473
Test name
Test status
Simulation time 3456013832 ps
CPU time 382.65 seconds
Started Mar 24 03:51:45 PM PDT 24
Finished Mar 24 03:58:09 PM PDT 24
Peak memory 635904 kb
Host smart-4e7166de-2c6e-4b03-a5d1-48e017dcf90c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784027897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1784027897
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.201558313
Short name T463
Test name
Test status
Simulation time 3960440196 ps
CPU time 332.6 seconds
Started Mar 24 03:54:21 PM PDT 24
Finished Mar 24 03:59:54 PM PDT 24
Peak memory 636228 kb
Host smart-ebd7fa4c-3949-4a71-a3c0-70bd899c3b3e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201558313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s
w_alert_handler_lpg_sleep_mode_alerts.201558313
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.3207171203
Short name T484
Test name
Test status
Simulation time 4254307496 ps
CPU time 640.77 seconds
Started Mar 24 03:53:10 PM PDT 24
Finished Mar 24 04:03:53 PM PDT 24
Peak memory 635040 kb
Host smart-ccae297b-ad91-4f6c-8490-f19f13ef92c5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3207171203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3207171203
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.2356610270
Short name T504
Test name
Test status
Simulation time 4546523496 ps
CPU time 491.94 seconds
Started Mar 24 03:49:38 PM PDT 24
Finished Mar 24 03:57:50 PM PDT 24
Peak memory 636236 kb
Host smart-07acfd7a-c525-495d-9926-5d67ab3f672b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2356610270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2356610270
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336623486
Short name T493
Test name
Test status
Simulation time 3113252600 ps
CPU time 306.33 seconds
Started Mar 24 03:53:04 PM PDT 24
Finished Mar 24 03:58:11 PM PDT 24
Peak memory 636048 kb
Host smart-d04ac251-cee3-4d3e-9974-1c9a7172d3b8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336623486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3336623486
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978599617
Short name T299
Test name
Test status
Simulation time 3504052000 ps
CPU time 294.1 seconds
Started Mar 24 03:52:57 PM PDT 24
Finished Mar 24 03:57:51 PM PDT 24
Peak memory 635936 kb
Host smart-615a46e8-9939-41c8-8295-c02b04a1cd53
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978599617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1978599617
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.2039914591
Short name T455
Test name
Test status
Simulation time 5440303000 ps
CPU time 639.7 seconds
Started Mar 24 03:53:20 PM PDT 24
Finished Mar 24 04:04:00 PM PDT 24
Peak memory 635204 kb
Host smart-2160f595-8e3b-4b80-9f19-d94213d5d767
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2039914591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2039914591
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.359197215
Short name T373
Test name
Test status
Simulation time 5141179646 ps
CPU time 662.73 seconds
Started Mar 24 03:54:01 PM PDT 24
Finished Mar 24 04:05:05 PM PDT 24
Peak memory 635248 kb
Host smart-e2687fe8-0b13-4e49-b594-75356247defd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
359197215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.359197215
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519648438
Short name T501
Test name
Test status
Simulation time 3186720704 ps
CPU time 372.21 seconds
Started Mar 24 03:54:19 PM PDT 24
Finished Mar 24 04:00:33 PM PDT 24
Peak memory 636016 kb
Host smart-cbed81d8-58f2-4bdd-9f8b-ef9f0ad6929d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519648438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2519648438
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.178279642
Short name T509
Test name
Test status
Simulation time 3378245936 ps
CPU time 411.23 seconds
Started Mar 24 03:51:48 PM PDT 24
Finished Mar 24 03:58:39 PM PDT 24
Peak memory 636040 kb
Host smart-da5d1882-edb2-4477-920a-1f26ddaddea1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178279642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s
w_alert_handler_lpg_sleep_mode_alerts.178279642
Directory /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.376111847
Short name T503
Test name
Test status
Simulation time 4650939680 ps
CPU time 666.18 seconds
Started Mar 24 03:53:59 PM PDT 24
Finished Mar 24 04:05:06 PM PDT 24
Peak memory 636332 kb
Host smart-b95bb159-efd2-4e67-be94-134fc4af14d8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
376111847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.376111847
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_all_escalation_resets.1072297290
Short name T519
Test name
Test status
Simulation time 6447513804 ps
CPU time 727.44 seconds
Started Mar 24 03:53:04 PM PDT 24
Finished Mar 24 04:05:12 PM PDT 24
Peak memory 636232 kb
Host smart-51463245-c50b-4bde-8382-49f720e98db1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1072297290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1072297290
Directory /workspace/46.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289954839
Short name T348
Test name
Test status
Simulation time 3228098888 ps
CPU time 385.36 seconds
Started Mar 24 03:52:56 PM PDT 24
Finished Mar 24 03:59:22 PM PDT 24
Peak memory 635624 kb
Host smart-2ec8d85f-f212-4fd4-9272-0dd84630d480
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289954839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1289954839
Directory /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.2041075368
Short name T359
Test name
Test status
Simulation time 5663599706 ps
CPU time 745.22 seconds
Started Mar 24 03:54:24 PM PDT 24
Finished Mar 24 04:06:51 PM PDT 24
Peak memory 635264 kb
Host smart-5984436b-46af-4ee1-80b1-eca6118e9eb9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2041075368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2041075368
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2016138985
Short name T423
Test name
Test status
Simulation time 4340921704 ps
CPU time 419.41 seconds
Started Mar 24 03:53:00 PM PDT 24
Finished Mar 24 03:59:59 PM PDT 24
Peak memory 636452 kb
Host smart-82f135c4-3123-47ff-a890-dac2f189a815
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016138985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2016138985
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927655267
Short name T456
Test name
Test status
Simulation time 4072299416 ps
CPU time 332.98 seconds
Started Mar 24 03:54:18 PM PDT 24
Finished Mar 24 03:59:51 PM PDT 24
Peak memory 636284 kb
Host smart-1b807804-cb30-4d88-b143-5ccfda67864b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927655267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1927655267
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1882230444
Short name T179
Test name
Test status
Simulation time 4208338644 ps
CPU time 400.74 seconds
Started Mar 24 03:56:44 PM PDT 24
Finished Mar 24 04:03:26 PM PDT 24
Peak memory 635984 kb
Host smart-9feecdc0-b2f3-4924-a368-160997a4ad69
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882230444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1882230444
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.2353607544
Short name T491
Test name
Test status
Simulation time 5858393608 ps
CPU time 608.58 seconds
Started Mar 24 03:56:37 PM PDT 24
Finished Mar 24 04:06:47 PM PDT 24
Peak memory 636284 kb
Host smart-a57a9967-3027-4652-8a15-a89bb28e5ecf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2353607544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2353607544
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.2447486974
Short name T521
Test name
Test status
Simulation time 4032970846 ps
CPU time 478.13 seconds
Started Mar 24 03:53:37 PM PDT 24
Finished Mar 24 04:01:35 PM PDT 24
Peak memory 635896 kb
Host smart-f30001a8-a7ac-4a6d-8ebb-3e4dfe2b7c01
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2447486974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2447486974
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.3747199673
Short name T440
Test name
Test status
Simulation time 4583488472 ps
CPU time 611.68 seconds
Started Mar 24 03:53:30 PM PDT 24
Finished Mar 24 04:03:42 PM PDT 24
Peak memory 636216 kb
Host smart-7270454c-31da-42b7-ba53-4353cb48bd2d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3747199673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3747199673
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082056598
Short name T431
Test name
Test status
Simulation time 3403177144 ps
CPU time 394.55 seconds
Started Mar 24 03:54:04 PM PDT 24
Finished Mar 24 04:00:39 PM PDT 24
Peak memory 635952 kb
Host smart-deb2e432-6b9d-4e24-8101-c0a61fc2b164
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082056598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1082056598
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040808323
Short name T127
Test name
Test status
Simulation time 4213655024 ps
CPU time 385.76 seconds
Started Mar 24 03:54:30 PM PDT 24
Finished Mar 24 04:00:56 PM PDT 24
Peak memory 636412 kb
Host smart-d6d144a7-5543-45c3-aeb3-3d30c4fce8b7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040808323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3040808323
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748661804
Short name T461
Test name
Test status
Simulation time 3400549700 ps
CPU time 433.06 seconds
Started Mar 24 03:49:39 PM PDT 24
Finished Mar 24 03:56:52 PM PDT 24
Peak memory 636252 kb
Host smart-b83d437d-f554-4f55-bba0-906bdc9f0e16
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748661804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2748661804
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544416225
Short name T460
Test name
Test status
Simulation time 3786361848 ps
CPU time 349.73 seconds
Started Mar 24 03:55:51 PM PDT 24
Finished Mar 24 04:01:41 PM PDT 24
Peak memory 636240 kb
Host smart-a6a95e44-b0aa-4182-b685-f6e900c683a2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544416225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3544416225
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686118535
Short name T485
Test name
Test status
Simulation time 3802366384 ps
CPU time 360.42 seconds
Started Mar 24 03:55:14 PM PDT 24
Finished Mar 24 04:01:15 PM PDT 24
Peak memory 635856 kb
Host smart-2a804e33-5a6a-49b4-b72c-681368fe1eb5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686118535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3686118535
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.3957938224
Short name T518
Test name
Test status
Simulation time 5369284676 ps
CPU time 562.33 seconds
Started Mar 24 03:55:48 PM PDT 24
Finished Mar 24 04:05:12 PM PDT 24
Peak memory 635092 kb
Host smart-0d4e9c60-9572-45b4-9192-5b98259d645a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3957938224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3957938224
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.230246362
Short name T430
Test name
Test status
Simulation time 4045463166 ps
CPU time 408.41 seconds
Started Mar 24 03:55:38 PM PDT 24
Finished Mar 24 04:02:27 PM PDT 24
Peak memory 635952 kb
Host smart-998761c0-f96e-4c5a-b03a-449091a92186
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230246362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s
w_alert_handler_lpg_sleep_mode_alerts.230246362
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526809033
Short name T448
Test name
Test status
Simulation time 3969192130 ps
CPU time 455.87 seconds
Started Mar 24 03:55:29 PM PDT 24
Finished Mar 24 04:03:05 PM PDT 24
Peak memory 635948 kb
Host smart-dba2ef45-bd36-4d42-a59c-aa8b18f37593
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526809033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1526809033
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.554735537
Short name T284
Test name
Test status
Simulation time 4391435280 ps
CPU time 590.26 seconds
Started Mar 24 03:56:07 PM PDT 24
Finished Mar 24 04:05:57 PM PDT 24
Peak memory 636332 kb
Host smart-c8d60e9d-9009-46f7-8f16-f57c39e5058c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
554735537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.554735537
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.2664604194
Short name T447
Test name
Test status
Simulation time 6164274696 ps
CPU time 613.39 seconds
Started Mar 24 03:58:01 PM PDT 24
Finished Mar 24 04:08:14 PM PDT 24
Peak memory 635372 kb
Host smart-2f50479c-2ff8-43e4-af70-4ff80cc88bdb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2664604194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2664604194
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.704371994
Short name T231
Test name
Test status
Simulation time 5395181314 ps
CPU time 534.77 seconds
Started Mar 24 03:55:41 PM PDT 24
Finished Mar 24 04:04:36 PM PDT 24
Peak memory 636404 kb
Host smart-da36ab21-092e-4857-9915-42a791bc5d5a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
704371994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.704371994
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4215170407
Short name T43
Test name
Test status
Simulation time 3103893670 ps
CPU time 129.4 seconds
Started Mar 24 03:23:48 PM PDT 24
Finished Mar 24 03:25:58 PM PDT 24
Peak memory 610724 kb
Host smart-a808efcc-f80c-4131-a1f7-c18f8f097422
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4215170407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.4215170407
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1318670151
Short name T31
Test name
Test status
Simulation time 2503371980 ps
CPU time 307.27 seconds
Started Mar 24 03:28:04 PM PDT 24
Finished Mar 24 03:33:11 PM PDT 24
Peak memory 599620 kb
Host smart-e89f77e9-d334-4879-bd31-0b56a9b815ec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318670151 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1318670151
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3659068050
Short name T108
Test name
Test status
Simulation time 4394561950 ps
CPU time 437.06 seconds
Started Mar 24 03:34:27 PM PDT 24
Finished Mar 24 03:41:44 PM PDT 24
Peak memory 606112 kb
Host smart-a1b7a178-ad11-4da2-b5d6-f2969359cdfc
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659
068050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3659068050
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.657831497
Short name T272
Test name
Test status
Simulation time 2721527300 ps
CPU time 145.78 seconds
Started Mar 24 03:22:15 PM PDT 24
Finished Mar 24 03:24:41 PM PDT 24
Peak memory 605420 kb
Host smart-64d5df34-3d9b-4a92-accd-0b2b10d7bbbe
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657831497 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.657831497
Directory /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2563914534
Short name T277
Test name
Test status
Simulation time 5758607200 ps
CPU time 963.53 seconds
Started Mar 24 03:21:11 PM PDT 24
Finished Mar 24 03:37:15 PM PDT 24
Peak memory 600480 kb
Host smart-23e061fd-b671-4e45-a4f1-ea7eaa73c6a0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2563914534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.2563914534
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.1776088928
Short name T92
Test name
Test status
Simulation time 5904801188 ps
CPU time 1046.04 seconds
Started Mar 24 03:46:43 PM PDT 24
Finished Mar 24 04:04:09 PM PDT 24
Peak memory 600004 kb
Host smart-a5145d36-05c6-4925-93de-819c79ba1bde
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776088928 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.1776088928
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2540911467
Short name T388
Test name
Test status
Simulation time 5161433604 ps
CPU time 909.05 seconds
Started Mar 24 03:22:02 PM PDT 24
Finished Mar 24 03:37:11 PM PDT 24
Peak memory 599720 kb
Host smart-b854d430-1a0e-41d5-8e8e-d03977197aa1
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540911467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2540911467
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/4.chip_tap_straps_testunlock0.2630629425
Short name T117
Test name
Test status
Simulation time 6422831752 ps
CPU time 603.36 seconds
Started Mar 24 03:49:20 PM PDT 24
Finished Mar 24 03:59:24 PM PDT 24
Peak memory 609568 kb
Host smart-4fd5ca58-94e7-4d84-8bd3-7a658f51e64f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630629425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2630629425
Directory /workspace/4.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.16276132
Short name T34
Test name
Test status
Simulation time 2706863960 ps
CPU time 308.63 seconds
Started Mar 24 03:30:05 PM PDT 24
Finished Mar 24 03:35:14 PM PDT 24
Peak memory 608280 kb
Host smart-9fd6630f-4d25-4639-a246-cc1fee5d486a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276132 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.16276132
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1108288569
Short name T357
Test name
Test status
Simulation time 20990281616 ps
CPU time 1910.31 seconds
Started Mar 24 03:20:14 PM PDT 24
Finished Mar 24 03:52:05 PM PDT 24
Peak memory 604448 kb
Host smart-a5d76542-388f-469e-80ea-7cf4ffc64d1f
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082885
69 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1108288569
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2607937607
Short name T145
Test name
Test status
Simulation time 12975432547 ps
CPU time 1606.25 seconds
Started Mar 24 03:27:49 PM PDT 24
Finished Mar 24 03:54:36 PM PDT 24
Peak memory 607236 kb
Host smart-30ca937c-f7f0-4cde-9129-cc841ff4fcae
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607937607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2607937607
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2025772420
Short name T233
Test name
Test status
Simulation time 2871583240 ps
CPU time 252.85 seconds
Started Mar 24 03:25:30 PM PDT 24
Finished Mar 24 03:29:43 PM PDT 24
Peak memory 598916 kb
Host smart-9a255749-127e-418c-8aff-670250d93987
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025772420 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2025772420
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1780464573
Short name T79
Test name
Test status
Simulation time 9443113233 ps
CPU time 547.9 seconds
Started Mar 24 03:33:48 PM PDT 24
Finished Mar 24 03:42:56 PM PDT 24
Peak memory 600304 kb
Host smart-ce0e51be-bf59-420e-804f-135fae8830e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780464573 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1780464573
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1242012856
Short name T124
Test name
Test status
Simulation time 31655969460 ps
CPU time 6581.67 seconds
Started Mar 24 03:21:00 PM PDT 24
Finished Mar 24 05:10:43 PM PDT 24
Peak memory 599964 kb
Host smart-b53f433c-359c-46fa-87db-a93818e627aa
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=1242012856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1242012856
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.1282485320
Short name T106
Test name
Test status
Simulation time 2769741800 ps
CPU time 293.9 seconds
Started Mar 24 03:21:41 PM PDT 24
Finished Mar 24 03:26:36 PM PDT 24
Peak memory 600084 kb
Host smart-c70d3363-3fa9-4d52-b0a7-f3de2f0abef7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282485320 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_plic_sw_irq.1282485320
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.3023212853
Short name T176
Test name
Test status
Simulation time 4758009578 ps
CPU time 801.68 seconds
Started Mar 24 03:20:22 PM PDT 24
Finished Mar 24 03:33:44 PM PDT 24
Peak memory 600012 kb
Host smart-fe0d990d-b943-46d4-8ceb-366b46cb5fd6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023212853 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.3023212853
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.4100678219
Short name T311
Test name
Test status
Simulation time 4829372248 ps
CPU time 481.18 seconds
Started Mar 24 03:53:53 PM PDT 24
Finished Mar 24 04:01:55 PM PDT 24
Peak memory 601256 kb
Host smart-ead958a1-36aa-42b8-8f21-aff8ff2e7b32
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4100678219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4100678219
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.44611486
Short name T203
Test name
Test status
Simulation time 43840704559 ps
CPU time 4975.48 seconds
Started Mar 24 03:20:28 PM PDT 24
Finished Mar 24 04:43:25 PM PDT 24
Peak memory 607468 kb
Host smart-04cf9627-2e7d-4d88-8da9-957472c3c118
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=44611486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.44611486
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1365862659
Short name T5
Test name
Test status
Simulation time 6811004645 ps
CPU time 946.58 seconds
Started Mar 24 03:34:42 PM PDT 24
Finished Mar 24 03:50:29 PM PDT 24
Peak memory 600192 kb
Host smart-33b92fdf-96ff-4fe3-a5ec-5bdbf7f01945
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365862659 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1365862659
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.2624755285
Short name T172
Test name
Test status
Simulation time 6555113700 ps
CPU time 1332.54 seconds
Started Mar 24 03:38:51 PM PDT 24
Finished Mar 24 04:01:05 PM PDT 24
Peak memory 600004 kb
Host smart-bb624b32-e63d-4172-8c0e-8a6034a4af64
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624755285 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_0.2624755285
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4060158725
Short name T154
Test name
Test status
Simulation time 6102121012 ps
CPU time 783.06 seconds
Started Mar 24 03:21:14 PM PDT 24
Finished Mar 24 03:34:17 PM PDT 24
Peak memory 599980 kb
Host smart-4d850dab-cb03-4d10-be4d-c7c4e5e23af9
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601587
25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.4060158725
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1557549506
Short name T158
Test name
Test status
Simulation time 4280417336 ps
CPU time 401.54 seconds
Started Mar 24 03:50:04 PM PDT 24
Finished Mar 24 03:56:46 PM PDT 24
Peak memory 599916 kb
Host smart-7760bd61-4399-40a3-9eeb-467de1d24577
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575495
06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1557549506
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2167218507
Short name T157
Test name
Test status
Simulation time 4602087676 ps
CPU time 670.77 seconds
Started Mar 24 03:49:41 PM PDT 24
Finished Mar 24 04:00:52 PM PDT 24
Peak memory 600064 kb
Host smart-90bb79f5-5234-450c-a980-4fbd7c3ec65b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672185
07 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2167218507
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.438458084
Short name T947
Test name
Test status
Simulation time 4556687520 ps
CPU time 250.31 seconds
Started Mar 24 03:12:21 PM PDT 24
Finished Mar 24 03:16:32 PM PDT 24
Peak memory 636280 kb
Host smart-8ad855e4-c405-41e9-b37d-cf358c990dbe
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438458084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 0.chip_padctrl_attributes.438458084
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4282231507
Short name T194
Test name
Test status
Simulation time 47112213388 ps
CPU time 5383.38 seconds
Started Mar 24 03:42:30 PM PDT 24
Finished Mar 24 05:12:14 PM PDT 24
Peak memory 608472 kb
Host smart-adf30e88-b725-443b-82d0-ebef4bf268b0
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282231507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_dev.4282231507
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1804566576
Short name T186
Test name
Test status
Simulation time 3130538289 ps
CPU time 194.13 seconds
Started Mar 24 03:19:51 PM PDT 24
Finished Mar 24 03:23:05 PM PDT 24
Peak memory 608076 kb
Host smart-d62baee3-6b88-476e-b99c-7e8618f6bc55
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804566576 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1804566576
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.703452323
Short name T249
Test name
Test status
Simulation time 5232334279 ps
CPU time 787.99 seconds
Started Mar 24 03:21:07 PM PDT 24
Finished Mar 24 03:34:15 PM PDT 24
Peak memory 607176 kb
Host smart-00c6d1bd-d8b2-4cf8-9a7c-84d4ed6601be
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703452323 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.703452323
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.14533228
Short name T11
Test name
Test status
Simulation time 4772712478 ps
CPU time 709.69 seconds
Started Mar 24 03:20:33 PM PDT 24
Finished Mar 24 03:32:23 PM PDT 24
Peak memory 616660 kb
Host smart-098e0794-c619-4eeb-9681-4fc4ab5cc81b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533228 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.14533228
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.2128135008
Short name T168
Test name
Test status
Simulation time 4270081982 ps
CPU time 543.69 seconds
Started Mar 24 03:21:08 PM PDT 24
Finished Mar 24 03:30:13 PM PDT 24
Peak memory 599936 kb
Host smart-e60614af-ddef-4438-93d3-ec8bde6acd15
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128135008 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_10.2128135008
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2452841612
Short name T340
Test name
Test status
Simulation time 13518014584 ps
CPU time 1772.44 seconds
Started Mar 24 03:24:22 PM PDT 24
Finished Mar 24 03:53:55 PM PDT 24
Peak memory 600020 kb
Host smart-825305a0-025c-44b2-b293-bab0202d8fe4
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2452841612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2452841612
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2742377110
Short name T377
Test name
Test status
Simulation time 4361095981 ps
CPU time 558.22 seconds
Started Mar 24 03:22:57 PM PDT 24
Finished Mar 24 03:32:16 PM PDT 24
Peak memory 600016 kb
Host smart-ee393bed-bac1-4723-b5a5-898ce95981e8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2742377110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2742377110
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.46941510
Short name T747
Test name
Test status
Simulation time 8033157064 ps
CPU time 445.3 seconds
Started Mar 24 03:44:51 PM PDT 24
Finished Mar 24 03:52:16 PM PDT 24
Peak memory 600272 kb
Host smart-3fc22132-0cf9-476a-a652-3ba71a6cd712
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46941510 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.46941510
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3499181295
Short name T361
Test name
Test status
Simulation time 19306746208 ps
CPU time 814.45 seconds
Started Mar 24 03:31:34 PM PDT 24
Finished Mar 24 03:45:09 PM PDT 24
Peak memory 607184 kb
Host smart-72ea8762-dc52-4876-942c-c68d8f9c3b1e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3499181295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3499181295
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.342399728
Short name T630
Test name
Test status
Simulation time 3708844950 ps
CPU time 602.65 seconds
Started Mar 24 03:20:19 PM PDT 24
Finished Mar 24 03:30:23 PM PDT 24
Peak memory 603888 kb
Host smart-bab3e1c7-e5fc-4619-9461-e1165643ad60
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342399728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_dev.342399728
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2376652828
Short name T202
Test name
Test status
Simulation time 43204411198 ps
CPU time 5061.36 seconds
Started Mar 24 03:42:19 PM PDT 24
Finished Mar 24 05:06:42 PM PDT 24
Peak memory 607296 kb
Host smart-1c47e3ca-d41b-4fd8-a1a5-60a7b59aebec
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2376652828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2376652828
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.180406528
Short name T71
Test name
Test status
Simulation time 13608798204 ps
CPU time 1331.99 seconds
Started Mar 24 03:13:21 PM PDT 24
Finished Mar 24 03:35:33 PM PDT 24
Peak memory 599536 kb
Host smart-ebbddf3f-9d4a-4ab5-b0b0-71b39f0098f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180406528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m
em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.180406528
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3822224828
Short name T59
Test name
Test status
Simulation time 18933657432 ps
CPU time 1979.47 seconds
Started Mar 24 03:21:23 PM PDT 24
Finished Mar 24 03:54:23 PM PDT 24
Peak memory 601292 kb
Host smart-3feef1a8-db0b-4f44-bf45-cd7c89569fe4
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3822224828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3822224828
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2711239475
Short name T365
Test name
Test status
Simulation time 8082751944 ps
CPU time 1858.47 seconds
Started Mar 24 03:20:45 PM PDT 24
Finished Mar 24 03:51:44 PM PDT 24
Peak memory 600100 kb
Host smart-f646309f-eed6-468d-9387-5f7c4baa26b8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2711239475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2711239475
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.4001389589
Short name T177
Test name
Test status
Simulation time 4961195192 ps
CPU time 885.15 seconds
Started Mar 24 03:44:40 PM PDT 24
Finished Mar 24 03:59:25 PM PDT 24
Peak memory 600072 kb
Host smart-0026c4a2-5373-4d93-920b-c208c2451668
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001389589 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_20.4001389589
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1921101106
Short name T760
Test name
Test status
Simulation time 4974916225 ps
CPU time 771.8 seconds
Started Mar 24 03:25:21 PM PDT 24
Finished Mar 24 03:38:14 PM PDT 24
Peak memory 607184 kb
Host smart-3eb6fa58-8ac6-47ff-8b22-c2cdbefb1365
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1921101106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1921101106
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.225517238
Short name T413
Test name
Test status
Simulation time 5345609588 ps
CPU time 536.74 seconds
Started Mar 24 03:22:57 PM PDT 24
Finished Mar 24 03:31:54 PM PDT 24
Peak memory 607180 kb
Host smart-02b86092-14a0-4be5-83f6-4ed4a03634e8
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225517238 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.225517238
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.1757833386
Short name T25
Test name
Test status
Simulation time 3812727899 ps
CPU time 521.45 seconds
Started Mar 24 03:20:03 PM PDT 24
Finished Mar 24 03:28:44 PM PDT 24
Peak memory 599564 kb
Host smart-2daa0cdc-ceaf-4563-a637-dc6aa6ffd190
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757833386 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_gpio.1757833386
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.122604191
Short name T16
Test name
Test status
Simulation time 3392754818 ps
CPU time 416.13 seconds
Started Mar 24 03:21:25 PM PDT 24
Finished Mar 24 03:28:22 PM PDT 24
Peak memory 599896 kb
Host smart-fff6fc9e-ffdb-4985-9f87-09d692122adf
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122604
191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.122604191
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.2044294380
Short name T316
Test name
Test status
Simulation time 3922174824 ps
CPU time 411.54 seconds
Started Mar 24 03:21:51 PM PDT 24
Finished Mar 24 03:28:42 PM PDT 24
Peak memory 599864 kb
Host smart-a0a2697f-4a6f-4530-a98e-2e2855f4f1a1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044294380 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2044294380
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.547159296
Short name T167
Test name
Test status
Simulation time 4136475744 ps
CPU time 713.76 seconds
Started Mar 24 03:34:54 PM PDT 24
Finished Mar 24 03:46:48 PM PDT 24
Peak memory 599948 kb
Host smart-290c1900-6b8a-4a07-a572-4194b74ebb70
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547159296 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_10.547159296
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.808882681
Short name T354
Test name
Test status
Simulation time 3128018620 ps
CPU time 236.31 seconds
Started Mar 24 03:38:31 PM PDT 24
Finished Mar 24 03:42:29 PM PDT 24
Peak memory 600052 kb
Host smart-6f6ee75e-43e2-4381-b166-82010e6d9a76
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808882681 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.808882681
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.180924510
Short name T133
Test name
Test status
Simulation time 5411662499 ps
CPU time 854.64 seconds
Started Mar 24 03:20:38 PM PDT 24
Finished Mar 24 03:34:53 PM PDT 24
Peak memory 607164 kb
Host smart-20861d4c-9a67-4221-bb67-20c5e0e22860
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180924510 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.180924510
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1529964244
Short name T187
Test name
Test status
Simulation time 2386735170 ps
CPU time 233.73 seconds
Started Mar 24 03:28:34 PM PDT 24
Finished Mar 24 03:32:28 PM PDT 24
Peak memory 607052 kb
Host smart-e290c7a7-c9fb-4cf0-916e-4a1e0db417c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529964244 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1529964244
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2421851443
Short name T212
Test name
Test status
Simulation time 4666614232 ps
CPU time 952.4 seconds
Started Mar 24 03:19:58 PM PDT 24
Finished Mar 24 03:35:51 PM PDT 24
Peak memory 599836 kb
Host smart-0a5fd0ef-5754-4a5b-ae84-b95d2d21044c
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421851443 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2421851443
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.2462185775
Short name T393
Test name
Test status
Simulation time 3337226178 ps
CPU time 598.36 seconds
Started Mar 24 03:19:37 PM PDT 24
Finished Mar 24 03:29:36 PM PDT 24
Peak memory 600096 kb
Host smart-74f3f468-7a66-4818-bd1e-c3ab893543d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462185775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
boot_mode.2462185775
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.93765799
Short name T193
Test name
Test status
Simulation time 20057832952 ps
CPU time 1861.04 seconds
Started Mar 24 03:19:03 PM PDT 24
Finished Mar 24 03:50:05 PM PDT 24
Peak memory 604432 kb
Host smart-edf25ff2-1010-486e-bce3-434aa960f723
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93765799 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.93765799
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4156492256
Short name T213
Test name
Test status
Simulation time 5283708200 ps
CPU time 634.49 seconds
Started Mar 24 03:22:02 PM PDT 24
Finished Mar 24 03:32:37 PM PDT 24
Peak memory 599368 kb
Host smart-6169ec29-8115-4d95-b730-6ebca4974dbf
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156492256 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.4156492256
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4178667874
Short name T218
Test name
Test status
Simulation time 4424148180 ps
CPU time 911.88 seconds
Started Mar 24 03:20:52 PM PDT 24
Finished Mar 24 03:36:05 PM PDT 24
Peak memory 599976 kb
Host smart-65f64fbe-227a-42a5-a55d-b0eef177631c
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178667874 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.4178667874
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.672032489
Short name T119
Test name
Test status
Simulation time 2185954423 ps
CPU time 203.41 seconds
Started Mar 24 03:39:13 PM PDT 24
Finished Mar 24 03:42:36 PM PDT 24
Peak memory 607024 kb
Host smart-a850dc63-72ff-4730-83a2-a00499f5759b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672032489 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.672032489
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4244426795
Short name T199
Test name
Test status
Simulation time 7861121250 ps
CPU time 771.26 seconds
Started Mar 24 03:21:22 PM PDT 24
Finished Mar 24 03:34:13 PM PDT 24
Peak memory 601036 kb
Host smart-2fd2700a-35b3-4d7f-9c74-108d74669062
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244426795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.4244426795
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.254800649
Short name T19
Test name
Test status
Simulation time 20117371212 ps
CPU time 3358.34 seconds
Started Mar 24 03:21:02 PM PDT 24
Finished Mar 24 04:17:01 PM PDT 24
Peak memory 599528 kb
Host smart-2ca2690e-f392-43c6-b743-fc35ddbfbf81
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254800649 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.254800649
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3080004790
Short name T83
Test name
Test status
Simulation time 5575558360 ps
CPU time 753.91 seconds
Started Mar 24 03:48:07 PM PDT 24
Finished Mar 24 04:00:41 PM PDT 24
Peak memory 600464 kb
Host smart-7c1d3836-d88c-47c8-b9d9-d017887afdef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3080004790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3080004790
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.1492762117
Short name T415
Test name
Test status
Simulation time 13469149582 ps
CPU time 1409.61 seconds
Started Mar 24 03:36:54 PM PDT 24
Finished Mar 24 04:00:24 PM PDT 24
Peak memory 609580 kb
Host smart-85bab3b9-9966-4886-9b69-be427ac07ebf
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1492762117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1492762117
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.853060643
Short name T378
Test name
Test status
Simulation time 4562341008 ps
CPU time 552.3 seconds
Started Mar 24 03:29:19 PM PDT 24
Finished Mar 24 03:38:32 PM PDT 24
Peak memory 599880 kb
Host smart-6348401a-f15b-40f2-88b2-3a73041b86bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853060643 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.853060643
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.3617400727
Short name T26
Test name
Test status
Simulation time 4123563312 ps
CPU time 658.39 seconds
Started Mar 24 03:30:03 PM PDT 24
Finished Mar 24 03:41:02 PM PDT 24
Peak memory 599860 kb
Host smart-e424e010-927e-4788-8ede-33a03433a2f5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617400727 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_gpio.3617400727
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219810388
Short name T288
Test name
Test status
Simulation time 4391245455 ps
CPU time 505.63 seconds
Started Mar 24 03:34:35 PM PDT 24
Finished Mar 24 03:43:01 PM PDT 24
Peak memory 600992 kb
Host smart-7f8f24bd-235f-4a27-9293-2a62f35ce296
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219810388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219810388
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2296026290
Short name T389
Test name
Test status
Simulation time 24061377450 ps
CPU time 3494.87 seconds
Started Mar 24 03:22:59 PM PDT 24
Finished Mar 24 04:21:15 PM PDT 24
Peak memory 600144 kb
Host smart-ba15928c-50cb-4d20-9f93-649647f87063
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296026290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2296026290
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.49221270
Short name T704
Test name
Test status
Simulation time 5040336768 ps
CPU time 670.31 seconds
Started Mar 24 03:26:29 PM PDT 24
Finished Mar 24 03:37:39 PM PDT 24
Peak memory 600048 kb
Host smart-e872b233-9cbb-4733-ae04-a5b0dd975ec3
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49221270 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.49221270
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.467235127
Short name T94
Test name
Test status
Simulation time 3188010238 ps
CPU time 347.24 seconds
Started Mar 24 03:23:53 PM PDT 24
Finished Mar 24 03:29:40 PM PDT 24
Peak memory 599940 kb
Host smart-b82f8ed2-5ba4-4c78-ab0f-5930b33ded4c
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467235127 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.467235127
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2150504577
Short name T540
Test name
Test status
Simulation time 10193311505 ps
CPU time 1067.86 seconds
Started Mar 24 03:21:03 PM PDT 24
Finished Mar 24 03:38:52 PM PDT 24
Peak memory 612364 kb
Host smart-aa99a0d7-7c5a-4acd-8181-d7abdac03a10
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150504577 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2150504577
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.51897782
Short name T317
Test name
Test status
Simulation time 10413672660 ps
CPU time 657.05 seconds
Started Mar 24 03:24:53 PM PDT 24
Finished Mar 24 03:35:51 PM PDT 24
Peak memory 600204 kb
Host smart-dd450905-ed19-451b-a29b-51d2e9e64947
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51897782 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.51897782
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2504526402
Short name T561
Test name
Test status
Simulation time 7029426660 ps
CPU time 503.83 seconds
Started Mar 24 03:21:59 PM PDT 24
Finished Mar 24 03:30:23 PM PDT 24
Peak memory 606604 kb
Host smart-42f53fb6-785e-4f73-bdac-e2611e827943
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2504526402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2504526402
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2874006127
Short name T312
Test name
Test status
Simulation time 4022466340 ps
CPU time 802.19 seconds
Started Mar 24 03:26:44 PM PDT 24
Finished Mar 24 03:40:06 PM PDT 24
Peak memory 599892 kb
Host smart-c9dfc6ad-2fd6-4f00-acfd-11438bf3ba5f
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28740
06127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2874006127
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4028278584
Short name T148
Test name
Test status
Simulation time 18557736595 ps
CPU time 3697.72 seconds
Started Mar 24 03:24:55 PM PDT 24
Finished Mar 24 04:26:34 PM PDT 24
Peak memory 600104 kb
Host smart-bd894aeb-d29a-492a-81ec-4baf9eecfb34
User root
Command /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028278584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw
_csrng_edn_concurrency_reduced_freq.4028278584
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3053726743
Short name T883
Test name
Test status
Simulation time 4803195580 ps
CPU time 855.22 seconds
Started Mar 24 03:22:51 PM PDT 24
Finished Mar 24 03:37:07 PM PDT 24
Peak memory 600088 kb
Host smart-886f575c-ebcc-487b-b276-cb079590edc0
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053726743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3053726743
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3881714208
Short name T327
Test name
Test status
Simulation time 5461998968 ps
CPU time 679.41 seconds
Started Mar 24 03:21:19 PM PDT 24
Finished Mar 24 03:32:39 PM PDT 24
Peak memory 600588 kb
Host smart-4fb527a4-8a3e-4f52-ba43-9bdbfbbcd0da
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388171
4208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3881714208
Directory /workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1999041109
Short name T332
Test name
Test status
Simulation time 15342475304 ps
CPU time 4148.59 seconds
Started Mar 24 03:21:50 PM PDT 24
Finished Mar 24 04:30:59 PM PDT 24
Peak memory 600268 kb
Host smart-e5d8f367-7d98-46bb-9f54-075590f103a7
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
41109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1999041109
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.963686498
Short name T719
Test name
Test status
Simulation time 3437731198 ps
CPU time 430.87 seconds
Started Mar 24 03:24:26 PM PDT 24
Finished Mar 24 03:31:37 PM PDT 24
Peak memory 599980 kb
Host smart-d990872d-16fc-4d7f-aa24-46ea05ec3def
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963686498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.963686498
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4223769764
Short name T262
Test name
Test status
Simulation time 12008442580 ps
CPU time 2913.79 seconds
Started Mar 24 03:31:04 PM PDT 24
Finished Mar 24 04:19:39 PM PDT 24
Peak memory 601060 kb
Host smart-295d4c84-cf9c-467b-ab77-f523a2a17ef7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4223769764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4223769764
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.3658288631
Short name T902
Test name
Test status
Simulation time 2825076280 ps
CPU time 213.13 seconds
Started Mar 24 03:19:06 PM PDT 24
Finished Mar 24 03:22:40 PM PDT 24
Peak memory 600000 kb
Host smart-fcee8314-5714-4bdf-a86b-36a616684025
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3658288631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3658288631
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703619182
Short name T375
Test name
Test status
Simulation time 18819011570 ps
CPU time 456.3 seconds
Started Mar 24 03:24:25 PM PDT 24
Finished Mar 24 03:32:02 PM PDT 24
Peak memory 607200 kb
Host smart-1e882d2d-7f41-4064-9059-2506c1aed8c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=703619182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703619182
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.3327973422
Short name T646
Test name
Test status
Simulation time 2605990450 ps
CPU time 277.36 seconds
Started Mar 24 03:19:04 PM PDT 24
Finished Mar 24 03:23:42 PM PDT 24
Peak memory 599904 kb
Host smart-12c44276-4022-400b-a416-b1d16fcfd05f
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327973422 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3327973422
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3425990359
Short name T528
Test name
Test status
Simulation time 3100549546 ps
CPU time 267.88 seconds
Started Mar 24 03:20:46 PM PDT 24
Finished Mar 24 03:25:15 PM PDT 24
Peak memory 599900 kb
Host smart-716fe63a-a593-4b04-8657-6ad7c02ca8ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425
990359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.3425990359
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1218137693
Short name T101
Test name
Test status
Simulation time 2544966084 ps
CPU time 232.6 seconds
Started Mar 24 03:22:13 PM PDT 24
Finished Mar 24 03:26:06 PM PDT 24
Peak memory 599896 kb
Host smart-21fbd1e7-9f5f-4b70-bc5d-80d256154a40
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1218137693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1218137693
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.89287947
Short name T102
Test name
Test status
Simulation time 3043450888 ps
CPU time 207.38 seconds
Started Mar 24 03:21:32 PM PDT 24
Finished Mar 24 03:25:00 PM PDT 24
Peak memory 599908 kb
Host smart-724383b1-062a-45d8-9fe6-8af3e3ce752c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89287947 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.89287947
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.4153123520
Short name T621
Test name
Test status
Simulation time 2537946150 ps
CPU time 222.11 seconds
Started Mar 24 03:21:22 PM PDT 24
Finished Mar 24 03:25:05 PM PDT 24
Peak memory 599876 kb
Host smart-aa797da1-eab3-4bfe-ae70-bedcfe049882
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153123520 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.4153123520
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.4076749603
Short name T710
Test name
Test status
Simulation time 2351481927 ps
CPU time 280.74 seconds
Started Mar 24 03:22:35 PM PDT 24
Finished Mar 24 03:27:17 PM PDT 24
Peak memory 599596 kb
Host smart-e8bbd473-abdc-40fb-ba13-e56e3e83e7de
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076749603 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.4076749603
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.2750092638
Short name T735
Test name
Test status
Simulation time 2422150740 ps
CPU time 218.21 seconds
Started Mar 24 03:26:28 PM PDT 24
Finished Mar 24 03:30:06 PM PDT 24
Peak memory 599932 kb
Host smart-0443933b-b2d5-4613-b591-6e22fb0586f5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750092638 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.2750092638
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1277549300
Short name T54
Test name
Test status
Simulation time 3268338087 ps
CPU time 262.01 seconds
Started Mar 24 03:20:27 PM PDT 24
Finished Mar 24 03:24:49 PM PDT 24
Peak memory 599364 kb
Host smart-3615c483-98e5-437d-bd93-3f2f4dccb830
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1277549300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1277549300
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3586018871
Short name T256
Test name
Test status
Simulation time 6183647962 ps
CPU time 604.16 seconds
Started Mar 24 03:21:54 PM PDT 24
Finished Mar 24 03:31:59 PM PDT 24
Peak memory 607096 kb
Host smart-3009e743-f2f9-4e46-ba9a-62d384bf8b1c
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3586018871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3586018871
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2303979968
Short name T701
Test name
Test status
Simulation time 7488515788 ps
CPU time 1789.82 seconds
Started Mar 24 03:21:45 PM PDT 24
Finished Mar 24 03:51:35 PM PDT 24
Peak memory 600868 kb
Host smart-aa853584-32dc-4cc4-be53-d20779adb877
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2303979968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2303979968
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.88878994
Short name T634
Test name
Test status
Simulation time 6414547070 ps
CPU time 1474.58 seconds
Started Mar 24 03:23:50 PM PDT 24
Finished Mar 24 03:48:26 PM PDT 24
Peak memory 599436 kb
Host smart-5eb96543-4abc-4fec-be32-7740aee68edf
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=88878994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.88878994
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2618380509
Short name T442
Test name
Test status
Simulation time 10249367790 ps
CPU time 1194.99 seconds
Started Mar 24 03:20:14 PM PDT 24
Finished Mar 24 03:40:09 PM PDT 24
Peak memory 601148 kb
Host smart-597a3471-57ad-452b-b697-a3404c0fbb3d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618380509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.2618380509
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1028710296
Short name T339
Test name
Test status
Simulation time 3262125750 ps
CPU time 276.83 seconds
Started Mar 24 03:21:27 PM PDT 24
Finished Mar 24 03:26:04 PM PDT 24
Peak memory 599164 kb
Host smart-9103b250-0a55-4d87-8558-48bd7cf43d54
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1028710296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1028710296
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3768232433
Short name T859
Test name
Test status
Simulation time 254708065108 ps
CPU time 11728.3 seconds
Started Mar 24 03:21:05 PM PDT 24
Finished Mar 24 06:36:35 PM PDT 24
Peak memory 599988 kb
Host smart-dfe61231-ce7a-4be2-9a9b-4c9fe3929b2b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768232433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3768232433
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.323962221
Short name T77
Test name
Test status
Simulation time 3515164392 ps
CPU time 354.55 seconds
Started Mar 24 03:22:40 PM PDT 24
Finished Mar 24 03:28:35 PM PDT 24
Peak memory 599956 kb
Host smart-550065dc-3132-4324-b024-5f63b1fe66e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323962221 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_alert_test.323962221
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4073247927
Short name T825
Test name
Test status
Simulation time 6311145832 ps
CPU time 577.94 seconds
Started Mar 24 03:24:37 PM PDT 24
Finished Mar 24 03:34:16 PM PDT 24
Peak memory 600008 kb
Host smart-cb8bb201-4635-463e-9542-45896cd64d76
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4073247927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4073247927
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3356238748
Short name T899
Test name
Test status
Simulation time 3167489080 ps
CPU time 308.17 seconds
Started Mar 24 03:27:09 PM PDT 24
Finished Mar 24 03:32:18 PM PDT 24
Peak memory 599872 kb
Host smart-59134c08-a8fb-45f7-b508-d75e9b5bae0e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356238748 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_aon_timer_smoketest.3356238748
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2693393403
Short name T720
Test name
Test status
Simulation time 10140747960 ps
CPU time 927.54 seconds
Started Mar 24 03:22:19 PM PDT 24
Finished Mar 24 03:37:47 PM PDT 24
Peak memory 599932 kb
Host smart-bd717fc5-9cd5-45a4-93af-7c050007cc0e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2693393403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2693393403
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4238959994
Short name T877
Test name
Test status
Simulation time 4427742500 ps
CPU time 751.05 seconds
Started Mar 24 03:23:58 PM PDT 24
Finished Mar 24 03:36:29 PM PDT 24
Peak memory 600084 kb
Host smart-fb2de8b7-1f45-489f-88f5-cfac8a0e207e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4238959994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.4238959994
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3786182556
Short name T773
Test name
Test status
Simulation time 6365036614 ps
CPU time 991.96 seconds
Started Mar 24 03:21:40 PM PDT 24
Finished Mar 24 03:38:12 PM PDT 24
Peak memory 606068 kb
Host smart-ea6b532d-5caa-4265-ba21-73ee685735ea
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786182556 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3786182556
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4221864244
Short name T893
Test name
Test status
Simulation time 7045185680 ps
CPU time 640.27 seconds
Started Mar 24 03:21:11 PM PDT 24
Finished Mar 24 03:31:52 PM PDT 24
Peak memory 612596 kb
Host smart-0db9386a-b740-48c5-b9fc-dca5b1484767
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=4221864244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.4221864244
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.345127977
Short name T600
Test name
Test status
Simulation time 4283623596 ps
CPU time 688.2 seconds
Started Mar 24 03:25:32 PM PDT 24
Finished Mar 24 03:37:01 PM PDT 24
Peak memory 603152 kb
Host smart-80e82d08-6040-4ac8-b1d0-dc0ca367f99f
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345127977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_rma.345127977
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3216307822
Short name T767
Test name
Test status
Simulation time 3520119700 ps
CPU time 582.4 seconds
Started Mar 24 03:26:03 PM PDT 24
Finished Mar 24 03:35:46 PM PDT 24
Peak memory 602740 kb
Host smart-d3792b66-7ebb-4e20-af45-7f362709053a
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216307822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3216307822
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.58896555
Short name T611
Test name
Test status
Simulation time 4987774736 ps
CPU time 534.7 seconds
Started Mar 24 03:20:27 PM PDT 24
Finished Mar 24 03:29:22 PM PDT 24
Peak memory 603264 kb
Host smart-0ad67e3a-3fa2-4eb1-acae-1970d6509b7d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58896555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clk
mgr_external_clk_src_for_sw_slow_dev.58896555
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1966316285
Short name T44
Test name
Test status
Simulation time 4900928928 ps
CPU time 641.18 seconds
Started Mar 24 03:20:57 PM PDT 24
Finished Mar 24 03:31:38 PM PDT 24
Peak memory 603128 kb
Host smart-2d5dcd16-86aa-4259-a0b0-341a5187e7eb
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966316285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1966316285
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2144641762
Short name T163
Test name
Test status
Simulation time 3736916060 ps
CPU time 526.48 seconds
Started Mar 24 03:19:52 PM PDT 24
Finished Mar 24 03:28:39 PM PDT 24
Peak memory 603196 kb
Host smart-5df3f5dc-0100-44ed-bc44-a200c218918c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144641762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2144641762
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2217408827
Short name T915
Test name
Test status
Simulation time 2680592250 ps
CPU time 247.95 seconds
Started Mar 24 03:23:47 PM PDT 24
Finished Mar 24 03:27:55 PM PDT 24
Peak memory 599836 kb
Host smart-ee383c08-9ecb-471e-a47b-30b791a76042
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217408827 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_clkmgr_jitter.2217408827
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3184617079
Short name T629
Test name
Test status
Simulation time 3313193288 ps
CPU time 383.3 seconds
Started Mar 24 03:21:22 PM PDT 24
Finished Mar 24 03:27:46 PM PDT 24
Peak memory 599904 kb
Host smart-8ed2b3f9-5783-42cd-96ae-3c7cd9f53593
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184617079 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3184617079
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3567077552
Short name T578
Test name
Test status
Simulation time 1992109723 ps
CPU time 151.4 seconds
Started Mar 24 03:26:13 PM PDT 24
Finished Mar 24 03:28:45 PM PDT 24
Peak memory 599852 kb
Host smart-b9a0d89b-0e6e-484e-a683-59fbf3a1de2d
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567077552 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3567077552
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2859593782
Short name T896
Test name
Test status
Simulation time 5324311524 ps
CPU time 464.11 seconds
Started Mar 24 03:21:09 PM PDT 24
Finished Mar 24 03:28:54 PM PDT 24
Peak memory 599356 kb
Host smart-b8bc5cc2-ffdf-4df6-94a6-f4bde5d617ba
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859593782 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2859593782
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.41562980
Short name T571
Test name
Test status
Simulation time 5669246784 ps
CPU time 528.94 seconds
Started Mar 24 03:22:20 PM PDT 24
Finished Mar 24 03:31:09 PM PDT 24
Peak memory 599844 kb
Host smart-f68150d9-ff7d-4c03-98c7-1fdebac19f6b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41562980 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.41562980
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.376249975
Short name T779
Test name
Test status
Simulation time 5689429184 ps
CPU time 531.07 seconds
Started Mar 24 03:21:18 PM PDT 24
Finished Mar 24 03:30:09 PM PDT 24
Peak memory 599976 kb
Host smart-850fcecc-d5bb-4ed0-a01a-e3ba4855a62e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376249975 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.376249975
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.449848786
Short name T96
Test name
Test status
Simulation time 5190347800 ps
CPU time 528.95 seconds
Started Mar 24 03:20:32 PM PDT 24
Finished Mar 24 03:29:21 PM PDT 24
Peak memory 600008 kb
Host smart-3fd36731-075f-4330-9ceb-9bfb2b717452
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449848786 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.449848786
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3700694025
Short name T897
Test name
Test status
Simulation time 11874958914 ps
CPU time 1620.96 seconds
Started Mar 24 03:22:02 PM PDT 24
Finished Mar 24 03:49:03 PM PDT 24
Peak memory 599916 kb
Host smart-295a691c-d4f9-4ca7-8709-d6fc268189f2
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700694025
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3700694025
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1166830844
Short name T384
Test name
Test status
Simulation time 3535833312 ps
CPU time 465.28 seconds
Started Mar 24 03:22:00 PM PDT 24
Finished Mar 24 03:29:45 PM PDT 24
Peak memory 599888 kb
Host smart-74360dd0-58b3-402e-a3e2-345cf09a9009
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166830844 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1166830844
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2362694885
Short name T525
Test name
Test status
Simulation time 4822431336 ps
CPU time 595.96 seconds
Started Mar 24 03:22:47 PM PDT 24
Finished Mar 24 03:32:43 PM PDT 24
Peak memory 599304 kb
Host smart-ed6a9cb1-32bd-4d6e-8dfa-acd8aaf93c88
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362694885 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2362694885
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.84082972
Short name T408
Test name
Test status
Simulation time 2810217156 ps
CPU time 221.76 seconds
Started Mar 24 03:27:30 PM PDT 24
Finished Mar 24 03:31:12 PM PDT 24
Peak memory 599848 kb
Host smart-5ecc1f54-529c-486d-ba8a-51d2b6a25590
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84082972 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_clkmgr_smoketest.84082972
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.1738742199
Short name T662
Test name
Test status
Simulation time 51178589256 ps
CPU time 10238.8 seconds
Started Mar 24 03:19:52 PM PDT 24
Finished Mar 24 06:10:32 PM PDT 24
Peak memory 598984 kb
Host smart-08cca06c-1aa3-443b-9800-3a9648df4db9
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1738742199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1738742199
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3846697158
Short name T718
Test name
Test status
Simulation time 20747777496 ps
CPU time 4722.31 seconds
Started Mar 24 03:21:35 PM PDT 24
Finished Mar 24 04:40:18 PM PDT 24
Peak memory 600028 kb
Host smart-41340f89-9ca5-4071-a904-19ef7617bd55
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846697158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3846697158
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1151947114
Short name T204
Test name
Test status
Simulation time 5524499774 ps
CPU time 533.16 seconds
Started Mar 24 03:20:27 PM PDT 24
Finished Mar 24 03:29:21 PM PDT 24
Peak memory 600164 kb
Host smart-5d54dab1-9481-4ee3-9ff4-ed4fbed5c1ea
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
47114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1151947114
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.3433646039
Short name T723
Test name
Test status
Simulation time 2652880410 ps
CPU time 238.84 seconds
Started Mar 24 03:24:09 PM PDT 24
Finished Mar 24 03:28:08 PM PDT 24
Peak memory 599808 kb
Host smart-520c95f1-c29e-419a-b631-2f2cba215e1d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433646039 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3433646039
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.89085508
Short name T104
Test name
Test status
Simulation time 5209792900 ps
CPU time 523.18 seconds
Started Mar 24 03:22:24 PM PDT 24
Finished Mar 24 03:31:07 PM PDT 24
Peak memory 600276 kb
Host smart-067b34e7-1d65-455f-a446-a921d4212eb4
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89085508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc
_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng
_lc_hw_debug_en_test.89085508
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.3294886183
Short name T798
Test name
Test status
Simulation time 2298952624 ps
CPU time 215.1 seconds
Started Mar 24 03:28:16 PM PDT 24
Finished Mar 24 03:31:53 PM PDT 24
Peak memory 599948 kb
Host smart-1cb0387e-dd55-4b49-bfc4-b384fc153357
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294886183 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.3294886183
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.309054274
Short name T744
Test name
Test status
Simulation time 3252460572 ps
CPU time 702.18 seconds
Started Mar 24 03:21:45 PM PDT 24
Finished Mar 24 03:33:27 PM PDT 24
Peak memory 605428 kb
Host smart-10195c13-a63e-4394-ad3e-c2dec724a330
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309054274 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_edn_kat.309054274
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.1444299578
Short name T708
Test name
Test status
Simulation time 11219517200 ps
CPU time 2482.96 seconds
Started Mar 24 03:19:55 PM PDT 24
Finished Mar 24 04:01:19 PM PDT 24
Peak memory 599228 kb
Host smart-c6e01029-1fe9-49a5-a665-c749e27f3108
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444299578 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1444299578
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.780460500
Short name T591
Test name
Test status
Simulation time 2615009374 ps
CPU time 308.98 seconds
Started Mar 24 03:20:55 PM PDT 24
Finished Mar 24 03:26:04 PM PDT 24
Peak memory 599088 kb
Host smart-3faef17b-f599-4199-aea3-8f91c1aaaac5
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78
0460500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.780460500
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3842461072
Short name T336
Test name
Test status
Simulation time 3393246958 ps
CPU time 248.34 seconds
Started Mar 24 03:23:59 PM PDT 24
Finished Mar 24 03:28:07 PM PDT 24
Peak memory 599920 kb
Host smart-9b3d0510-2989-446d-b8d3-5b88567f430c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842461072
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3842461072
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2103657553
Short name T937
Test name
Test status
Simulation time 2846664056 ps
CPU time 376.07 seconds
Started Mar 24 03:26:37 PM PDT 24
Finished Mar 24 03:32:54 PM PDT 24
Peak memory 599888 kb
Host smart-d20f5085-fb22-43c4-8ada-7d627ecb8340
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2103657553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2103657553
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.2800004708
Short name T907
Test name
Test status
Simulation time 2949245410 ps
CPU time 241.07 seconds
Started Mar 24 03:21:04 PM PDT 24
Finished Mar 24 03:25:05 PM PDT 24
Peak memory 599852 kb
Host smart-dbf590a8-fd89-4486-92ac-53c83f750f29
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800004708 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_example_concurrency.2800004708
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.242382141
Short name T837
Test name
Test status
Simulation time 3139108786 ps
CPU time 217.48 seconds
Started Mar 24 03:21:01 PM PDT 24
Finished Mar 24 03:24:39 PM PDT 24
Peak memory 598912 kb
Host smart-4b98fcbc-d878-4431-b331-c0ba580542a9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242382141 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.242382141
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.1591774544
Short name T661
Test name
Test status
Simulation time 2787251812 ps
CPU time 224.18 seconds
Started Mar 24 03:19:45 PM PDT 24
Finished Mar 24 03:23:29 PM PDT 24
Peak memory 599912 kb
Host smart-72a3cb26-260b-4e33-9a87-3604a08f983f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591774544 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_example_manufacturer.1591774544
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.3318804966
Short name T820
Test name
Test status
Simulation time 2164351656 ps
CPU time 129.91 seconds
Started Mar 24 03:19:35 PM PDT 24
Finished Mar 24 03:21:45 PM PDT 24
Peak memory 599452 kb
Host smart-7680f436-9ebd-4a20-bae1-68df25a3fbf6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318804966 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_rom.3318804966
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2211098272
Short name T775
Test name
Test status
Simulation time 57956544113 ps
CPU time 10522.9 seconds
Started Mar 24 03:21:20 PM PDT 24
Finished Mar 24 06:16:45 PM PDT 24
Peak memory 608232 kb
Host smart-e5f58dbe-46bb-4258-8e02-9a5e15b7b49a
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2211098272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2211098272
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.2501315738
Short name T689
Test name
Test status
Simulation time 4558225030 ps
CPU time 666.56 seconds
Started Mar 24 03:23:10 PM PDT 24
Finished Mar 24 03:34:17 PM PDT 24
Peak memory 601204 kb
Host smart-2038249a-e0da-47ed-8de4-50a996c88f27
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=2501315738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2501315738
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1226687959
Short name T709
Test name
Test status
Simulation time 5678120288 ps
CPU time 1215.38 seconds
Started Mar 24 03:22:04 PM PDT 24
Finished Mar 24 03:42:20 PM PDT 24
Peak memory 600008 kb
Host smart-e83454b0-2030-44b1-9153-296e428c66cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226687959 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_flash_ctrl_access.1226687959
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3174605925
Short name T790
Test name
Test status
Simulation time 5597732858 ps
CPU time 1007.71 seconds
Started Mar 24 03:21:02 PM PDT 24
Finished Mar 24 03:37:51 PM PDT 24
Peak memory 600020 kb
Host smart-b6c85095-cfff-48b3-83b1-a3798fa3930a
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174605925 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3174605925
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3513269951
Short name T142
Test name
Test status
Simulation time 7635483528 ps
CPU time 1255.61 seconds
Started Mar 24 03:24:35 PM PDT 24
Finished Mar 24 03:45:30 PM PDT 24
Peak memory 600012 kb
Host smart-13bfcefe-29ed-49a5-8669-828afa9e6369
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513269951 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3513269951
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3916147770
Short name T876
Test name
Test status
Simulation time 6003428488 ps
CPU time 1177.66 seconds
Started Mar 24 03:21:54 PM PDT 24
Finished Mar 24 03:41:32 PM PDT 24
Peak memory 599968 kb
Host smart-84960d20-fe6a-48c8-82ad-e740d3a210ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916147770 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3916147770
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3342030244
Short name T301
Test name
Test status
Simulation time 3029610072 ps
CPU time 245.5 seconds
Started Mar 24 03:20:18 PM PDT 24
Finished Mar 24 03:24:24 PM PDT 24
Peak memory 598864 kb
Host smart-b8583147-d804-4ad3-abfa-a8ec02cdc049
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342030244 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3342030244
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.110001608
Short name T110
Test name
Test status
Simulation time 4987053560 ps
CPU time 420.46 seconds
Started Mar 24 03:20:20 PM PDT 24
Finished Mar 24 03:27:20 PM PDT 24
Peak memory 599908 kb
Host smart-1e9b3616-1408-4028-bfaa-1b9cbb0ea7ee
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11
0001608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.110001608
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.616151973
Short name T532
Test name
Test status
Simulation time 5648395496 ps
CPU time 997.54 seconds
Started Mar 24 03:22:37 PM PDT 24
Finished Mar 24 03:39:15 PM PDT 24
Peak memory 599976 kb
Host smart-8471d137-dafc-4601-944e-20ebf8978c09
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616151973 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.616151973
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.180549778
Short name T307
Test name
Test status
Simulation time 3946387104 ps
CPU time 757.91 seconds
Started Mar 24 03:25:33 PM PDT 24
Finished Mar 24 03:38:11 PM PDT 24
Peak memory 599844 kb
Host smart-8948e00e-7bc9-4609-aa37-2d80b3f5a898
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180549778 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.180549778
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3684613437
Short name T364
Test name
Test status
Simulation time 4380237322 ps
CPU time 650 seconds
Started Mar 24 03:19:42 PM PDT 24
Finished Mar 24 03:30:32 PM PDT 24
Peak memory 599352 kb
Host smart-207d7aa9-68d5-4fff-9eac-834df947722e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3684613437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3684613437
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2596217957
Short name T678
Test name
Test status
Simulation time 22892043347 ps
CPU time 2111.75 seconds
Started Mar 24 03:22:48 PM PDT 24
Finished Mar 24 03:58:01 PM PDT 24
Peak memory 604040 kb
Host smart-4d15bfba-a613-4515-a531-94dcd46c4ad4
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2596217957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2596217957
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4216241537
Short name T574
Test name
Test status
Simulation time 3368080752 ps
CPU time 230.71 seconds
Started Mar 24 03:27:54 PM PDT 24
Finished Mar 24 03:31:45 PM PDT 24
Peak memory 600064 kb
Host smart-3ef38fe6-ba98-4dd1-b5d8-39d790e5893f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4216241537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.4216241537
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.3512796129
Short name T828
Test name
Test status
Simulation time 3444955892 ps
CPU time 314.15 seconds
Started Mar 24 03:25:58 PM PDT 24
Finished Mar 24 03:31:12 PM PDT 24
Peak memory 600908 kb
Host smart-79a31320-6eed-42bc-8d1f-0c9dfbade6ab
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512796129 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_gpio_smoketest.3512796129
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.3463009060
Short name T900
Test name
Test status
Simulation time 2831612830 ps
CPU time 335.32 seconds
Started Mar 24 03:22:03 PM PDT 24
Finished Mar 24 03:27:39 PM PDT 24
Peak memory 599844 kb
Host smart-cd10cd79-8827-4e05-abc7-b7abfd9ebc40
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463009060 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.3463009060
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2464476822
Short name T892
Test name
Test status
Simulation time 2875751672 ps
CPU time 245.22 seconds
Started Mar 24 03:20:10 PM PDT 24
Finished Mar 24 03:24:17 PM PDT 24
Peak memory 599888 kb
Host smart-74187eae-d5a6-4b94-a82c-8277345ff4c2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464476822 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_hmac_enc_idle.2464476822
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2944310401
Short name T901
Test name
Test status
Simulation time 3623755781 ps
CPU time 297.75 seconds
Started Mar 24 03:24:10 PM PDT 24
Finished Mar 24 03:29:08 PM PDT 24
Peak memory 599912 kb
Host smart-1a8546ff-39cc-4551-bad7-2d4f943a8d7d
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944310401 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2944310401
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.3690694585
Short name T857
Test name
Test status
Simulation time 2688406330 ps
CPU time 296.39 seconds
Started Mar 24 03:25:33 PM PDT 24
Finished Mar 24 03:30:30 PM PDT 24
Peak memory 599924 kb
Host smart-06fe4ce4-34a6-4cef-85a1-8e6f54ef0f66
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690694585 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_hmac_smoketest.3690694585
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.760647041
Short name T215
Test name
Test status
Simulation time 4054649616 ps
CPU time 425.51 seconds
Started Mar 24 03:19:32 PM PDT 24
Finished Mar 24 03:26:39 PM PDT 24
Peak memory 599980 kb
Host smart-2efa5569-d5d8-4c24-8377-1e69318aa7b7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760647041 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.760647041
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2530735689
Short name T248
Test name
Test status
Simulation time 64399790486 ps
CPU time 11352.5 seconds
Started Mar 24 03:21:00 PM PDT 24
Finished Mar 24 06:30:14 PM PDT 24
Peak memory 615340 kb
Host smart-272ee8be-4bdf-417f-8425-c711af7b66bc
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2530735689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2530735689
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.263290825
Short name T220
Test name
Test status
Simulation time 4822298320 ps
CPU time 474.37 seconds
Started Mar 24 03:20:57 PM PDT 24
Finished Mar 24 03:28:52 PM PDT 24
Peak memory 607124 kb
Host smart-1fe4fb8c-77fe-43c3-9c68-19b43f1a72cd
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632
90825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.263290825
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.61992062
Short name T321
Test name
Test status
Simulation time 4691589445 ps
CPU time 623.03 seconds
Started Mar 24 03:22:03 PM PDT 24
Finished Mar 24 03:32:27 PM PDT 24
Peak memory 607108 kb
Host smart-2fe8dd28-5c17-4706-b8fc-d9722513d1ae
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61992062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.61992062
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3720915285
Short name T671
Test name
Test status
Simulation time 4372546082 ps
CPU time 395.12 seconds
Started Mar 24 03:23:41 PM PDT 24
Finished Mar 24 03:30:16 PM PDT 24
Peak memory 606700 kb
Host smart-756697da-a60c-4b13-84b0-98939a242157
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3720915285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.3720915285
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.764139864
Short name T320
Test name
Test status
Simulation time 4543930662 ps
CPU time 331.47 seconds
Started Mar 24 03:19:56 PM PDT 24
Finished Mar 24 03:25:28 PM PDT 24
Peak memory 606032 kb
Host smart-94bbec3f-1fa2-4013-b53f-d7aba08c6585
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=764139864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.764139864
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.274726298
Short name T871
Test name
Test status
Simulation time 3871092896 ps
CPU time 371.75 seconds
Started Mar 24 03:20:49 PM PDT 24
Finished Mar 24 03:27:01 PM PDT 24
Peak memory 600404 kb
Host smart-89587af2-7d71-43b7-9735-b5f06b65d9b6
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27472
6298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.274726298
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.753530529
Short name T852
Test name
Test status
Simulation time 2715215896 ps
CPU time 262.46 seconds
Started Mar 24 03:22:00 PM PDT 24
Finished Mar 24 03:26:23 PM PDT 24
Peak memory 599928 kb
Host smart-5545e794-6077-4155-b196-e1608b7bcf3b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753530529 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_kmac_app_rom.753530529
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.1705262292
Short name T99
Test name
Test status
Simulation time 2448635868 ps
CPU time 249.52 seconds
Started Mar 24 03:22:01 PM PDT 24
Finished Mar 24 03:26:11 PM PDT 24
Peak memory 599840 kb
Host smart-5105b05f-0de9-4eea-abad-14eab3370495
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705262292 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.1705262292
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.1966225834
Short name T580
Test name
Test status
Simulation time 2790650120 ps
CPU time 323.1 seconds
Started Mar 24 03:21:32 PM PDT 24
Finished Mar 24 03:26:55 PM PDT 24
Peak memory 599932 kb
Host smart-89b41eef-4204-4b50-9673-7c2d1053373a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966225834 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_idle.1966225834
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.880056848
Short name T680
Test name
Test status
Simulation time 2981549004 ps
CPU time 258.14 seconds
Started Mar 24 03:22:49 PM PDT 24
Finished Mar 24 03:27:07 PM PDT 24
Peak memory 599924 kb
Host smart-05c3b3c7-7419-4042-b762-b7b85cb181de
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880056848 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_kmac_mode_cshake.880056848
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1396986483
Short name T543
Test name
Test status
Simulation time 2472404472 ps
CPU time 275.68 seconds
Started Mar 24 03:21:11 PM PDT 24
Finished Mar 24 03:25:47 PM PDT 24
Peak memory 599856 kb
Host smart-0161b0c2-d75b-4fcf-a282-473c17dfa6d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396986483 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_kmac_mode_kmac.1396986483
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4227875636
Short name T696
Test name
Test status
Simulation time 2633329392 ps
CPU time 217.22 seconds
Started Mar 24 03:19:22 PM PDT 24
Finished Mar 24 03:22:59 PM PDT 24
Peak memory 599816 kb
Host smart-166a71a8-d550-4cf6-a130-2278c95d5b1e
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227875636 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.4227875636
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1986859343
Short name T598
Test name
Test status
Simulation time 3671782089 ps
CPU time 345.64 seconds
Started Mar 24 03:22:44 PM PDT 24
Finished Mar 24 03:28:30 PM PDT 24
Peak memory 599920 kb
Host smart-6882f038-df13-4ae5-8600-ecb0e030ec92
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868593
43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1986859343
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.739599399
Short name T731
Test name
Test status
Simulation time 2948169896 ps
CPU time 308.71 seconds
Started Mar 24 03:25:43 PM PDT 24
Finished Mar 24 03:30:52 PM PDT 24
Peak memory 599912 kb
Host smart-e3df6fc4-d800-4e05-9e48-363027f91075
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739599399 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_kmac_smoketest.739599399
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3881409078
Short name T766
Test name
Test status
Simulation time 3497132482 ps
CPU time 258.07 seconds
Started Mar 24 03:20:18 PM PDT 24
Finished Mar 24 03:24:36 PM PDT 24
Peak memory 599848 kb
Host smart-bb0b7902-5503-460e-bbd2-faae2de5c722
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881409078 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3881409078
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.736010307
Short name T196
Test name
Test status
Simulation time 3802037518 ps
CPU time 256.01 seconds
Started Mar 24 03:21:00 PM PDT 24
Finished Mar 24 03:25:16 PM PDT 24
Peak memory 611188 kb
Host smart-9d2664b0-0f24-4918-9a70-0af1652e6184
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73601030
7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.736010307
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1830000441
Short name T776
Test name
Test status
Simulation time 2482347344 ps
CPU time 149.09 seconds
Started Mar 24 03:21:21 PM PDT 24
Finished Mar 24 03:23:50 PM PDT 24
Peak memory 610720 kb
Host smart-80ee5b62-09ce-4a1d-8651-33e23aa207f9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1830000441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1830000441
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1492945823
Short name T197
Test name
Test status
Simulation time 3072217495 ps
CPU time 141.53 seconds
Started Mar 24 03:23:22 PM PDT 24
Finished Mar 24 03:25:44 PM PDT 24
Peak memory 610632 kb
Host smart-8b40fb77-7f08-4de2-b8bc-4af5cccd0ee6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492945823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1492945823
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.856701208
Short name T418
Test name
Test status
Simulation time 1829390161 ps
CPU time 105.78 seconds
Started Mar 24 03:19:22 PM PDT 24
Finished Mar 24 03:21:08 PM PDT 24
Peak memory 607696 kb
Host smart-8cff2eef-c087-47e5-b9d8-13ab2e19a2a4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=856701208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.856701208
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2131520649
Short name T309
Test name
Test status
Simulation time 2124587149 ps
CPU time 110.22 seconds
Started Mar 24 03:20:22 PM PDT 24
Finished Mar 24 03:22:12 PM PDT 24
Peak memory 606668 kb
Host smart-f9fd2fe5-27b3-41e1-8e25-52c5c27c1068
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131520649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2131520649
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1192802574
Short name T870
Test name
Test status
Simulation time 51880013080 ps
CPU time 5427.23 seconds
Started Mar 24 03:18:53 PM PDT 24
Finished Mar 24 04:49:21 PM PDT 24
Peak memory 607416 kb
Host smart-253f3cdb-f345-4256-8de8-3bbb3528ce87
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192802574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_dev.1192802574
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3437510567
Short name T890
Test name
Test status
Simulation time 50277529032 ps
CPU time 5454.24 seconds
Started Mar 24 03:19:39 PM PDT 24
Finished Mar 24 04:50:34 PM PDT 24
Peak memory 608432 kb
Host smart-f767f9cb-ec53-405d-aec9-e85590066083
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437510567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi
p_sw_lc_walkthrough_prod.3437510567
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.201858494
Short name T609
Test name
Test status
Simulation time 7806511620 ps
CPU time 1117.59 seconds
Started Mar 24 03:24:55 PM PDT 24
Finished Mar 24 03:43:34 PM PDT 24
Peak memory 608216 kb
Host smart-707f236d-049e-47bb-a77c-ec9ea381713f
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=201858494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.201858494
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2771190107
Short name T635
Test name
Test status
Simulation time 45781044228 ps
CPU time 5868.18 seconds
Started Mar 24 03:20:21 PM PDT 24
Finished Mar 24 04:58:11 PM PDT 24
Peak memory 608480 kb
Host smart-94924496-6ecd-44d5-ae94-506ed1c638e9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771190107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_rma.2771190107
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2308770628
Short name T711
Test name
Test status
Simulation time 27446152355 ps
CPU time 2105.32 seconds
Started Mar 24 03:24:57 PM PDT 24
Finished Mar 24 04:00:03 PM PDT 24
Peak memory 607200 kb
Host smart-54850467-c281-408e-a051-baf0ade7f593
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2308770628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun
locks.2308770628
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3375934619
Short name T401
Test name
Test status
Simulation time 17173816180 ps
CPU time 3756.51 seconds
Started Mar 24 03:23:28 PM PDT 24
Finished Mar 24 04:26:05 PM PDT 24
Peak memory 599424 kb
Host smart-062573e1-6e34-41bc-b321-bff33ab47b33
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3375934619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3375934619
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4259359402
Short name T151
Test name
Test status
Simulation time 18495904512 ps
CPU time 3142.05 seconds
Started Mar 24 03:26:43 PM PDT 24
Finished Mar 24 04:19:05 PM PDT 24
Peak memory 600044 kb
Host smart-ec765b9f-e6db-493b-92bc-b0c1dec70400
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4259359402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4259359402
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.3840214373
Short name T170
Test name
Test status
Simulation time 6059444472 ps
CPU time 1007.1 seconds
Started Mar 24 03:19:47 PM PDT 24
Finished Mar 24 03:36:34 PM PDT 24
Peak memory 600132 kb
Host smart-07e06943-4ee2-47c7-914a-bad97723fb90
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3840214373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3840214373
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.1603618315
Short name T903
Test name
Test status
Simulation time 4954536800 ps
CPU time 991.73 seconds
Started Mar 24 03:26:57 PM PDT 24
Finished Mar 24 03:43:29 PM PDT 24
Peak memory 600128 kb
Host smart-b0a01dbf-3061-4aaf-8d55-e3f8dd655d8f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603618315 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_otbn_smoketest.1603618315
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3254499934
Short name T192
Test name
Test status
Simulation time 6035931560 ps
CPU time 649.08 seconds
Started Mar 24 03:23:41 PM PDT 24
Finished Mar 24 03:34:31 PM PDT 24
Peak memory 601428 kb
Host smart-611628aa-195f-422e-b014-822f7c040f0a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3254499934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3254499934
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.993490591
Short name T928
Test name
Test status
Simulation time 8869855136 ps
CPU time 1205.61 seconds
Started Mar 24 03:21:04 PM PDT 24
Finished Mar 24 03:41:10 PM PDT 24
Peak memory 600020 kb
Host smart-134ad568-d183-4483-8e19-ee5c3fb32a90
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=993490591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.993490591
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3002271166
Short name T568
Test name
Test status
Simulation time 7213762122 ps
CPU time 1229.71 seconds
Started Mar 24 03:20:21 PM PDT 24
Finished Mar 24 03:40:51 PM PDT 24
Peak memory 600108 kb
Host smart-071d7a15-557b-480e-aad8-43583237d4c5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3002271166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3002271166
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4050842682
Short name T625
Test name
Test status
Simulation time 8260240080 ps
CPU time 1125.7 seconds
Started Mar 24 03:21:12 PM PDT 24
Finished Mar 24 03:39:58 PM PDT 24
Peak memory 599752 kb
Host smart-9e211976-f889-467c-ba0c-30b391439df4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4050842682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.4050842682
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2640024237
Short name T616
Test name
Test status
Simulation time 4143961966 ps
CPU time 597.66 seconds
Started Mar 24 03:19:52 PM PDT 24
Finished Mar 24 03:29:50 PM PDT 24
Peak memory 599912 kb
Host smart-1a2491e2-f906-4d38-8d8d-53ad1a910b30
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2640024237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2640024237
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2735210674
Short name T406
Test name
Test status
Simulation time 3738887734 ps
CPU time 344.53 seconds
Started Mar 24 03:26:53 PM PDT 24
Finished Mar 24 03:32:38 PM PDT 24
Peak memory 599860 kb
Host smart-7814cd83-8928-4d73-bc5f-ee4907d6217f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735210674 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_otp_ctrl_smoketest.2735210674
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.3385829259
Short name T2
Test name
Test status
Simulation time 2562374120 ps
CPU time 193.53 seconds
Started Mar 24 03:21:59 PM PDT 24
Finished Mar 24 03:25:13 PM PDT 24
Peak memory 598840 kb
Host smart-b4ed3475-1cf4-4b3c-8103-47bcf5792430
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385829259 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3385829259
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.1330816993
Short name T128
Test name
Test status
Simulation time 4038189188 ps
CPU time 604.22 seconds
Started Mar 24 03:24:09 PM PDT 24
Finished Mar 24 03:34:14 PM PDT 24
Peak memory 599484 kb
Host smart-3d28a635-0fc7-4f06-897f-79cb79226761
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330816993 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1330816993
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2072235475
Short name T741
Test name
Test status
Simulation time 29095345831 ps
CPU time 2961.12 seconds
Started Mar 24 03:22:26 PM PDT 24
Finished Mar 24 04:11:47 PM PDT 24
Peak memory 600260 kb
Host smart-b66e8cc0-7868-4564-908b-c57f1b32525c
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207
2235475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2072235475
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3723466263
Short name T549
Test name
Test status
Simulation time 15813028465 ps
CPU time 1128.33 seconds
Started Mar 24 03:24:28 PM PDT 24
Finished Mar 24 03:43:17 PM PDT 24
Peak memory 600404 kb
Host smart-23e4f97c-da3b-42a9-8462-5eafee9be5c2
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3723466263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3723466263
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3261157912
Short name T139
Test name
Test status
Simulation time 7267364840 ps
CPU time 464.09 seconds
Started Mar 24 03:19:54 PM PDT 24
Finished Mar 24 03:27:38 PM PDT 24
Peak memory 600236 kb
Host smart-ced5a7e3-e2c3-4d53-8c6c-b62e4b39169a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261157912 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3261157912
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3208361814
Short name T586
Test name
Test status
Simulation time 3801477834 ps
CPU time 395.84 seconds
Started Mar 24 03:20:27 PM PDT 24
Finished Mar 24 03:27:03 PM PDT 24
Peak memory 606252 kb
Host smart-d85a3d59-983e-4019-a940-ceb83c2c22af
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3208361814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3208361814
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.740840812
Short name T677
Test name
Test status
Simulation time 10720078017 ps
CPU time 1714.86 seconds
Started Mar 24 03:22:19 PM PDT 24
Finished Mar 24 03:50:54 PM PDT 24
Peak memory 600356 kb
Host smart-e455882c-5623-4f05-baa4-3d89b75c77c4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740840812 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.740840812
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4265118410
Short name T135
Test name
Test status
Simulation time 7646742612 ps
CPU time 494.44 seconds
Started Mar 24 03:25:27 PM PDT 24
Finished Mar 24 03:33:42 PM PDT 24
Peak memory 599996 kb
Host smart-74d23b8d-55a8-482c-8af2-f75d6bc771c7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265118410 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4265118410
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1276060531
Short name T777
Test name
Test status
Simulation time 5988527076 ps
CPU time 742.59 seconds
Started Mar 24 03:20:29 PM PDT 24
Finished Mar 24 03:32:51 PM PDT 24
Peak memory 599148 kb
Host smart-a9e320d4-76ad-4916-b887-02ce3ba53f24
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276060531 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1276060531
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3606804438
Short name T130
Test name
Test status
Simulation time 16930196569 ps
CPU time 2209.14 seconds
Started Mar 24 03:20:06 PM PDT 24
Finished Mar 24 03:56:56 PM PDT 24
Peak memory 600772 kb
Host smart-22d663cb-032c-4f5a-901d-52d634629070
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3606804438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3606804438
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.466774244
Short name T129
Test name
Test status
Simulation time 38616945854 ps
CPU time 3989.72 seconds
Started Mar 24 03:24:08 PM PDT 24
Finished Mar 24 04:30:38 PM PDT 24
Peak memory 602380 kb
Host smart-6f4282d4-0a43-45ff-ae0a-5cc9d9a3ceae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466774244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl
eep_power_glitch_reset.466774244
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2292272744
Short name T842
Test name
Test status
Simulation time 5941437000 ps
CPU time 474.93 seconds
Started Mar 24 03:20:00 PM PDT 24
Finished Mar 24 03:27:56 PM PDT 24
Peak memory 606432 kb
Host smart-c045d00b-c890-415f-9ae6-3edea59e62e5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2292272744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2292272744
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1901942176
Short name T695
Test name
Test status
Simulation time 5156865530 ps
CPU time 321.3 seconds
Started Mar 24 03:23:48 PM PDT 24
Finished Mar 24 03:29:10 PM PDT 24
Peak memory 600104 kb
Host smart-43c5b757-9d81-4893-888d-c0d71aa09331
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1901942176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1901942176
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3036822966
Short name T538
Test name
Test status
Simulation time 6073022848 ps
CPU time 395.57 seconds
Started Mar 24 03:27:16 PM PDT 24
Finished Mar 24 03:33:52 PM PDT 24
Peak memory 599920 kb
Host smart-2955c520-1846-42cc-a13f-3099429944d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036822966 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3036822966
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.615603670
Short name T872
Test name
Test status
Simulation time 5858317128 ps
CPU time 878.95 seconds
Started Mar 24 03:22:00 PM PDT 24
Finished Mar 24 03:36:39 PM PDT 24
Peak memory 599208 kb
Host smart-580b5dc7-9bea-4e81-ace4-6d5062c7853f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615603670 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.615603670
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3983043571
Short name T729
Test name
Test status
Simulation time 4893106564 ps
CPU time 579.46 seconds
Started Mar 24 03:25:25 PM PDT 24
Finished Mar 24 03:35:05 PM PDT 24
Peak memory 600020 kb
Host smart-62cabc34-529f-4ea4-a842-b71e3a708ffd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983043571 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3983043571
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3190397145
Short name T934
Test name
Test status
Simulation time 6084398042 ps
CPU time 484.63 seconds
Started Mar 24 03:27:28 PM PDT 24
Finished Mar 24 03:35:33 PM PDT 24
Peak memory 600012 kb
Host smart-7dc89983-0c72-44da-a4a2-59b6aa5d7d34
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190397145 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3190397145
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2261806167
Short name T936
Test name
Test status
Simulation time 5093176680 ps
CPU time 654.47 seconds
Started Mar 24 03:22:18 PM PDT 24
Finished Mar 24 03:33:12 PM PDT 24
Peak memory 599916 kb
Host smart-0080aa37-8e12-4a32-b914-7e6d8150b8c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226
1806167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2261806167
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1952296333
Short name T82
Test name
Test status
Simulation time 8263862887 ps
CPU time 534.9 seconds
Started Mar 24 03:19:56 PM PDT 24
Finished Mar 24 03:28:51 PM PDT 24
Peak memory 599992 kb
Host smart-259fa599-f61f-4e5f-ac29-0826db14a258
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952296333 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1952296333
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1803192589
Short name T269
Test name
Test status
Simulation time 5230850184 ps
CPU time 620.6 seconds
Started Mar 24 03:21:08 PM PDT 24
Finished Mar 24 03:31:28 PM PDT 24
Peak memory 600020 kb
Host smart-c990d015-811e-4e54-8b03-8b0337d44574
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803192589 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1803192589
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3724433404
Short name T381
Test name
Test status
Simulation time 5371560212 ps
CPU time 592.69 seconds
Started Mar 24 03:19:13 PM PDT 24
Finished Mar 24 03:29:05 PM PDT 24
Peak memory 630892 kb
Host smart-106bdb3c-6c55-4a93-9404-abe8a86b9acb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3724433404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3724433404
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.971181461
Short name T712
Test name
Test status
Simulation time 2382341624 ps
CPU time 230.78 seconds
Started Mar 24 03:28:10 PM PDT 24
Finished Mar 24 03:32:00 PM PDT 24
Peak memory 599800 kb
Host smart-05071ece-5154-4625-bef2-9e7d54af4dd5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971181461 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_rstmgr_smoketest.971181461
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4066250534
Short name T584
Test name
Test status
Simulation time 3525826344 ps
CPU time 368.99 seconds
Started Mar 24 03:20:44 PM PDT 24
Finished Mar 24 03:26:54 PM PDT 24
Peak memory 599848 kb
Host smart-b41fd4ad-c4d1-45e4-910f-d0fb5ed28a91
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066250534 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.4066250534
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2587854125
Short name T686
Test name
Test status
Simulation time 2973652606 ps
CPU time 252.87 seconds
Started Mar 24 03:21:51 PM PDT 24
Finished Mar 24 03:26:04 PM PDT 24
Peak memory 599836 kb
Host smart-c4b82999-5b57-4b26-a3d0-a41915baa8d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587854125 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.2587854125
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.258562563
Short name T201
Test name
Test status
Simulation time 2555910404 ps
CPU time 274.35 seconds
Started Mar 24 03:23:58 PM PDT 24
Finished Mar 24 03:28:33 PM PDT 24
Peak memory 599360 kb
Host smart-2a449eb3-f8ee-4c22-bbfc-f11937e0060a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258562563 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.258562563
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3137876937
Short name T134
Test name
Test status
Simulation time 4722562882 ps
CPU time 936.57 seconds
Started Mar 24 03:23:56 PM PDT 24
Finished Mar 24 03:39:33 PM PDT 24
Peak memory 599964 kb
Host smart-4210e8d1-616c-474d-bf99-544ccc874e80
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3137876937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3137876937
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3801328588
Short name T734
Test name
Test status
Simulation time 2557621550 ps
CPU time 241.91 seconds
Started Mar 24 03:26:22 PM PDT 24
Finished Mar 24 03:30:24 PM PDT 24
Peak memory 599924 kb
Host smart-ead19741-18b6-444a-8b82-c3a1fd8fb65b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801328588 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_plic_smoketest.3801328588
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.1462597197
Short name T624
Test name
Test status
Simulation time 2363214120 ps
CPU time 232.84 seconds
Started Mar 24 03:24:17 PM PDT 24
Finished Mar 24 03:28:11 PM PDT 24
Peak memory 599932 kb
Host smart-08eb4b14-2e31-4891-89f1-8a30fa63d665
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462597197 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_irq.1462597197
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.838495198
Short name T266
Test name
Test status
Simulation time 3532933600 ps
CPU time 282.17 seconds
Started Mar 24 03:27:27 PM PDT 24
Finished Mar 24 03:32:10 PM PDT 24
Peak memory 599852 kb
Host smart-87ecae4f-99c3-4a4e-af12-e83258ac6452
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838495198 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_timer_smoketest.838495198
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2330231241
Short name T843
Test name
Test status
Simulation time 3007759983 ps
CPU time 247.43 seconds
Started Mar 24 03:26:46 PM PDT 24
Finished Mar 24 03:30:54 PM PDT 24
Peak memory 600148 kb
Host smart-c2874f6b-6f3b-4ded-8efb-76ae6b4c5ec2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330231
241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2330231241
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3653192035
Short name T305
Test name
Test status
Simulation time 8288527300 ps
CPU time 1327.31 seconds
Started Mar 24 03:23:15 PM PDT 24
Finished Mar 24 03:45:22 PM PDT 24
Peak memory 600208 kb
Host smart-5b6c5414-34e5-4db4-9ed7-6386d43f24d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653192035 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3653192035
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.805096819
Short name T107
Test name
Test status
Simulation time 6883315888 ps
CPU time 906.45 seconds
Started Mar 24 03:22:47 PM PDT 24
Finished Mar 24 03:37:54 PM PDT 24
Peak memory 599924 kb
Host smart-b78c3a33-af54-4c5e-9c03-3f4bb1bf3391
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805096819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sle
ep_sram_ret_contents_no_scramble.805096819
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.81907304
Short name T10
Test name
Test status
Simulation time 6623807097 ps
CPU time 862.06 seconds
Started Mar 24 03:20:04 PM PDT 24
Finished Mar 24 03:34:26 PM PDT 24
Peak memory 616428 kb
Host smart-1c2d5680-f4f0-4d92-b3a1-a50f4afd6d77
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81907304 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.81907304
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.3505900696
Short name T35
Test name
Test status
Simulation time 3377623826 ps
CPU time 424.22 seconds
Started Mar 24 03:21:18 PM PDT 24
Finished Mar 24 03:28:22 PM PDT 24
Peak memory 607176 kb
Host smart-ac06ddc8-dac6-4de0-bcd9-58984a654216
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505900696 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.3505900696
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1666541070
Short name T32
Test name
Test status
Simulation time 3105414980 ps
CPU time 365.78 seconds
Started Mar 24 03:19:58 PM PDT 24
Finished Mar 24 03:26:04 PM PDT 24
Peak memory 598980 kb
Host smart-112de5f3-4b59-44e8-8a9a-758916bf57aa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666541070 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1666541070
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1848816295
Short name T114
Test name
Test status
Simulation time 6672984081 ps
CPU time 711.67 seconds
Started Mar 24 03:21:49 PM PDT 24
Finished Mar 24 03:33:41 PM PDT 24
Peak memory 600464 kb
Host smart-2cece09c-76b5-498a-8408-8408404d1d17
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848816295 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1848816295
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.621153127
Short name T781
Test name
Test status
Simulation time 5559848140 ps
CPU time 619.9 seconds
Started Mar 24 03:20:51 PM PDT 24
Finished Mar 24 03:31:12 PM PDT 24
Peak memory 600376 kb
Host smart-d23c7ec3-92a4-49b2-84b0-2475ae2a09cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621153127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl
_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_
sram_ctrl_scrambled_access.621153127
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3183762380
Short name T733
Test name
Test status
Simulation time 4365528372 ps
CPU time 583.73 seconds
Started Mar 24 03:21:59 PM PDT 24
Finished Mar 24 03:31:43 PM PDT 24
Peak memory 600340 kb
Host smart-e6faf907-31c4-4922-988c-4457615e494d
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183762380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3183762380
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2077862554
Short name T112
Test name
Test status
Simulation time 3847762083 ps
CPU time 450.7 seconds
Started Mar 24 03:22:11 PM PDT 24
Finished Mar 24 03:29:42 PM PDT 24
Peak memory 599724 kb
Host smart-22ad00ad-b871-43da-ac54-f4f0b4081f73
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077862554 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2077862554
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3821988292
Short name T577
Test name
Test status
Simulation time 2986353644 ps
CPU time 244.98 seconds
Started Mar 24 03:26:50 PM PDT 24
Finished Mar 24 03:30:55 PM PDT 24
Peak memory 599928 kb
Host smart-c95c1510-cd55-4a51-a7be-1de69d3731a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821988292 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3821988292
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.779203321
Short name T243
Test name
Test status
Simulation time 4673525773 ps
CPU time 623.95 seconds
Started Mar 24 03:25:59 PM PDT 24
Finished Mar 24 03:36:25 PM PDT 24
Peak memory 603172 kb
Host smart-75018601-34ce-4760-84e8-d5461b03c7ff
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779203321 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.779203321
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2035790541
Short name T868
Test name
Test status
Simulation time 2765947227 ps
CPU time 224.72 seconds
Started Mar 24 03:23:59 PM PDT 24
Finished Mar 24 03:27:44 PM PDT 24
Peak memory 602524 kb
Host smart-efade13a-cfa3-40d6-a6ec-8f12466f7760
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035790541 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2035790541
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4042586448
Short name T412
Test name
Test status
Simulation time 4790811680 ps
CPU time 580.75 seconds
Started Mar 24 03:21:19 PM PDT 24
Finished Mar 24 03:31:00 PM PDT 24
Peak memory 600032 kb
Host smart-626a3cbd-1607-4bc9-8863-ddfb62d4b471
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042586448 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4042586448
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.3790747079
Short name T526
Test name
Test status
Simulation time 2430703668 ps
CPU time 196.4 seconds
Started Mar 24 03:27:14 PM PDT 24
Finished Mar 24 03:30:30 PM PDT 24
Peak memory 599688 kb
Host smart-490cd1f9-0fb3-4bcf-9519-37bcebd276e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790747079 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.3790747079
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest_signed.2550443647
Short name T785
Test name
Test status
Simulation time 8587942534 ps
CPU time 2276.41 seconds
Started Mar 24 03:32:02 PM PDT 24
Finished Mar 24 04:10:00 PM PDT 24
Peak memory 600116 kb
Host smart-369667a8-ae93-4157-a36a-4d8e4bb2b085
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa
ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2550443647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_smoketest_signed.2550443647
Directory /workspace/0.chip_sw_uart_smoketest_signed/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1466054476
Short name T369
Test name
Test status
Simulation time 6068500693 ps
CPU time 722.1 seconds
Started Mar 24 03:18:48 PM PDT 24
Finished Mar 24 03:30:50 PM PDT 24
Peak memory 608112 kb
Host smart-ecbf05c0-fd92-4cb9-a764-a7a5dd452e6f
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466054476 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1466054476
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2912852874
Short name T342
Test name
Test status
Simulation time 5187976995 ps
CPU time 724.79 seconds
Started Mar 24 03:25:03 PM PDT 24
Finished Mar 24 03:37:09 PM PDT 24
Peak memory 607176 kb
Host smart-bad605e6-a750-43b3-bb1d-afd79c66e0b7
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912852874 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2912852874
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1068345911
Short name T847
Test name
Test status
Simulation time 2819769453 ps
CPU time 315.17 seconds
Started Mar 24 03:21:15 PM PDT 24
Finished Mar 24 03:26:31 PM PDT 24
Peak memory 599788 kb
Host smart-f043d562-94d5-4b14-92c8-fbffaf1958d8
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068345911
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1068345911
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.2590744865
Short name T22
Test name
Test status
Simulation time 8000986742 ps
CPU time 1968.65 seconds
Started Mar 24 03:18:46 PM PDT 24
Finished Mar 24 03:51:36 PM PDT 24
Peak memory 599920 kb
Host smart-30367284-2511-4712-bb67-ccc48452b0ca
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25907
44865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2590744865
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.3277215359
Short name T23
Test name
Test status
Simulation time 12331458288 ps
CPU time 2905.19 seconds
Started Mar 24 03:21:04 PM PDT 24
Finished Mar 24 04:09:30 PM PDT 24
Peak memory 599992 kb
Host smart-82df54bb-f04b-429d-8e41-25f10e6f6e0c
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3277215359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3277215359
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.119243437
Short name T123
Test name
Test status
Simulation time 3245649532 ps
CPU time 268.84 seconds
Started Mar 24 03:19:38 PM PDT 24
Finished Mar 24 03:24:08 PM PDT 24
Peak memory 599888 kb
Host smart-48fa0a48-7d7a-430e-96a4-eb2351bf6d64
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119243437
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.119243437
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2286361381
Short name T21
Test name
Test status
Simulation time 3921468892 ps
CPU time 553.45 seconds
Started Mar 24 03:21:08 PM PDT 24
Finished Mar 24 03:30:22 PM PDT 24
Peak memory 599816 kb
Host smart-ba9f67cb-ed2f-4737-b1ea-369a30d5fc59
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228636138
1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2286361381
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.135686564
Short name T898
Test name
Test status
Simulation time 18954101112 ps
CPU time 4165.03 seconds
Started Mar 24 03:22:04 PM PDT 24
Finished Mar 24 04:31:30 PM PDT 24
Peak memory 599940 kb
Host smart-a9ae66a2-8596-4745-b2de-3f4b5b9748db
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=135686564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.135686564
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.1955677101
Short name T174
Test name
Test status
Simulation time 3207245090 ps
CPU time 263.71 seconds
Started Mar 24 03:20:16 PM PDT 24
Finished Mar 24 03:24:40 PM PDT 24
Peak memory 599064 kb
Host smart-7bc93a59-6d60-42c6-8931-dab4cd884b14
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955677101 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1955677101
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_dev.2467062466
Short name T122
Test name
Test status
Simulation time 11582401436 ps
CPU time 1444.84 seconds
Started Mar 24 03:22:11 PM PDT 24
Finished Mar 24 03:46:16 PM PDT 24
Peak memory 609428 kb
Host smart-9da261c6-b1c6-4b87-89f0-a0c012c7b83e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2467062466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2467062466
Directory /workspace/0.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.747821281
Short name T717
Test name
Test status
Simulation time 2894398164 ps
CPU time 162.29 seconds
Started Mar 24 03:24:23 PM PDT 24
Finished Mar 24 03:27:05 PM PDT 24
Peak memory 609096 kb
Host smart-ca4484b0-9c8f-4bc1-a9e1-0701e29ce6f4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=747821281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.747821281
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.chip_tap_straps_rma.2733615763
Short name T854
Test name
Test status
Simulation time 4432731521 ps
CPU time 388.68 seconds
Started Mar 24 03:23:16 PM PDT 24
Finished Mar 24 03:29:45 PM PDT 24
Peak memory 609524 kb
Host smart-cb878b86-fe83-40b8-b211-d41d5d40134e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733615763 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2733615763
Directory /workspace/0.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/0.chip_tap_straps_testunlock0.4014122148
Short name T121
Test name
Test status
Simulation time 5787232885 ps
CPU time 511.22 seconds
Started Mar 24 03:21:07 PM PDT 24
Finished Mar 24 03:29:39 PM PDT 24
Peak memory 617728 kb
Host smart-8042b03b-b43e-4ecb-90ea-60c563c01506
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014122148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.4014122148
Directory /workspace/0.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.2357845071
Short name T39
Test name
Test status
Simulation time 8651432631 ps
CPU time 2122.74 seconds
Started Mar 24 03:29:21 PM PDT 24
Finished Mar 24 04:04:44 PM PDT 24
Peak memory 600124 kb
Host smart-1a53e66e-d9ff-458f-91df-a09e13c2afc8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357845071 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.rom_e2e_asm_init_dev.2357845071
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.51015625
Short name T313
Test name
Test status
Simulation time 8991153193 ps
CPU time 2433.18 seconds
Started Mar 24 03:31:53 PM PDT 24
Finished Mar 24 04:12:27 PM PDT 24
Peak memory 599600 kb
Host smart-78b35737-8b8e-4c89-8b9e-3bafda55fe63
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51015625 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.rom_e2e_asm_init_prod.51015625
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3365425599
Short name T546
Test name
Test status
Simulation time 8593871744 ps
CPU time 2184.8 seconds
Started Mar 24 03:31:09 PM PDT 24
Finished Mar 24 04:07:35 PM PDT 24
Peak memory 600236 kb
Host smart-37297593-875f-49e4-b5fa-1940a29f6064
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365425599 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rom_e2e_asm_init_prod_end.3365425599
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.80477277
Short name T601
Test name
Test status
Simulation time 8482651190 ps
CPU time 1803.86 seconds
Started Mar 24 03:33:59 PM PDT 24
Finished Mar 24 04:04:03 PM PDT 24
Peak memory 600160 kb
Host smart-1d43203b-6fe0-457d-ade4-0912b23047b2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80477277 -assert nopostproc +UVM_TESTNAME=chip_base_tes
t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.rom_e2e_asm_init_rma.80477277
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1267302659
Short name T40
Test name
Test status
Simulation time 7468737017 ps
CPU time 1553.41 seconds
Started Mar 24 03:29:36 PM PDT 24
Finished Mar 24 03:55:30 PM PDT 24
Peak memory 600364 kb
Host smart-2209adc1-58c6-48ea-8538-0c74123df265
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_
flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267302659 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1267302659
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3960880751
Short name T260
Test name
Test status
Simulation time 11618014180 ps
CPU time 3649.42 seconds
Started Mar 24 03:29:14 PM PDT 24
Finished Mar 24 04:30:04 PM PDT 24
Peak memory 601200 kb
Host smart-efa644cd-5aec-4132-a675-95f848495ec3
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with
_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3960880751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3960880751
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3210544415
Short name T784
Test name
Test status
Simulation time 11822558296 ps
CPU time 3154.81 seconds
Started Mar 24 03:31:06 PM PDT 24
Finished Mar 24 04:23:41 PM PDT 24
Peak memory 601092 kb
Host smart-e55fb072-9549-4c24-a019-21e03b7925c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_
with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3210544415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3210544415
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2112143889
Short name T261
Test name
Test status
Simulation time 11492721768 ps
CPU time 3029.33 seconds
Started Mar 24 03:30:58 PM PDT 24
Finished Mar 24 04:21:28 PM PDT 24
Peak memory 601112 kb
Host smart-550071f0-a0f9-436f-a30e-b2efb8525feb
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2112143889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2112143889
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2651598510
Short name T863
Test name
Test status
Simulation time 9823409786 ps
CPU time 2507.1 seconds
Started Mar 24 03:29:16 PM PDT 24
Finished Mar 24 04:11:03 PM PDT 24
Peak memory 601204 kb
Host smart-9b115525-c6f8-41f2-b226-e37481f2c76c
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0
:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2651598510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2651598510
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3263069022
Short name T752
Test name
Test status
Simulation time 8821402740 ps
CPU time 2231.97 seconds
Started Mar 24 03:29:07 PM PDT 24
Finished Mar 24 04:06:19 PM PDT 24
Peak memory 599832 kb
Host smart-125a7cae-ca6e-4444-96d1-4fab698482ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3263069022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3263069022
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2473550547
Short name T745
Test name
Test status
Simulation time 9398215808 ps
CPU time 2076.74 seconds
Started Mar 24 03:31:01 PM PDT 24
Finished Mar 24 04:05:39 PM PDT 24
Peak memory 599072 kb
Host smart-c5450729-3763-4b2a-9df4-c4a7f1221e8c
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with
_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2473550547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2473550547
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.202374110
Short name T623
Test name
Test status
Simulation time 8306061256 ps
CPU time 1853.29 seconds
Started Mar 24 03:28:35 PM PDT 24
Finished Mar 24 03:59:29 PM PDT 24
Peak memory 601100 kb
Host smart-daa9dcf2-1e56-4f85-9019-1206167b4f93
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_
with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=202374110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.202374110
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3057380538
Short name T805
Test name
Test status
Simulation time 8454592334 ps
CPU time 2049.3 seconds
Started Mar 24 03:29:35 PM PDT 24
Finished Mar 24 04:03:45 PM PDT 24
Peak memory 601044 kb
Host smart-1bd3b1bd-27e6-4281-8e64-9da9274d7d38
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3057380538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3057380538
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1665564760
Short name T582
Test name
Test status
Simulation time 7146079320 ps
CPU time 1656.33 seconds
Started Mar 24 03:29:50 PM PDT 24
Finished Mar 24 03:57:26 PM PDT 24
Peak memory 601040 kb
Host smart-2c794f81-ca2b-433f-8f08-3c2fdb1c3c7b
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b
inary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0
:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1665564760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1665564760
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2423715367
Short name T753
Test name
Test status
Simulation time 8702117648 ps
CPU time 1880.04 seconds
Started Mar 24 03:28:45 PM PDT 24
Finished Mar 24 04:00:05 PM PDT 24
Peak memory 599848 kb
Host smart-ba7588f7-b0c8-4618-82f8-ffe27273c015
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_fake_keys:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2423715367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2423715367
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3032969994
Short name T921
Test name
Test status
Simulation time 8525425398 ps
CPU time 2377.82 seconds
Started Mar 24 03:30:24 PM PDT 24
Finished Mar 24 04:10:02 PM PDT 24
Peak memory 601156 kb
Host smart-0d9c8b64-033a-4c7a-96f6-a6bde5f2988a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with_fake_keys
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3032969994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3032969994
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1525898606
Short name T722
Test name
Test status
Simulation time 9079127286 ps
CPU time 2131.29 seconds
Started Mar 24 03:28:37 PM PDT 24
Finished Mar 24 04:04:09 PM PDT 24
Peak memory 601168 kb
Host smart-1e7261fa-0aa4-4a88-b996-e43cc413fde6
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_with_fake_
keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1525898606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1525898606
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935573617
Short name T547
Test name
Test status
Simulation time 9329014840 ps
CPU time 2006.25 seconds
Started Mar 24 03:29:42 PM PDT 24
Finished Mar 24 04:03:10 PM PDT 24
Peak memory 599992 kb
Host smart-e209383f-0c11-411e-8cd9-6e6e0c5c5378
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi
nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_fake_keys:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=935573617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935573617
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3824181702
Short name T608
Test name
Test status
Simulation time 6430849752 ps
CPU time 1817.38 seconds
Started Mar 24 03:30:31 PM PDT 24
Finished Mar 24 04:00:49 PM PDT 24
Peak memory 601024 kb
Host smart-7af36470-ea07-43c0-a892-6ce402bfbd43
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b
inary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,rom_wit
h_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3824181702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3824181702
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.623716483
Short name T37
Test name
Test status
Simulation time 8745427832 ps
CPU time 2093.56 seconds
Started Mar 24 03:29:44 PM PDT 24
Finished Mar 24 04:04:38 PM PDT 24
Peak memory 600144 kb
Host smart-d1fa3a27-df21-45d1-b108-9559dd0afb27
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_
with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=623716483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.623716483
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.3798832932
Short name T682
Test name
Test status
Simulation time 25809755729 ps
CPU time 2887.15 seconds
Started Mar 24 03:30:30 PM PDT 24
Finished Mar 24 04:18:37 PM PDT 24
Peak memory 600808 kb
Host smart-46a8fa99-dce6-41b0-ac08-556a16ebc290
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina
ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798832932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.rom_e2e_shutdown_output.3798832932
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.281777777
Short name T631
Test name
Test status
Simulation time 11420311141 ps
CPU time 3375.14 seconds
Started Mar 24 03:30:19 PM PDT 24
Finished Mar 24 04:26:35 PM PDT 24
Peak memory 599964 kb
Host smart-57757ca3-b9b4-4354-a9aa-9f135edf72eb
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigve
rify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281777777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_alw
ays_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_si
gverify_always_a_bad_b_bad_dev.281777777
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3003885807
Short name T834
Test name
Test status
Simulation time 12193641456 ps
CPU time 2765.51 seconds
Started Mar 24 03:29:34 PM PDT 24
Finished Mar 24 04:15:40 PM PDT 24
Peak memory 600120 kb
Host smart-82eba2c7-9edf-427a-8d73-3913f5a66411
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig
verify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003885807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify
_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2
e_sigverify_always_a_bad_b_bad_prod.3003885807
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2600599637
Short name T737
Test name
Test status
Simulation time 11151140415 ps
CPU time 3007.59 seconds
Started Mar 24 03:31:08 PM PDT 24
Finished Mar 24 04:21:17 PM PDT 24
Peak memory 600140 kb
Host smart-2a123312-63d0-4213-914b-62fd0822bcb9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig
verify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600599637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigve
rify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ro
m_e2e_sigverify_always_a_bad_b_bad_prod_end.2600599637
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2529338897
Short name T856
Test name
Test status
Simulation time 11412351750 ps
CPU time 2832.17 seconds
Started Mar 24 03:31:28 PM PDT 24
Finished Mar 24 04:18:41 PM PDT 24
Peak memory 600296 kb
Host smart-abf4ce2c-453d-4cd4-8396-0a3168372538
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig
verify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529338897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_
always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e
_sigverify_always_a_bad_b_bad_rma.2529338897
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3244143721
Short name T770
Test name
Test status
Simulation time 10003420400 ps
CPU time 2760.78 seconds
Started Mar 24 03:28:51 PM PDT 24
Finished Mar 24 04:14:52 PM PDT 24
Peak memory 601172 kb
Host smart-d754afbe-04d0-4789-8c29-190befeaf0c0
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_si
gverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244143721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2
e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3244143721
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3601545484
Short name T602
Test name
Test status
Simulation time 9026798796 ps
CPU time 1857.76 seconds
Started Mar 24 03:30:50 PM PDT 24
Finished Mar 24 04:01:49 PM PDT 24
Peak memory 599128 kb
Host smart-2592ec4a-9745-4ae6-8c95-8d87af6a30fc
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601545484 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3601545484
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3012812300
Short name T672
Test name
Test status
Simulation time 8371048214 ps
CPU time 1904.16 seconds
Started Mar 24 03:28:19 PM PDT 24
Finished Mar 24 04:00:04 PM PDT 24
Peak memory 600224 kb
Host smart-4aca6dc6-528c-4ade-80d2-6965efcb2f23
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012812300 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3012812300
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2098238436
Short name T923
Test name
Test status
Simulation time 8207562056 ps
CPU time 2281.43 seconds
Started Mar 24 03:30:50 PM PDT 24
Finished Mar 24 04:08:52 PM PDT 24
Peak memory 600176 kb
Host smart-77cade68-84dc-40aa-aa7b-a8eca72b7513
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098238436 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2098238436
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3115371350
Short name T658
Test name
Test status
Simulation time 6806847576 ps
CPU time 1637.11 seconds
Started Mar 24 03:30:41 PM PDT 24
Finished Mar 24 03:57:58 PM PDT 24
Peak memory 600060 kb
Host smart-ad5a49fe-928a-4ef3-80fe-763ff3a488db
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115371350 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3115371350
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.355306456
Short name T667
Test name
Test status
Simulation time 8602624852 ps
CPU time 2005.22 seconds
Started Mar 24 03:28:17 PM PDT 24
Finished Mar 24 04:01:43 PM PDT 24
Peak memory 599836 kb
Host smart-8902a152-1749-4cbb-b39d-95c537d897cc
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o
t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355306456 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.355306456
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3618525831
Short name T283
Test name
Test status
Simulation time 8207377645 ps
CPU time 2114.41 seconds
Started Mar 24 03:29:41 PM PDT 24
Finished Mar 24 04:04:55 PM PDT 24
Peak memory 599792 kb
Host smart-42b93726-ad31-4ddc-87a4-1f9a08c1048a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618525831 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3618525831
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3750633681
Short name T721
Test name
Test status
Simulation time 8769562616 ps
CPU time 2140.54 seconds
Started Mar 24 03:29:55 PM PDT 24
Finished Mar 24 04:05:36 PM PDT 24
Peak memory 600072 kb
Host smart-d2697ae6-b93e-4245-96ce-b5d6c48917f2
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750633681 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3750633681
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1757833105
Short name T914
Test name
Test status
Simulation time 8212137292 ps
CPU time 2104.54 seconds
Started Mar 24 03:28:44 PM PDT 24
Finished Mar 24 04:03:48 PM PDT 24
Peak memory 600228 kb
Host smart-44a1e7ea-9f9f-4fc4-a664-e01cd6692f66
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o
t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757833105 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1757833105
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1555124240
Short name T38
Test name
Test status
Simulation time 6719916000 ps
CPU time 1817.8 seconds
Started Mar 24 03:28:55 PM PDT 24
Finished Mar 24 03:59:14 PM PDT 24
Peak memory 600060 kb
Host smart-10ec1047-6600-4c81-9532-0085e5933780
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555124240 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1555124240
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.3053805794
Short name T685
Test name
Test status
Simulation time 8851455718 ps
CPU time 2048.52 seconds
Started Mar 24 03:25:39 PM PDT 24
Finished Mar 24 03:59:48 PM PDT 24
Peak memory 600052 kb
Host smart-6540c51a-010f-4d04-a7ca-dc146d99fd6f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0
,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3053805794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3053805794
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.3279814922
Short name T567
Test name
Test status
Simulation time 10261421256 ps
CPU time 2558.47 seconds
Started Mar 24 03:31:10 PM PDT 24
Finished Mar 24 04:13:49 PM PDT 24
Peak memory 600120 kb
Host smart-02807dd4-2876-413a-a5f0-d7c6299bfa31
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3279814922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3279814922
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.243777712
Short name T345
Test name
Test status
Simulation time 15997748962 ps
CPU time 2000.1 seconds
Started Mar 24 03:26:41 PM PDT 24
Finished Mar 24 04:00:01 PM PDT 24
Peak memory 607388 kb
Host smart-e6435b51-2dd5-4c10-84e3-20268dda6486
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=243777712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.243777712
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.857440453
Short name T826
Test name
Test status
Simulation time 2212875278 ps
CPU time 92.56 seconds
Started Mar 24 03:25:52 PM PDT 24
Finished Mar 24 03:27:25 PM PDT 24
Peak memory 606668 kb
Host smart-794f96c1-174d-4a14-bdb4-6e1b8a4a42a6
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857440453 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.857440453
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.3110304883
Short name T72
Test name
Test status
Simulation time 12910730320 ps
CPU time 1284.9 seconds
Started Mar 24 03:28:08 PM PDT 24
Finished Mar 24 03:49:33 PM PDT 24
Peak memory 599504 kb
Host smart-b0d99133-6732-4d62-99a3-1c2a2cd897bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110304883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3
110304883
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2119295550
Short name T58
Test name
Test status
Simulation time 4578038648 ps
CPU time 446.72 seconds
Started Mar 24 03:35:21 PM PDT 24
Finished Mar 24 03:42:50 PM PDT 24
Peak memory 607100 kb
Host smart-9e1ba36e-f1b4-4cfc-a47e-44a2f0a20504
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
119295550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2119295550
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.2701679720
Short name T791
Test name
Test status
Simulation time 2578452728 ps
CPU time 279.82 seconds
Started Mar 24 03:27:25 PM PDT 24
Finished Mar 24 03:32:05 PM PDT 24
Peak memory 599996 kb
Host smart-bb93f795-64a2-40c9-9d96-004d9b9b9ec0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2701679720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2701679720
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.102067192
Short name T636
Test name
Test status
Simulation time 2398910046 ps
CPU time 258.57 seconds
Started Mar 24 03:33:16 PM PDT 24
Finished Mar 24 03:37:35 PM PDT 24
Peak memory 599908 kb
Host smart-b958233e-9101-4e61-a025-cc58ca3ad5ae
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102067192 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.102067192
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4053227609
Short name T916
Test name
Test status
Simulation time 2691784649 ps
CPU time 200.38 seconds
Started Mar 24 03:32:42 PM PDT 24
Finished Mar 24 03:36:03 PM PDT 24
Peak memory 599980 kb
Host smart-4ba478cb-b28e-46de-ab45-b57fd2e644c9
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053
227609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.4053227609
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.539849343
Short name T633
Test name
Test status
Simulation time 3005838694 ps
CPU time 238.85 seconds
Started Mar 24 03:37:45 PM PDT 24
Finished Mar 24 03:41:44 PM PDT 24
Peak memory 600000 kb
Host smart-75bf5896-16bc-40bb-a146-88980396b27b
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=539849343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.539849343
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.3732714196
Short name T656
Test name
Test status
Simulation time 2161102614 ps
CPU time 255.26 seconds
Started Mar 24 03:33:09 PM PDT 24
Finished Mar 24 03:37:25 PM PDT 24
Peak memory 599808 kb
Host smart-d11b2349-26a1-4537-8976-2a13e64826ca
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732714196 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3732714196
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.2020866375
Short name T539
Test name
Test status
Simulation time 2763008608 ps
CPU time 224.34 seconds
Started Mar 24 03:33:51 PM PDT 24
Finished Mar 24 03:37:37 PM PDT 24
Peak memory 599888 kb
Host smart-a3ff7499-09bf-43a9-928a-d7c68de57391
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020866375 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2020866375
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.3623062371
Short name T395
Test name
Test status
Simulation time 2630477965 ps
CPU time 264.59 seconds
Started Mar 24 03:33:40 PM PDT 24
Finished Mar 24 03:38:06 PM PDT 24
Peak memory 599624 kb
Host smart-d865ce9d-88e8-48bd-88a0-0767495bab21
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623062371 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3623062371
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.1276541191
Short name T545
Test name
Test status
Simulation time 2823085978 ps
CPU time 297.66 seconds
Started Mar 24 03:38:41 PM PDT 24
Finished Mar 24 03:43:39 PM PDT 24
Peak memory 599936 kb
Host smart-5a40930e-1338-4258-ba4b-d74ffd4069ba
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276541191 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.1276541191
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3754517890
Short name T182
Test name
Test status
Simulation time 3333041521 ps
CPU time 320.99 seconds
Started Mar 24 03:33:53 PM PDT 24
Finished Mar 24 03:39:15 PM PDT 24
Peak memory 599372 kb
Host smart-eeac8b44-96a2-4cfa-bb06-6b1cc046234b
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3754517890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3754517890
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1491408367
Short name T861
Test name
Test status
Simulation time 4293446374 ps
CPU time 517.35 seconds
Started Mar 24 03:33:15 PM PDT 24
Finished Mar 24 03:41:53 PM PDT 24
Peak memory 607116 kb
Host smart-60e9d45d-9116-44eb-83c1-56b2d273c71a
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1491408367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1491408367
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.798191729
Short name T818
Test name
Test status
Simulation time 9659043928 ps
CPU time 2369.12 seconds
Started Mar 24 03:34:06 PM PDT 24
Finished Mar 24 04:13:36 PM PDT 24
Peak memory 599988 kb
Host smart-92176dac-d919-4841-8e21-6b5be85459cd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=798191729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.798191729
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1519425178
Short name T888
Test name
Test status
Simulation time 8101799076 ps
CPU time 1932.73 seconds
Started Mar 24 03:33:53 PM PDT 24
Finished Mar 24 04:06:06 PM PDT 24
Peak memory 599808 kb
Host smart-9821e38e-9fb3-4491-93f2-59393fb4aa5c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519425178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg
le.1519425178
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2402550349
Short name T927
Test name
Test status
Simulation time 3788037570 ps
CPU time 479.03 seconds
Started Mar 24 03:33:19 PM PDT 24
Finished Mar 24 03:41:18 PM PDT 24
Peak memory 599472 kb
Host smart-ac559e5a-4468-4a48-9000-d28510046875
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2402550349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2402550349
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.744258872
Short name T56
Test name
Test status
Simulation time 255277656230 ps
CPU time 11753.7 seconds
Started Mar 24 03:32:16 PM PDT 24
Finished Mar 24 06:48:11 PM PDT 24
Peak memory 599616 kb
Host smart-18d89b8a-0789-43fa-9377-7d30bf550070
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744258872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.744258872
Directory /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.689871527
Short name T78
Test name
Test status
Simulation time 3285930254 ps
CPU time 311.04 seconds
Started Mar 24 03:32:21 PM PDT 24
Finished Mar 24 03:37:32 PM PDT 24
Peak memory 599052 kb
Host smart-5201cb07-8176-4d77-b623-9510d41a4582
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689871527 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_alert_test.689871527
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.400752334
Short name T282
Test name
Test status
Simulation time 4163937186 ps
CPU time 354.25 seconds
Started Mar 24 03:31:39 PM PDT 24
Finished Mar 24 03:37:34 PM PDT 24
Peak memory 599892 kb
Host smart-554ee7da-109d-45b7-9178-71608e5697c9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400752334 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.400752334
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3985016785
Short name T141
Test name
Test status
Simulation time 6875319610 ps
CPU time 600.36 seconds
Started Mar 24 03:32:22 PM PDT 24
Finished Mar 24 03:42:23 PM PDT 24
Peak memory 599968 kb
Host smart-7d517115-6317-4f32-8a68-904e42ce0299
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3985016785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3985016785
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1292744299
Short name T660
Test name
Test status
Simulation time 2411409764 ps
CPU time 275.25 seconds
Started Mar 24 03:38:05 PM PDT 24
Finished Mar 24 03:42:41 PM PDT 24
Peak memory 599864 kb
Host smart-42b9020d-4204-41cf-b9e6-e257080cfbef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292744299 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.1292744299
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1470561860
Short name T742
Test name
Test status
Simulation time 9471012146 ps
CPU time 988.17 seconds
Started Mar 24 03:33:22 PM PDT 24
Finished Mar 24 03:49:51 PM PDT 24
Peak memory 599908 kb
Host smart-a71f7971-41cf-4835-9322-62b4a2a986de
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1470561860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1470561860
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3893215764
Short name T645
Test name
Test status
Simulation time 5334673230 ps
CPU time 582.9 seconds
Started Mar 24 03:32:40 PM PDT 24
Finished Mar 24 03:42:23 PM PDT 24
Peak memory 600088 kb
Host smart-fc15e186-bf0e-400a-a4b0-296a1e852ce5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3893215764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3893215764
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1587760212
Short name T439
Test name
Test status
Simulation time 7053937040 ps
CPU time 1295.38 seconds
Started Mar 24 03:35:00 PM PDT 24
Finished Mar 24 03:56:36 PM PDT 24
Peak memory 606636 kb
Host smart-71fdda7b-34fb-4e45-960c-e0fce0bc5107
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587760212 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.1587760212
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4157689875
Short name T536
Test name
Test status
Simulation time 9944915881 ps
CPU time 1138.42 seconds
Started Mar 24 03:35:41 PM PDT 24
Finished Mar 24 03:54:40 PM PDT 24
Peak memory 612624 kb
Host smart-2262be84-9775-4634-a6e9-13597f397533
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=4157689875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.4157689875
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2322132790
Short name T657
Test name
Test status
Simulation time 4264751336 ps
CPU time 794.96 seconds
Started Mar 24 03:39:04 PM PDT 24
Finished Mar 24 03:52:20 PM PDT 24
Peak memory 602808 kb
Host smart-35b79815-d660-445d-8c0d-d48db3d91bc7
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322132790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.2322132790
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1895116437
Short name T866
Test name
Test status
Simulation time 3336696680 ps
CPU time 527.89 seconds
Started Mar 24 03:35:44 PM PDT 24
Finished Mar 24 03:44:32 PM PDT 24
Peak memory 602788 kb
Host smart-0ff16c3a-68b4-4723-b475-fe83f74adabc
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895116437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1895116437
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2710042442
Short name T774
Test name
Test status
Simulation time 3915747850 ps
CPU time 640.52 seconds
Started Mar 24 03:39:15 PM PDT 24
Finished Mar 24 03:49:56 PM PDT 24
Peak memory 603096 kb
Host smart-bdf6c0cd-999b-44c9-a7f0-c37dacfe6f4d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710042442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2710042442
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.967990546
Short name T663
Test name
Test status
Simulation time 5174002152 ps
CPU time 823.75 seconds
Started Mar 24 03:35:41 PM PDT 24
Finished Mar 24 03:49:25 PM PDT 24
Peak memory 602904 kb
Host smart-20aa56e6-adb5-4813-996c-95014b0a2bfe
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967990546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl
kmgr_external_clk_src_for_sw_slow_dev.967990546
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2160502421
Short name T604
Test name
Test status
Simulation time 5186826464 ps
CPU time 865.55 seconds
Started Mar 24 03:38:27 PM PDT 24
Finished Mar 24 03:52:53 PM PDT 24
Peak memory 602872 kb
Host smart-9611b8d7-9365-4fa5-b12a-7b1576b623a8
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160502421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2160502421
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.971475234
Short name T162
Test name
Test status
Simulation time 4704771292 ps
CPU time 620.38 seconds
Started Mar 24 03:34:36 PM PDT 24
Finished Mar 24 03:44:57 PM PDT 24
Peak memory 603220 kb
Host smart-f4739e18-7962-4a82-a2f8-704e4f4ddd80
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971475234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.971475234
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.278159745
Short name T335
Test name
Test status
Simulation time 3423255872 ps
CPU time 280.15 seconds
Started Mar 24 03:35:41 PM PDT 24
Finished Mar 24 03:40:21 PM PDT 24
Peak memory 599944 kb
Host smart-6b86b127-9309-4a64-a9cf-d0924aa173b9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278159745 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_clkmgr_jitter.278159745
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.452608815
Short name T849
Test name
Test status
Simulation time 3821764192 ps
CPU time 505.97 seconds
Started Mar 24 03:40:36 PM PDT 24
Finished Mar 24 03:49:03 PM PDT 24
Peak memory 599944 kb
Host smart-e266ea03-505f-4ba8-b016-a85844ddffd9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452608815 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.452608815
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1018250229
Short name T559
Test name
Test status
Simulation time 2751970285 ps
CPU time 238.98 seconds
Started Mar 24 03:36:53 PM PDT 24
Finished Mar 24 03:40:53 PM PDT 24
Peak memory 599916 kb
Host smart-9a80ccc7-ed23-4a6f-ae8f-25c6c31a96c2
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018250229 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1018250229
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1024154566
Short name T800
Test name
Test status
Simulation time 5041138572 ps
CPU time 469.11 seconds
Started Mar 24 03:35:03 PM PDT 24
Finished Mar 24 03:42:53 PM PDT 24
Peak memory 599996 kb
Host smart-b66dce6e-3132-4158-a1fa-63f681159555
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024154566 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1024154566
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1106744970
Short name T597
Test name
Test status
Simulation time 5723114500 ps
CPU time 614.18 seconds
Started Mar 24 03:38:42 PM PDT 24
Finished Mar 24 03:48:56 PM PDT 24
Peak memory 599420 kb
Host smart-8ca1e3d0-7c67-43b3-a671-5f4d75088bb0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106744970 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1106744970
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3150510090
Short name T644
Test name
Test status
Simulation time 5309114730 ps
CPU time 542.99 seconds
Started Mar 24 03:33:47 PM PDT 24
Finished Mar 24 03:42:50 PM PDT 24
Peak memory 600008 kb
Host smart-a4e82667-6063-433b-8ad9-3038360dea76
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150510090 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3150510090
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1502389497
Short name T30
Test name
Test status
Simulation time 4211616042 ps
CPU time 375.28 seconds
Started Mar 24 03:35:00 PM PDT 24
Finished Mar 24 03:41:15 PM PDT 24
Peak memory 599944 kb
Host smart-0fd3295c-0899-4b22-b37d-81867cb2dcce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502389497 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1502389497
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.923782960
Short name T84
Test name
Test status
Simulation time 9345764308 ps
CPU time 1109 seconds
Started Mar 24 03:34:17 PM PDT 24
Finished Mar 24 03:52:46 PM PDT 24
Peak memory 599996 kb
Host smart-5ec3150e-4a6f-4115-85b8-af8d808bf8d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923782960
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.923782960
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2763156340
Short name T757
Test name
Test status
Simulation time 3549231044 ps
CPU time 463.25 seconds
Started Mar 24 03:34:19 PM PDT 24
Finished Mar 24 03:42:02 PM PDT 24
Peak memory 599996 kb
Host smart-3caa27dc-a189-458f-ad56-4472eaf280ad
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763156340 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2763156340
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2748001867
Short name T573
Test name
Test status
Simulation time 4703340982 ps
CPU time 657.23 seconds
Started Mar 24 03:35:17 PM PDT 24
Finished Mar 24 03:46:15 PM PDT 24
Peak memory 599912 kb
Host smart-e41fee43-fbd5-46f7-a89d-aac5eff62f92
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748001867 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2748001867
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4073243809
Short name T860
Test name
Test status
Simulation time 3299762154 ps
CPU time 213.37 seconds
Started Mar 24 03:38:41 PM PDT 24
Finished Mar 24 03:42:15 PM PDT 24
Peak memory 599920 kb
Host smart-e7d6bbef-f883-46bd-ad69-c7e3dbcb8c31
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073243809 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_clkmgr_smoketest.4073243809
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.529412464
Short name T594
Test name
Test status
Simulation time 7926634070 ps
CPU time 1974.38 seconds
Started Mar 24 03:32:38 PM PDT 24
Finished Mar 24 04:05:33 PM PDT 24
Peak memory 600132 kb
Host smart-5a2b0ea7-114b-4c7c-903e-34c59bd3da22
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529412464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.529412464
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2203525946
Short name T690
Test name
Test status
Simulation time 17001593551 ps
CPU time 2898.12 seconds
Started Mar 24 03:37:16 PM PDT 24
Finished Mar 24 04:25:34 PM PDT 24
Peak memory 600132 kb
Host smart-7ac9ec11-230f-4739-82ec-655638c9f1f1
User root
Command /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203525946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_csrng_edn_concurrency_reduced_freq.2203525946
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1891738196
Short name T739
Test name
Test status
Simulation time 3240741830 ps
CPU time 424.34 seconds
Started Mar 24 03:33:59 PM PDT 24
Finished Mar 24 03:41:04 PM PDT 24
Peak memory 599896 kb
Host smart-2e321e72-7875-4107-92ad-37b187d4d07d
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
38196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1891738196
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.3073379615
Short name T529
Test name
Test status
Simulation time 2989964224 ps
CPU time 285.03 seconds
Started Mar 24 03:33:51 PM PDT 24
Finished Mar 24 03:38:36 PM PDT 24
Peak memory 599820 kb
Host smart-31fdb342-028b-4ef9-b628-62f6b0907235
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073379615 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3073379615
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.3654822243
Short name T655
Test name
Test status
Simulation time 2377700200 ps
CPU time 233.47 seconds
Started Mar 24 03:38:50 PM PDT 24
Finished Mar 24 03:42:44 PM PDT 24
Peak memory 599932 kb
Host smart-4092a365-bc42-460d-96d7-4c58ba65b757
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654822243 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_csrng_smoketest.3654822243
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4090039229
Short name T749
Test name
Test status
Simulation time 5240802360 ps
CPU time 561.04 seconds
Started Mar 24 03:28:50 PM PDT 24
Finished Mar 24 03:38:11 PM PDT 24
Peak memory 600100 kb
Host smart-7f1f199e-e8b2-45d1-a835-f07b89669238
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4090039229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.4090039229
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.2197426529
Short name T392
Test name
Test status
Simulation time 3433409906 ps
CPU time 873.87 seconds
Started Mar 24 03:32:36 PM PDT 24
Finished Mar 24 03:47:10 PM PDT 24
Peak memory 600040 kb
Host smart-9722393b-1e5f-40c7-ad34-240b11fb4bd7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197426529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.2197426529
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.2850607638
Short name T394
Test name
Test status
Simulation time 2897138160 ps
CPU time 428.51 seconds
Started Mar 24 03:32:45 PM PDT 24
Finished Mar 24 03:39:54 PM PDT 24
Peak memory 600128 kb
Host smart-16ed4060-ad74-493a-bf32-3068d34450b7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850607638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
boot_mode.2850607638
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3409134389
Short name T802
Test name
Test status
Simulation time 4862966520 ps
CPU time 1182.8 seconds
Started Mar 24 03:33:38 PM PDT 24
Finished Mar 24 03:53:22 PM PDT 24
Peak memory 600128 kb
Host smart-147af05f-2ceb-433a-9cd9-a72bd61f91ee
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409134389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3409134389
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3529112431
Short name T333
Test name
Test status
Simulation time 4808664334 ps
CPU time 830.32 seconds
Started Mar 24 03:32:58 PM PDT 24
Finished Mar 24 03:46:49 PM PDT 24
Peak memory 600184 kb
Host smart-4b66008f-f88f-410d-8ebd-6469f2ce278f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529112431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3529112431
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.2180850349
Short name T880
Test name
Test status
Simulation time 2929447712 ps
CPU time 855.3 seconds
Started Mar 24 03:33:31 PM PDT 24
Finished Mar 24 03:47:47 PM PDT 24
Peak memory 605576 kb
Host smart-88b01f0d-3d12-4f8f-b54c-e10aef74edc9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180850349 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_edn_kat.2180850349
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.2823403414
Short name T653
Test name
Test status
Simulation time 6785417060 ps
CPU time 1349.8 seconds
Started Mar 24 03:34:37 PM PDT 24
Finished Mar 24 03:57:07 PM PDT 24
Peak memory 599956 kb
Host smart-2f3e2fd5-d00a-49d7-b2ed-9665baf25b0f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823403414 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2823403414
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.888903554
Short name T642
Test name
Test status
Simulation time 3168325718 ps
CPU time 345.04 seconds
Started Mar 24 03:35:23 PM PDT 24
Finished Mar 24 03:41:09 PM PDT 24
Peak memory 599908 kb
Host smart-bf2e7819-6bf7-4748-9181-e56b67a23852
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88
8903554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.888903554
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.767697758
Short name T367
Test name
Test status
Simulation time 7425854350 ps
CPU time 1723.37 seconds
Started Mar 24 03:33:54 PM PDT 24
Finished Mar 24 04:02:39 PM PDT 24
Peak memory 600104 kb
Host smart-11b509da-77f1-470b-a193-1279e4f03971
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=767697758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.767697758
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3268057111
Short name T587
Test name
Test status
Simulation time 3008533712 ps
CPU time 292.08 seconds
Started Mar 24 03:35:07 PM PDT 24
Finished Mar 24 03:40:01 PM PDT 24
Peak memory 599820 kb
Host smart-c29b820b-cdb8-4367-9fb5-f2439795260d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268057111
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3268057111
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2934248574
Short name T530
Test name
Test status
Simulation time 3418649630 ps
CPU time 527.9 seconds
Started Mar 24 03:37:17 PM PDT 24
Finished Mar 24 03:46:05 PM PDT 24
Peak memory 599912 kb
Host smart-9eae5be0-4482-4141-8b7b-e7dc81b8094f
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2934248574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2934248574
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.1136117170
Short name T761
Test name
Test status
Simulation time 2953338800 ps
CPU time 228.2 seconds
Started Mar 24 03:28:15 PM PDT 24
Finished Mar 24 03:32:04 PM PDT 24
Peak memory 599896 kb
Host smart-48be0d39-dcb8-4fd2-b387-4c20639ff2af
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136117170 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_example_concurrency.1136117170
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.2348729495
Short name T724
Test name
Test status
Simulation time 2901575908 ps
CPU time 260.37 seconds
Started Mar 24 03:27:17 PM PDT 24
Finished Mar 24 03:31:38 PM PDT 24
Peak memory 599956 kb
Host smart-5b39540e-4f25-4205-93f9-2416eef3fd74
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348729495 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.2348729495
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.2134795690
Short name T808
Test name
Test status
Simulation time 2472745500 ps
CPU time 182.63 seconds
Started Mar 24 03:27:04 PM PDT 24
Finished Mar 24 03:30:07 PM PDT 24
Peak memory 599856 kb
Host smart-6e7a204a-01c3-4609-b87e-50d42f063aeb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134795690 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_example_manufacturer.2134795690
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.3002137611
Short name T679
Test name
Test status
Simulation time 2164987248 ps
CPU time 111.1 seconds
Started Mar 24 03:26:32 PM PDT 24
Finished Mar 24 03:28:23 PM PDT 24
Peak memory 599524 kb
Host smart-cb60ae8c-f18b-4a95-8a70-03875fd95455
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002137611 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.3002137611
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2082197692
Short name T763
Test name
Test status
Simulation time 59573697001 ps
CPU time 10653.9 seconds
Started Mar 24 03:27:51 PM PDT 24
Finished Mar 24 06:25:26 PM PDT 24
Peak memory 608232 kb
Host smart-4f6573cd-aa2a-48b7-aa17-f6118b6ab7f8
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2082197692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2082197692
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.386741555
Short name T534
Test name
Test status
Simulation time 5785964328 ps
CPU time 764.86 seconds
Started Mar 24 03:36:46 PM PDT 24
Finished Mar 24 03:49:32 PM PDT 24
Peak memory 601472 kb
Host smart-56d783c0-667d-419c-8242-e676499ea4bc
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=386741555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.386741555
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1722495997
Short name T933
Test name
Test status
Simulation time 5586461456 ps
CPU time 966.76 seconds
Started Mar 24 03:29:55 PM PDT 24
Finished Mar 24 03:46:02 PM PDT 24
Peak memory 600080 kb
Host smart-3c0b462e-ee6e-4555-bc81-71d879b91d5c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722495997 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_flash_ctrl_access.1722495997
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2482637709
Short name T693
Test name
Test status
Simulation time 5200344025 ps
CPU time 949.15 seconds
Started Mar 24 03:30:22 PM PDT 24
Finished Mar 24 03:46:11 PM PDT 24
Peak memory 599972 kb
Host smart-aef9ce85-da19-4cc4-aafe-fb87613ba14a
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482637709 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2482637709
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3053885294
Short name T754
Test name
Test status
Simulation time 7108293025 ps
CPU time 1057 seconds
Started Mar 24 03:37:40 PM PDT 24
Finished Mar 24 03:55:18 PM PDT 24
Peak memory 600072 kb
Host smart-0929f2d1-5da2-441f-8c9a-dd78bc290339
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053885294 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3053885294
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2477164194
Short name T782
Test name
Test status
Simulation time 5358452798 ps
CPU time 993.7 seconds
Started Mar 24 03:28:35 PM PDT 24
Finished Mar 24 03:45:09 PM PDT 24
Peak memory 599996 kb
Host smart-bcf94915-99e9-4374-8ce9-85ae48cf7057
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477164194 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2477164194
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.937172335
Short name T239
Test name
Test status
Simulation time 3661430520 ps
CPU time 321.68 seconds
Started Mar 24 03:28:08 PM PDT 24
Finished Mar 24 03:33:30 PM PDT 24
Peak memory 599960 kb
Host smart-e876b504-1af5-4db2-8949-bd9c2aebf923
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937172335 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.937172335
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.776019710
Short name T746
Test name
Test status
Simulation time 4846034099 ps
CPU time 475.02 seconds
Started Mar 24 03:29:27 PM PDT 24
Finished Mar 24 03:37:22 PM PDT 24
Peak memory 600260 kb
Host smart-b9f540e7-48d7-4659-9c9f-2d101bcb2f04
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77
6019710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.776019710
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3222953733
Short name T585
Test name
Test status
Simulation time 5274558240 ps
CPU time 1242.13 seconds
Started Mar 24 03:38:11 PM PDT 24
Finished Mar 24 03:58:53 PM PDT 24
Peak memory 599904 kb
Host smart-dab378ff-0ae7-45c0-ab22-80fdf99571b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222953733 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3222953733
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3027957852
Short name T143
Test name
Test status
Simulation time 4168644351 ps
CPU time 599.45 seconds
Started Mar 24 03:30:17 PM PDT 24
Finished Mar 24 03:40:17 PM PDT 24
Peak memory 599864 kb
Host smart-774db032-30cd-4a7a-85fc-2402a8bff8f4
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3027957852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3027957852
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2862022718
Short name T771
Test name
Test status
Simulation time 5333305985 ps
CPU time 699.09 seconds
Started Mar 24 03:39:34 PM PDT 24
Finished Mar 24 03:51:14 PM PDT 24
Peak memory 599984 kb
Host smart-bfd2ea7f-42e9-4218-b846-c696911e2e4c
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2862022718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2862022718
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.3973675721
Short name T931
Test name
Test status
Simulation time 23853271300 ps
CPU time 2240.64 seconds
Started Mar 24 03:27:36 PM PDT 24
Finished Mar 24 04:04:58 PM PDT 24
Peak memory 606512 kb
Host smart-0fe13d32-92be-486a-a170-e15cddbc0b6f
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973675721 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3973675721
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4214470612
Short name T221
Test name
Test status
Simulation time 26559647466 ps
CPU time 1941.94 seconds
Started Mar 24 03:36:50 PM PDT 24
Finished Mar 24 04:09:13 PM PDT 24
Peak memory 604796 kb
Host smart-7784533d-c2cb-42cd-8265-2cf27bda6859
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4214470612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.4214470612
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3564948118
Short name T821
Test name
Test status
Simulation time 2926735148 ps
CPU time 271.82 seconds
Started Mar 24 03:42:17 PM PDT 24
Finished Mar 24 03:46:49 PM PDT 24
Peak memory 599904 kb
Host smart-2dafa43c-e438-4e94-a388-92fb8bb77272
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3564948118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3564948118
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.2574863901
Short name T13
Test name
Test status
Simulation time 2375489959 ps
CPU time 280.84 seconds
Started Mar 24 03:39:44 PM PDT 24
Finished Mar 24 03:44:26 PM PDT 24
Peak memory 600980 kb
Host smart-b0c979a8-583f-488a-b857-7835ef0e97c9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574863901 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_gpio_smoketest.2574863901
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.4013816830
Short name T783
Test name
Test status
Simulation time 2930640744 ps
CPU time 332.37 seconds
Started Mar 24 03:33:29 PM PDT 24
Finished Mar 24 03:39:03 PM PDT 24
Peak memory 599848 kb
Host smart-343bda17-06d4-44fd-bd4d-9d0496c15bf5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013816830 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.4013816830
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1524351145
Short name T922
Test name
Test status
Simulation time 2819165664 ps
CPU time 232.86 seconds
Started Mar 24 03:33:34 PM PDT 24
Finished Mar 24 03:37:27 PM PDT 24
Peak memory 599948 kb
Host smart-b6d87be8-4d9a-41dd-9a9c-52db2941be0f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524351145 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_hmac_enc_idle.1524351145
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.813039518
Short name T788
Test name
Test status
Simulation time 3159716609 ps
CPU time 326.13 seconds
Started Mar 24 03:34:16 PM PDT 24
Finished Mar 24 03:39:43 PM PDT 24
Peak memory 599912 kb
Host smart-a3b4901e-3708-415c-a5cd-4630831031f7
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813039518 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.813039518
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2940770081
Short name T407
Test name
Test status
Simulation time 3081637008 ps
CPU time 224.87 seconds
Started Mar 24 03:37:06 PM PDT 24
Finished Mar 24 03:40:51 PM PDT 24
Peak memory 599856 kb
Host smart-f070edb3-443d-4324-a003-0c725bb26661
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940770081 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2940770081
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.1472681268
Short name T555
Test name
Test status
Simulation time 2570996092 ps
CPU time 380.51 seconds
Started Mar 24 03:38:53 PM PDT 24
Finished Mar 24 03:45:13 PM PDT 24
Peak memory 599892 kb
Host smart-bc3097da-4225-46a1-a0cf-6fc690f98944
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472681268 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_hmac_smoketest.1472681268
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2800418282
Short name T841
Test name
Test status
Simulation time 4049147452 ps
CPU time 428.82 seconds
Started Mar 24 03:28:54 PM PDT 24
Finished Mar 24 03:36:04 PM PDT 24
Peak memory 599924 kb
Host smart-6eb77dab-315e-4a4b-bbfc-fcbf322b8f4c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800418282 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2800418282
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.638225525
Short name T211
Test name
Test status
Simulation time 5867757750 ps
CPU time 1139.84 seconds
Started Mar 24 03:28:02 PM PDT 24
Finished Mar 24 03:47:03 PM PDT 24
Peak memory 599824 kb
Host smart-3bb01069-5387-4644-b110-8adab1b52dea
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638225525 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.638225525
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2484596118
Short name T214
Test name
Test status
Simulation time 5705382656 ps
CPU time 757.76 seconds
Started Mar 24 03:28:19 PM PDT 24
Finished Mar 24 03:40:57 PM PDT 24
Peak memory 599428 kb
Host smart-4cee9f1d-e66c-453a-8b49-180b3d3d4ba5
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484596118 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2484596118
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.289486592
Short name T216
Test name
Test status
Simulation time 4421845940 ps
CPU time 767.71 seconds
Started Mar 24 03:27:39 PM PDT 24
Finished Mar 24 03:40:27 PM PDT 24
Peak memory 599860 kb
Host smart-2d8e5579-a7de-42f3-97d4-f4d134c0884d
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289486592 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.289486592
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1459949697
Short name T654
Test name
Test status
Simulation time 64130366120 ps
CPU time 10725.8 seconds
Started Mar 24 03:26:44 PM PDT 24
Finished Mar 24 06:25:31 PM PDT 24
Peak memory 615368 kb
Host smart-741c8e68-8d33-4cb8-9e54-c4e924184f75
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1459949697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1459949697
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2663522336
Short name T323
Test name
Test status
Simulation time 5484060176 ps
CPU time 579.67 seconds
Started Mar 24 03:32:45 PM PDT 24
Finished Mar 24 03:42:25 PM PDT 24
Peak memory 607036 kb
Host smart-a99e2819-fbef-496d-872c-08fb32295f76
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2663522336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2663522336
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2849582700
Short name T738
Test name
Test status
Simulation time 3701164913 ps
CPU time 464.12 seconds
Started Mar 24 03:37:57 PM PDT 24
Finished Mar 24 03:45:41 PM PDT 24
Peak memory 607072 kb
Host smart-1acc46f7-8f56-4c49-9f48-063bede496bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2849582700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.2849582700
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1252547688
Short name T319
Test name
Test status
Simulation time 4387995612 ps
CPU time 587.28 seconds
Started Mar 24 03:33:17 PM PDT 24
Finished Mar 24 03:43:05 PM PDT 24
Peak memory 606708 kb
Host smart-4a855bd1-14ab-4fb4-9ef2-311eddc36f11
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1252547688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1252547688
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3701399987
Short name T328
Test name
Test status
Simulation time 3674696242 ps
CPU time 403.55 seconds
Started Mar 24 03:33:30 PM PDT 24
Finished Mar 24 03:40:14 PM PDT 24
Peak memory 600468 kb
Host smart-b899db5d-49d2-4838-ad93-123228f2a11e
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370139
9987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.3701399987
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3372253705
Short name T325
Test name
Test status
Simulation time 4747429928 ps
CPU time 430.55 seconds
Started Mar 24 03:34:04 PM PDT 24
Finished Mar 24 03:41:15 PM PDT 24
Peak memory 600108 kb
Host smart-0b4a30f8-fdd6-4cd3-9ee9-cef0cd502ce4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
53705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3372253705
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2707327372
Short name T326
Test name
Test status
Simulation time 10957818994 ps
CPU time 3567.77 seconds
Started Mar 24 03:34:36 PM PDT 24
Finished Mar 24 04:34:05 PM PDT 24
Peak memory 600304 kb
Host smart-28bb3ee4-9cb1-47a2-95e5-4caab5949336
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
27372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2707327372
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.1089634549
Short name T81
Test name
Test status
Simulation time 2665739400 ps
CPU time 281.15 seconds
Started Mar 24 03:33:47 PM PDT 24
Finished Mar 24 03:38:28 PM PDT 24
Peak memory 599848 kb
Host smart-473b7b34-55b2-4192-ac9a-a1d80ad08c0c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089634549 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.1089634549
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.1082745374
Short name T386
Test name
Test status
Simulation time 2933321774 ps
CPU time 252.24 seconds
Started Mar 24 03:28:21 PM PDT 24
Finished Mar 24 03:32:34 PM PDT 24
Peak memory 599848 kb
Host smart-d95c3b91-5e9e-435e-9a35-5f6bde9d1911
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082745374 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_entropy.1082745374
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.1669619087
Short name T306
Test name
Test status
Simulation time 2626563898 ps
CPU time 237.39 seconds
Started Mar 24 03:33:58 PM PDT 24
Finished Mar 24 03:37:56 PM PDT 24
Peak memory 599792 kb
Host smart-dad62973-c955-44f8-9d2a-3bad181cce72
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669619087 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_idle.1669619087
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3943490361
Short name T100
Test name
Test status
Simulation time 2618512200 ps
CPU time 225.37 seconds
Started Mar 24 03:35:20 PM PDT 24
Finished Mar 24 03:39:05 PM PDT 24
Peak memory 599924 kb
Host smart-ba388f5d-119f-4f67-8097-5ad83579768c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943490361 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3943490361
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1674924706
Short name T637
Test name
Test status
Simulation time 2465569716 ps
CPU time 296.77 seconds
Started Mar 24 03:36:12 PM PDT 24
Finished Mar 24 03:41:10 PM PDT 24
Peak memory 599928 kb
Host smart-172c19f9-7e9a-465a-bdc0-dbb8a5cb0edc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674924706 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.1674924706
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1491958916
Short name T564
Test name
Test status
Simulation time 2241818471 ps
CPU time 244.73 seconds
Started Mar 24 03:33:38 PM PDT 24
Finished Mar 24 03:37:43 PM PDT 24
Peak memory 599944 kb
Host smart-755be990-cc5a-4c79-99fa-6824e8a500e4
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491958916 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1491958916
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1899769619
Short name T552
Test name
Test status
Simulation time 3134270211 ps
CPU time 287.77 seconds
Started Mar 24 03:36:54 PM PDT 24
Finished Mar 24 03:41:42 PM PDT 24
Peak memory 599892 kb
Host smart-40af9abf-f241-434f-b711-da90c7dc67ce
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997696
19 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1899769619
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.2032834829
Short name T97
Test name
Test status
Simulation time 3052044620 ps
CPU time 332.99 seconds
Started Mar 24 03:39:58 PM PDT 24
Finished Mar 24 03:45:32 PM PDT 24
Peak memory 599960 kb
Host smart-175bf192-ebfa-42a9-8618-ef032bed69c8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032834829 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_smoketest.2032834829
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.926890904
Short name T572
Test name
Test status
Simulation time 3616421760 ps
CPU time 347.63 seconds
Started Mar 24 03:29:01 PM PDT 24
Finished Mar 24 03:34:49 PM PDT 24
Peak memory 599836 kb
Host smart-d341154b-1140-49c4-b3ba-bda0694724fa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926890904 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.926890904
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2910630308
Short name T819
Test name
Test status
Simulation time 3181352783 ps
CPU time 204.21 seconds
Started Mar 24 03:28:39 PM PDT 24
Finished Mar 24 03:32:04 PM PDT 24
Peak memory 611136 kb
Host smart-a23942eb-78a1-4416-99e0-4a547a322309
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106303
08 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2910630308
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3978359634
Short name T697
Test name
Test status
Simulation time 10920554475 ps
CPU time 1051.34 seconds
Started Mar 24 03:28:32 PM PDT 24
Finished Mar 24 03:46:04 PM PDT 24
Peak memory 612268 kb
Host smart-d4ab91c8-f38e-40a2-9714-f44b645f4fae
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978359634 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3978359634
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3161212311
Short name T416
Test name
Test status
Simulation time 2987749743 ps
CPU time 120.27 seconds
Started Mar 24 03:29:30 PM PDT 24
Finished Mar 24 03:31:31 PM PDT 24
Peak memory 607668 kb
Host smart-e8249fcb-b565-4a7f-99f1-c3275de60bee
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3161212311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3161212311
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.959729154
Short name T276
Test name
Test status
Simulation time 2427254589 ps
CPU time 119.03 seconds
Started Mar 24 03:30:38 PM PDT 24
Finished Mar 24 03:32:38 PM PDT 24
Peak memory 606696 kb
Host smart-fde79b00-d15b-4326-81d3-c8a74e2ad8c5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959729154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST
_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.959729154
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3696354056
Short name T223
Test name
Test status
Simulation time 51093708199 ps
CPU time 4629.05 seconds
Started Mar 24 03:29:39 PM PDT 24
Finished Mar 24 04:46:50 PM PDT 24
Peak memory 607432 kb
Host smart-6de85359-3df9-4c15-83a6-dafea2491ee3
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696354056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_dev.3696354056
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1953120415
Short name T829
Test name
Test status
Simulation time 11107950552 ps
CPU time 954.58 seconds
Started Mar 24 03:30:10 PM PDT 24
Finished Mar 24 03:46:05 PM PDT 24
Peak memory 607268 kb
Host smart-6a3e72c6-6174-44e2-90cf-a7fb6b8a30dd
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953120415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1953120415
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2597117385
Short name T225
Test name
Test status
Simulation time 45635133330 ps
CPU time 5510.3 seconds
Started Mar 24 03:30:33 PM PDT 24
Finished Mar 24 05:02:25 PM PDT 24
Peak memory 608464 kb
Host smart-b641f07c-d0c4-4f0c-baf5-96e889235601
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597117385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_rma.2597117385
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1704999789
Short name T706
Test name
Test status
Simulation time 26765535192 ps
CPU time 2030.37 seconds
Started Mar 24 03:30:02 PM PDT 24
Finished Mar 24 04:03:53 PM PDT 24
Peak memory 607216 kb
Host smart-9a328ed6-b98e-48ff-9c2a-2bc40e81dc03
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1704999789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun
locks.1704999789
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2326048344
Short name T147
Test name
Test status
Simulation time 17237784752 ps
CPU time 3215.16 seconds
Started Mar 24 03:33:48 PM PDT 24
Finished Mar 24 04:27:24 PM PDT 24
Peak memory 599996 kb
Host smart-7c22492c-10da-476a-80a7-375320a3b43c
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2326048344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2326048344
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4149255007
Short name T909
Test name
Test status
Simulation time 18049626779 ps
CPU time 3675.62 seconds
Started Mar 24 03:32:19 PM PDT 24
Finished Mar 24 04:33:35 PM PDT 24
Peak memory 600100 kb
Host smart-32942340-1fba-4ac7-ad68-1f87b9065ce8
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4149255007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4149255007
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2531864066
Short name T390
Test name
Test status
Simulation time 24767376760 ps
CPU time 4219.15 seconds
Started Mar 24 03:39:34 PM PDT 24
Finished Mar 24 04:49:54 PM PDT 24
Peak memory 600024 kb
Host smart-43a1c3f7-79e7-4257-84af-88d412518264
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531864066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2531864066
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.964052095
Short name T291
Test name
Test status
Simulation time 2934206732 ps
CPU time 541.29 seconds
Started Mar 24 03:33:42 PM PDT 24
Finished Mar 24 03:42:44 PM PDT 24
Peak memory 599976 kb
Host smart-6185f506-cda4-4b21-8455-02cfb33fe93e
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964052095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.964052095
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.1345361619
Short name T835
Test name
Test status
Simulation time 5911255352 ps
CPU time 1103.66 seconds
Started Mar 24 03:31:31 PM PDT 24
Finished Mar 24 03:49:56 PM PDT 24
Peak memory 600136 kb
Host smart-2e979052-45c9-4069-b956-d18b24f85889
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1345361619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1345361619
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.2254332626
Short name T713
Test name
Test status
Simulation time 5566133976 ps
CPU time 1049.72 seconds
Started Mar 24 03:38:42 PM PDT 24
Finished Mar 24 03:56:12 PM PDT 24
Peak memory 600096 kb
Host smart-7c6cfc5c-9a3a-425b-b469-df6e4f34ea7f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254332626 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_otbn_smoketest.2254332626
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.581805195
Short name T551
Test name
Test status
Simulation time 8935657824 ps
CPU time 1063.81 seconds
Started Mar 24 03:31:23 PM PDT 24
Finished Mar 24 03:49:08 PM PDT 24
Peak memory 600060 kb
Host smart-d7aeeaa0-53ae-4891-acbe-e369ac3cc375
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=581805195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.581805195
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3815608319
Short name T285
Test name
Test status
Simulation time 8094464184 ps
CPU time 1395.98 seconds
Started Mar 24 03:29:15 PM PDT 24
Finished Mar 24 03:52:32 PM PDT 24
Peak memory 600128 kb
Host smart-c1f819ca-f20f-458c-8ee4-8af8b8c93363
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3815608319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3815608319
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1477270387
Short name T648
Test name
Test status
Simulation time 8089889626 ps
CPU time 1587.09 seconds
Started Mar 24 03:29:09 PM PDT 24
Finished Mar 24 03:55:37 PM PDT 24
Peak memory 600032 kb
Host smart-8ea92c22-f42c-41dd-b9da-a0040ed9c5c6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1477270387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1477270387
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1267678427
Short name T694
Test name
Test status
Simulation time 3896726120 ps
CPU time 690.56 seconds
Started Mar 24 03:30:02 PM PDT 24
Finished Mar 24 03:41:33 PM PDT 24
Peak memory 599900 kb
Host smart-881145a3-1f96-4194-b535-1942ee5464be
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1267678427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1267678427
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3090289639
Short name T765
Test name
Test status
Simulation time 3444316556 ps
CPU time 302.93 seconds
Started Mar 24 03:38:31 PM PDT 24
Finished Mar 24 03:43:34 PM PDT 24
Peak memory 599832 kb
Host smart-255bf0cd-ce97-4b3c-9226-627b8ffbab1f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090289639 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.3090289639
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.2933818596
Short name T355
Test name
Test status
Simulation time 3120226712 ps
CPU time 261.05 seconds
Started Mar 24 03:27:29 PM PDT 24
Finished Mar 24 03:31:50 PM PDT 24
Peak memory 600876 kb
Host smart-874ae29d-a772-4d14-bb3f-a9ea34675855
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933818596 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2933818596
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.3965130030
Short name T237
Test name
Test status
Simulation time 3225369194 ps
CPU time 243.31 seconds
Started Mar 24 03:35:06 PM PDT 24
Finished Mar 24 03:39:10 PM PDT 24
Peak memory 599852 kb
Host smart-8abddff9-5818-4afe-a035-3740a23584ae
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965130030 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.3965130030
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.2875206354
Short name T911
Test name
Test status
Simulation time 4597546724 ps
CPU time 712.82 seconds
Started Mar 24 03:36:35 PM PDT 24
Finished Mar 24 03:48:28 PM PDT 24
Peak memory 599920 kb
Host smart-671f0f88-de29-4ca4-aae9-fa8516826e68
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875206354 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2875206354
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3749431393
Short name T702
Test name
Test status
Simulation time 12221508795 ps
CPU time 1433.55 seconds
Started Mar 24 03:30:22 PM PDT 24
Finished Mar 24 03:54:16 PM PDT 24
Peak memory 600776 kb
Host smart-c29273e2-b62e-49c8-8eca-c1933b4a6535
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749
431393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3749431393
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.937000147
Short name T411
Test name
Test status
Simulation time 19484898262 ps
CPU time 2456.35 seconds
Started Mar 24 03:38:53 PM PDT 24
Finished Mar 24 04:19:49 PM PDT 24
Peak memory 600224 kb
Host smart-8b91554e-45a8-437f-9cf4-d51e2dcc8725
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937
000147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.937000147
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2715231554
Short name T628
Test name
Test status
Simulation time 15623145556 ps
CPU time 1400.05 seconds
Started Mar 24 03:31:36 PM PDT 24
Finished Mar 24 03:54:57 PM PDT 24
Peak memory 600656 kb
Host smart-892b12ff-025c-4a74-84b7-f3c4a8cef765
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2715231554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2715231554
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2265933825
Short name T65
Test name
Test status
Simulation time 21004293400 ps
CPU time 1548.43 seconds
Started Mar 24 03:41:47 PM PDT 24
Finished Mar 24 04:07:35 PM PDT 24
Peak memory 601048 kb
Host smart-a1387797-a4d2-4b53-8653-c258b3b34b2e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2265933825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2265933825
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.242630678
Short name T3
Test name
Test status
Simulation time 6633075224 ps
CPU time 498.11 seconds
Started Mar 24 03:32:23 PM PDT 24
Finished Mar 24 03:40:42 PM PDT 24
Peak memory 606332 kb
Host smart-3dacc695-d62a-46d3-ab95-8d7cbbcf80bf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=242630678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.242630678
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.211910848
Short name T138
Test name
Test status
Simulation time 7099667666 ps
CPU time 538.6 seconds
Started Mar 24 03:30:22 PM PDT 24
Finished Mar 24 03:39:21 PM PDT 24
Peak memory 600168 kb
Host smart-705c944d-7134-47a3-8fe1-c2fba1c656e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211910848 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.211910848
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4285320310
Short name T703
Test name
Test status
Simulation time 4809962616 ps
CPU time 317.83 seconds
Started Mar 24 03:30:15 PM PDT 24
Finished Mar 24 03:35:33 PM PDT 24
Peak memory 606584 kb
Host smart-6b87018e-7a6d-48f4-9898-7d61ebb336ba
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4285320310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.4285320310
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1947591470
Short name T338
Test name
Test status
Simulation time 14243581251 ps
CPU time 1729.52 seconds
Started Mar 24 03:32:33 PM PDT 24
Finished Mar 24 04:01:23 PM PDT 24
Peak memory 600420 kb
Host smart-29fdd3f4-b6f4-43c4-9480-6a9f599f17cf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947591470 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1947591470
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4077909795
Short name T294
Test name
Test status
Simulation time 7260651584 ps
CPU time 514.99 seconds
Started Mar 24 03:31:33 PM PDT 24
Finished Mar 24 03:40:08 PM PDT 24
Peak memory 599172 kb
Host smart-ab92f0c1-e068-4ea6-91fe-90e0e12f226c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077909795 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.4077909795
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2491758232
Short name T651
Test name
Test status
Simulation time 19846853268 ps
CPU time 2705.12 seconds
Started Mar 24 03:30:38 PM PDT 24
Finished Mar 24 04:15:44 PM PDT 24
Peak memory 601712 kb
Host smart-d2b727bf-d7ee-4a60-aa86-f84b98b812d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2491758232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2491758232
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3262930276
Short name T17
Test name
Test status
Simulation time 20588675040 ps
CPU time 1677.05 seconds
Started Mar 24 03:41:54 PM PDT 24
Finished Mar 24 04:09:52 PM PDT 24
Peak memory 600936 kb
Host smart-ffa89b88-09aa-46c9-8f50-4ba7c1998ea3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3262930276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3262930276
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4161372349
Short name T858
Test name
Test status
Simulation time 34599781000 ps
CPU time 2968.48 seconds
Started Mar 24 03:30:52 PM PDT 24
Finished Mar 24 04:20:21 PM PDT 24
Peak memory 600916 kb
Host smart-82614561-4e2e-4822-83f2-3b0a5276701b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161372349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.4161372349
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4176780454
Short name T235
Test name
Test status
Simulation time 2685724708 ps
CPU time 254.88 seconds
Started Mar 24 03:30:26 PM PDT 24
Finished Mar 24 03:34:41 PM PDT 24
Peak memory 599848 kb
Host smart-c2521ddf-6ac7-44d1-8acf-97fc960ac5f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176780454 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4176780454
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2892417247
Short name T437
Test name
Test status
Simulation time 5235381840 ps
CPU time 598.79 seconds
Started Mar 24 03:31:31 PM PDT 24
Finished Mar 24 03:41:30 PM PDT 24
Peak memory 606132 kb
Host smart-b7320df6-3bdc-4785-8465-615dd0a7c7ec
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2892417247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2892417247
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2585358740
Short name T155
Test name
Test status
Simulation time 4768272388 ps
CPU time 480.47 seconds
Started Mar 24 03:34:11 PM PDT 24
Finished Mar 24 03:42:12 PM PDT 24
Peak memory 599252 kb
Host smart-0068a715-ca67-4f44-bdaf-9a9b08bdc719
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853587
40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2585358740
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2879877603
Short name T804
Test name
Test status
Simulation time 6240328940 ps
CPU time 445.96 seconds
Started Mar 24 03:36:04 PM PDT 24
Finished Mar 24 03:43:30 PM PDT 24
Peak memory 599756 kb
Host smart-887350c3-e8c6-4915-aee9-c1dd13b09343
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2879877603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2879877603
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1296776997
Short name T740
Test name
Test status
Simulation time 4861354158 ps
CPU time 417.7 seconds
Started Mar 24 03:40:01 PM PDT 24
Finished Mar 24 03:46:59 PM PDT 24
Peak memory 599940 kb
Host smart-fdc354cc-719d-48db-a2a5-ac290396dac9
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296776997 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1296776997
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1628993700
Short name T755
Test name
Test status
Simulation time 6938506776 ps
CPU time 1382.59 seconds
Started Mar 24 03:31:23 PM PDT 24
Finished Mar 24 03:54:26 PM PDT 24
Peak memory 599988 kb
Host smart-ed06872c-e0aa-468f-813e-89e6e91c43a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628993700 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1628993700
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.472576765
Short name T90
Test name
Test status
Simulation time 4947744230 ps
CPU time 480.15 seconds
Started Mar 24 03:32:56 PM PDT 24
Finished Mar 24 03:40:57 PM PDT 24
Peak memory 600028 kb
Host smart-e0b276e0-01ed-4235-b7c6-2131a36cecf2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472576765 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.472576765
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.52515700
Short name T941
Test name
Test status
Simulation time 5035353528 ps
CPU time 542.93 seconds
Started Mar 24 03:38:44 PM PDT 24
Finished Mar 24 03:47:47 PM PDT 24
Peak memory 599924 kb
Host smart-941cc8eb-4798-4ddb-816b-3b3139455693
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52515700 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.52515700
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.884435663
Short name T839
Test name
Test status
Simulation time 3937497728 ps
CPU time 589.76 seconds
Started Mar 24 03:32:16 PM PDT 24
Finished Mar 24 03:42:06 PM PDT 24
Peak memory 599920 kb
Host smart-95448a22-c764-48e1-b744-d69cb4a94594
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884
435663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.884435663
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1547066637
Short name T86
Test name
Test status
Simulation time 10835422056 ps
CPU time 1810.63 seconds
Started Mar 24 03:30:56 PM PDT 24
Finished Mar 24 04:01:07 PM PDT 24
Peak memory 600176 kb
Host smart-2f9773cd-4578-42a7-9573-2937f0008809
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1547066637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1547066637
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1594304267
Short name T271
Test name
Test status
Simulation time 5191985610 ps
CPU time 508.39 seconds
Started Mar 24 03:29:51 PM PDT 24
Finished Mar 24 03:38:20 PM PDT 24
Peak memory 599980 kb
Host smart-25ccba86-e0f6-4981-bda6-25f632b75354
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594304267 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1594304267
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2667965413
Short name T380
Test name
Test status
Simulation time 5554660518 ps
CPU time 730.61 seconds
Started Mar 24 03:28:58 PM PDT 24
Finished Mar 24 03:41:09 PM PDT 24
Peak memory 630520 kb
Host smart-6142649c-12a3-4e51-bfa0-987718608f72
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2667965413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2667965413
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2334885604
Short name T845
Test name
Test status
Simulation time 3018107752 ps
CPU time 254.28 seconds
Started Mar 24 03:38:30 PM PDT 24
Finished Mar 24 03:42:45 PM PDT 24
Peak memory 599904 kb
Host smart-ad15bc68-8474-409b-bf0e-37e319a9b7cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334885604 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_rstmgr_smoketest.2334885604
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2395548914
Short name T688
Test name
Test status
Simulation time 4823222832 ps
CPU time 568.19 seconds
Started Mar 24 03:29:50 PM PDT 24
Finished Mar 24 03:39:19 PM PDT 24
Peak memory 599888 kb
Host smart-3a3548da-ba55-48d6-aead-7eb7729015c1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395548914 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rstmgr_sw_req.2395548914
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3150649183
Short name T681
Test name
Test status
Simulation time 2308175192 ps
CPU time 262.27 seconds
Started Mar 24 03:29:36 PM PDT 24
Finished Mar 24 03:33:59 PM PDT 24
Peak memory 599796 kb
Host smart-57815a1c-fc0b-417c-888c-3e34e198a8f0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150649183 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3150649183
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2896329109
Short name T264
Test name
Test status
Simulation time 3479721244 ps
CPU time 351.61 seconds
Started Mar 24 03:35:59 PM PDT 24
Finished Mar 24 03:41:51 PM PDT 24
Peak memory 599964 kb
Host smart-8976be1a-47ef-4f34-abf5-5b3a358af360
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2896329109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2896329109
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.144329222
Short name T200
Test name
Test status
Simulation time 3179433074 ps
CPU time 234.44 seconds
Started Mar 24 03:36:48 PM PDT 24
Finished Mar 24 03:40:43 PM PDT 24
Peak memory 599268 kb
Host smart-5c02e79e-7620-460e-b078-60d8adb869e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144329222 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.144329222
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.553380133
Short name T383
Test name
Test status
Simulation time 2687762400 ps
CPU time 195.31 seconds
Started Mar 24 03:36:59 PM PDT 24
Finished Mar 24 03:40:15 PM PDT 24
Peak memory 599628 kb
Host smart-3a57a439-9477-48ec-a0dc-a8f5cf652b5b
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553380133 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.553380133
Directory /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.906007935
Short name T410
Test name
Test status
Simulation time 5223061560 ps
CPU time 797.39 seconds
Started Mar 24 03:33:02 PM PDT 24
Finished Mar 24 03:46:21 PM PDT 24
Peak memory 599928 kb
Host smart-8387481e-d5bd-49f7-8025-9fb6be2973d2
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90600
7935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.906007935
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.720777650
Short name T402
Test name
Test status
Simulation time 5493268350 ps
CPU time 895.68 seconds
Started Mar 24 03:32:46 PM PDT 24
Finished Mar 24 03:47:42 PM PDT 24
Peak memory 599864 kb
Host smart-97f7b8e8-568e-4775-82eb-a6dce19b6dfa
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=720777650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.720777650
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1794756739
Short name T49
Test name
Test status
Simulation time 5391128700 ps
CPU time 417.3 seconds
Started Mar 24 03:36:50 PM PDT 24
Finished Mar 24 03:43:48 PM PDT 24
Peak memory 608132 kb
Host smart-2ab1fe71-5e9c-470b-84ab-1fae5ed4bf5b
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794756739 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1794756739
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.546394143
Short name T50
Test name
Test status
Simulation time 3844902760 ps
CPU time 587.65 seconds
Started Mar 24 03:36:49 PM PDT 24
Finished Mar 24 03:46:37 PM PDT 24
Peak memory 607204 kb
Host smart-55e1d97f-1d6f-4377-b211-2f8002393c58
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546394
143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.546394143
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2290074511
Short name T727
Test name
Test status
Simulation time 3143895200 ps
CPU time 287.95 seconds
Started Mar 24 03:38:49 PM PDT 24
Finished Mar 24 03:43:37 PM PDT 24
Peak memory 599944 kb
Host smart-3ed62d16-2ec6-4dd3-8ce1-3b610e75d770
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290074511 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_plic_smoketest.2290074511
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.829028681
Short name T267
Test name
Test status
Simulation time 3170106728 ps
CPU time 225.34 seconds
Started Mar 24 03:32:57 PM PDT 24
Finished Mar 24 03:36:42 PM PDT 24
Peak memory 599944 kb
Host smart-9068b2f1-a70b-47d4-9b6a-c643ec695f2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829028681 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_irq.829028681
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.349729560
Short name T895
Test name
Test status
Simulation time 2475471768 ps
CPU time 229.92 seconds
Started Mar 24 03:38:22 PM PDT 24
Finished Mar 24 03:42:13 PM PDT 24
Peak memory 599820 kb
Host smart-bd56686d-dc33-4bb8-9190-f9ab6dfa4059
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349729560 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_smoketest.349729560
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.920231103
Short name T371
Test name
Test status
Simulation time 2810630911 ps
CPU time 274.27 seconds
Started Mar 24 03:34:51 PM PDT 24
Finished Mar 24 03:39:26 PM PDT 24
Peak memory 599872 kb
Host smart-ff31c1d2-39e3-4764-a9b6-de35fc60cddf
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9202311
03 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.920231103
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.486619814
Short name T63
Test name
Test status
Simulation time 4073802476 ps
CPU time 317.89 seconds
Started Mar 24 03:28:05 PM PDT 24
Finished Mar 24 03:33:23 PM PDT 24
Peak memory 599552 kb
Host smart-ecf66d69-ddfb-4ffe-911f-7653d4772e7b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486619814 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.486619814
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.823420266
Short name T61
Test name
Test status
Simulation time 5480967818 ps
CPU time 364.62 seconds
Started Mar 24 03:27:44 PM PDT 24
Finished Mar 24 03:33:49 PM PDT 24
Peak memory 600928 kb
Host smart-10570603-210f-48d1-bc76-d15f16b8004c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823420266 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.823420266
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.218142410
Short name T314
Test name
Test status
Simulation time 9266387944 ps
CPU time 1269.63 seconds
Started Mar 24 03:26:55 PM PDT 24
Finished Mar 24 03:48:04 PM PDT 24
Peak memory 600084 kb
Host smart-eb7a2149-7b67-4f56-be3a-080c749c6bfd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218142410 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.218142410
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1315692482
Short name T780
Test name
Test status
Simulation time 5213986136 ps
CPU time 512.31 seconds
Started Mar 24 03:33:50 PM PDT 24
Finished Mar 24 03:42:22 PM PDT 24
Peak memory 600860 kb
Host smart-0b8bdb95-d37c-43f7-9864-44601f7620f4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315692482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl
eep_sram_ret_contents_no_scramble.1315692482
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3695329774
Short name T797
Test name
Test status
Simulation time 8712350816 ps
CPU time 707.29 seconds
Started Mar 24 03:33:58 PM PDT 24
Finished Mar 24 03:45:45 PM PDT 24
Peak memory 600432 kb
Host smart-eefdfb8e-c82e-4e87-ac22-fd4c2e8a18af
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695329774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.3695329774
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1910770945
Short name T796
Test name
Test status
Simulation time 6969948567 ps
CPU time 771.99 seconds
Started Mar 24 03:28:12 PM PDT 24
Finished Mar 24 03:41:04 PM PDT 24
Peak memory 616348 kb
Host smart-6a31b8ec-e09a-46e0-b92a-55ad87684c2e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910770945 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1910770945
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1551994264
Short name T87
Test name
Test status
Simulation time 4947363001 ps
CPU time 512.88 seconds
Started Mar 24 03:27:47 PM PDT 24
Finished Mar 24 03:36:21 PM PDT 24
Peak memory 616740 kb
Host smart-3c3998d9-ea7e-4512-8467-e48bc2764bab
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551994264 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1551994264
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4267675045
Short name T905
Test name
Test status
Simulation time 5275885116 ps
CPU time 842.85 seconds
Started Mar 24 03:34:46 PM PDT 24
Finished Mar 24 03:48:50 PM PDT 24
Peak memory 600288 kb
Host smart-05c63780-20c9-474f-a870-8f803a46efd1
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267675045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.4267675045
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4082630730
Short name T874
Test name
Test status
Simulation time 3213760800 ps
CPU time 281.27 seconds
Started Mar 24 03:38:46 PM PDT 24
Finished Mar 24 03:43:27 PM PDT 24
Peak memory 599892 kb
Host smart-6a232f9d-977c-4d6d-aea7-8bebca183163
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082630730 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.4082630730
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.377903164
Short name T20
Test name
Test status
Simulation time 20872961661 ps
CPU time 3433.55 seconds
Started Mar 24 03:31:00 PM PDT 24
Finished Mar 24 04:28:15 PM PDT 24
Peak memory 600228 kb
Host smart-3b0576cb-7069-4edb-8599-0ff2b73fa264
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377903164 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.377903164
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3022470669
Short name T887
Test name
Test status
Simulation time 4254407048 ps
CPU time 624.5 seconds
Started Mar 24 03:30:23 PM PDT 24
Finished Mar 24 03:40:50 PM PDT 24
Peak memory 603868 kb
Host smart-afc56f4c-98af-456b-b23f-f4dbfcb51023
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022470669 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3022470669
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2163501826
Short name T762
Test name
Test status
Simulation time 2749388735 ps
CPU time 260.06 seconds
Started Mar 24 03:31:23 PM PDT 24
Finished Mar 24 03:35:44 PM PDT 24
Peak memory 603148 kb
Host smart-44b4c588-5f0d-433d-af8b-c79dd67f1cfb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163501826 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2163501826
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2574948310
Short name T18
Test name
Test status
Simulation time 23574458920 ps
CPU time 1643.65 seconds
Started Mar 24 03:30:54 PM PDT 24
Finished Mar 24 03:58:18 PM PDT 24
Peak memory 604320 kb
Host smart-746e10da-41e2-49ca-940e-fdb7c3e84937
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25749483
10 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2574948310
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985837689
Short name T247
Test name
Test status
Simulation time 5772980226 ps
CPU time 350.87 seconds
Started Mar 24 03:31:33 PM PDT 24
Finished Mar 24 03:37:24 PM PDT 24
Peak memory 600084 kb
Host smart-ca26c99d-5164-46ac-956b-f80c5ba7dfec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985837689 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985837689
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1436826647
Short name T632
Test name
Test status
Simulation time 14064665407 ps
CPU time 2353.35 seconds
Started Mar 24 03:28:00 PM PDT 24
Finished Mar 24 04:07:14 PM PDT 24
Peak memory 607276 kb
Host smart-8cb5fdda-9b01-4eac-b118-ad72d3ccf2b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1436826647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1436826647
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.3072167418
Short name T557
Test name
Test status
Simulation time 3585631672 ps
CPU time 307.62 seconds
Started Mar 24 03:38:53 PM PDT 24
Finished Mar 24 03:44:01 PM PDT 24
Peak memory 599740 kb
Host smart-1b11ffca-0990-4294-90f0-36833ebdabd3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072167418 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_uart_smoketest.3072167418
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2469762814
Short name T617
Test name
Test status
Simulation time 8925968868 ps
CPU time 1790.68 seconds
Started Mar 24 03:42:43 PM PDT 24
Finished Mar 24 04:12:34 PM PDT 24
Peak memory 599688 kb
Host smart-fecd3a17-c8a1-4976-87c7-1b5faad06c25
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa
ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2469762814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_smoketest_signed.2469762814
Directory /workspace/1.chip_sw_uart_smoketest_signed/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.33866871
Short name T570
Test name
Test status
Simulation time 5530089805 ps
CPU time 989.7 seconds
Started Mar 24 03:27:52 PM PDT 24
Finished Mar 24 03:44:23 PM PDT 24
Peak memory 608136 kb
Host smart-1ea57dd1-30db-48db-9015-fe3bd1b96de2
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866871 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.33866871
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3832717167
Short name T910
Test name
Test status
Simulation time 5624649359 ps
CPU time 981.03 seconds
Started Mar 24 03:27:57 PM PDT 24
Finished Mar 24 03:44:19 PM PDT 24
Peak memory 608108 kb
Host smart-878af13c-61f4-4d7c-a5b3-1a31f1bf3d9c
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832717167 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3832717167
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2572520840
Short name T343
Test name
Test status
Simulation time 5506986321 ps
CPU time 874.14 seconds
Started Mar 24 03:27:12 PM PDT 24
Finished Mar 24 03:41:46 PM PDT 24
Peak memory 607148 kb
Host smart-14de6e5d-5b21-4f4f-aeb8-4c45f5274eab
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572520840 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2572520840
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_prod.1910715707
Short name T716
Test name
Test status
Simulation time 5569172342 ps
CPU time 646.81 seconds
Started Mar 24 03:36:03 PM PDT 24
Finished Mar 24 03:46:51 PM PDT 24
Peak memory 609760 kb
Host smart-59c2d195-2569-4b42-8028-3c7d1214adf3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1910715707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1910715707
Directory /workspace/1.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/1.chip_tap_straps_rma.1568366092
Short name T904
Test name
Test status
Simulation time 3397425122 ps
CPU time 164.3 seconds
Started Mar 24 03:35:38 PM PDT 24
Finished Mar 24 03:38:23 PM PDT 24
Peak memory 618384 kb
Host smart-d8247053-7e70-474f-b477-76404f4bb751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568366092 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1568366092
Directory /workspace/1.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.2318514127
Short name T848
Test name
Test status
Simulation time 6165652980 ps
CPU time 542.07 seconds
Started Mar 24 03:36:34 PM PDT 24
Finished Mar 24 03:45:36 PM PDT 24
Peak memory 610100 kb
Host smart-3e10e1cd-b3c4-491c-811b-616ceaf9b3ce
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318514127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2318514127
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.3613755167
Short name T817
Test name
Test status
Simulation time 9350989254 ps
CPU time 1910.81 seconds
Started Mar 24 03:45:42 PM PDT 24
Finished Mar 24 04:17:33 PM PDT 24
Peak memory 600228 kb
Host smart-82b7530f-4ca9-4eec-89f6-fe54e18d7de7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613755167 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.rom_e2e_asm_init_dev.3613755167
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.638150266
Short name T544
Test name
Test status
Simulation time 9043181596 ps
CPU time 1822.91 seconds
Started Mar 24 03:42:34 PM PDT 24
Finished Mar 24 04:12:58 PM PDT 24
Peak memory 600188 kb
Host smart-5f0e9fe0-b97b-483b-a756-2a044ab602e2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638150266 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.rom_e2e_asm_init_prod.638150266
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3900205277
Short name T590
Test name
Test status
Simulation time 9192006851 ps
CPU time 1958.11 seconds
Started Mar 24 03:41:00 PM PDT 24
Finished Mar 24 04:13:39 PM PDT 24
Peak memory 600240 kb
Host smart-109df527-9e43-43f5-a5a8-785a775449ec
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900205277 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rom_e2e_asm_init_prod_end.3900205277
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.3035569782
Short name T881
Test name
Test status
Simulation time 8989744820 ps
CPU time 1913.22 seconds
Started Mar 24 03:42:12 PM PDT 24
Finished Mar 24 04:14:06 PM PDT 24
Peak memory 600248 kb
Host smart-997f5cf9-20a5-417b-99e2-82a583f4dbe9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035569782 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.rom_e2e_asm_init_rma.3035569782
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1723411496
Short name T280
Test name
Test status
Simulation time 7153038704 ps
CPU time 1504.75 seconds
Started Mar 24 03:42:19 PM PDT 24
Finished Mar 24 04:07:25 PM PDT 24
Peak memory 600280 kb
Host smart-a781d186-e1c6-4c3b-b1dd-bf575daa6219
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_
flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723411496 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1723411496
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2731259479
Short name T786
Test name
Test status
Simulation time 9357108139 ps
CPU time 2076.09 seconds
Started Mar 24 03:43:45 PM PDT 24
Finished Mar 24 04:18:21 PM PDT 24
Peak memory 600160 kb
Host smart-f144840d-8156-4b1e-b13e-95b6c69bbda5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_
with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2731259479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.2731259479
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.2504650530
Short name T882
Test name
Test status
Simulation time 9347859456 ps
CPU time 2067.18 seconds
Started Mar 24 03:40:12 PM PDT 24
Finished Mar 24 04:14:40 PM PDT 24
Peak memory 600008 kb
Host smart-16f47db9-431a-4071-89c3-d79916dbe1fd
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0
,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2504650530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2504650530
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.1643878735
Short name T638
Test name
Test status
Simulation time 10850266060 ps
CPU time 2189.6 seconds
Started Mar 24 03:40:28 PM PDT 24
Finished Mar 24 04:16:58 PM PDT 24
Peak memory 600048 kb
Host smart-9e28308e-d1f8-44ea-81da-ba1b7d60569d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1643878735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1643878735
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.3274345572
Short name T304
Test name
Test status
Simulation time 4123169374 ps
CPU time 546.43 seconds
Started Mar 24 03:39:07 PM PDT 24
Finished Mar 24 03:48:14 PM PDT 24
Peak memory 599948 kb
Host smart-85b63a72-ee86-4121-9cdf-7e9b92438416
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274345572 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.3274345572
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.584397233
Short name T669
Test name
Test status
Simulation time 14419512720 ps
CPU time 2152.73 seconds
Started Mar 24 03:39:10 PM PDT 24
Finished Mar 24 04:15:03 PM PDT 24
Peak memory 607288 kb
Host smart-6207e510-743a-4293-a370-07128c0bee80
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=584397233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.584397233
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.2042180678
Short name T189
Test name
Test status
Simulation time 1907755849 ps
CPU time 113.85 seconds
Started Mar 24 03:39:58 PM PDT 24
Finished Mar 24 03:41:52 PM PDT 24
Peak memory 606560 kb
Host smart-6848b960-1eeb-43ea-bc31-bed99714ec22
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042180678 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2042180678
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1797142892
Short name T195
Test name
Test status
Simulation time 8496510809 ps
CPU time 777.73 seconds
Started Mar 24 03:50:50 PM PDT 24
Finished Mar 24 04:03:49 PM PDT 24
Peak memory 612632 kb
Host smart-999b5b41-b566-4fc1-a7e0-8212b8b56a2e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797142892 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1797142892
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1992775563
Short name T705
Test name
Test status
Simulation time 4874310068 ps
CPU time 745.47 seconds
Started Mar 24 03:48:42 PM PDT 24
Finished Mar 24 04:01:08 PM PDT 24
Peak memory 607236 kb
Host smart-28b5a852-7681-43b2-bda2-9e6bd90932f4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1992775563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1992775563
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1857173670
Short name T674
Test name
Test status
Simulation time 5423637456 ps
CPU time 484.76 seconds
Started Mar 24 03:50:39 PM PDT 24
Finished Mar 24 03:58:44 PM PDT 24
Peak memory 612588 kb
Host smart-860f77ad-893f-407c-a6bb-41ce57fa0221
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857173670 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1857173670
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.775485675
Short name T579
Test name
Test status
Simulation time 13894814872 ps
CPU time 1783.2 seconds
Started Mar 24 03:50:38 PM PDT 24
Finished Mar 24 04:20:22 PM PDT 24
Peak memory 608184 kb
Host smart-39b88a51-7389-4749-96d4-586c64a4ff58
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=775485675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.775485675
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.372867388
Short name T541
Test name
Test status
Simulation time 11158136692 ps
CPU time 781.32 seconds
Started Mar 24 03:49:53 PM PDT 24
Finished Mar 24 04:02:55 PM PDT 24
Peak memory 612336 kb
Host smart-574a5fbb-3f3a-40b7-86a0-0d5869f555fa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372867388 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.372867388
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.3458625853
Short name T435
Test name
Test status
Simulation time 6044062038 ps
CPU time 523.93 seconds
Started Mar 24 03:50:42 PM PDT 24
Finished Mar 24 03:59:27 PM PDT 24
Peak memory 635316 kb
Host smart-df8768f2-a093-4635-a089-b2ba1d6ba897
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3458625853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3458625853
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3077425471
Short name T560
Test name
Test status
Simulation time 10268303285 ps
CPU time 586.36 seconds
Started Mar 24 03:49:56 PM PDT 24
Finished Mar 24 03:59:44 PM PDT 24
Peak memory 612516 kb
Host smart-bfd7896c-3c77-4013-89a9-f44edf51dc07
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077425471 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3077425471
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.279401758
Short name T352
Test name
Test status
Simulation time 5220104739 ps
CPU time 797.7 seconds
Started Mar 24 03:50:50 PM PDT 24
Finished Mar 24 04:04:08 PM PDT 24
Peak memory 608252 kb
Host smart-9a86bb0b-42f2-418e-baee-d7bd68c79d69
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=279401758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.279401758
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.567520198
Short name T575
Test name
Test status
Simulation time 11730703875 ps
CPU time 1118.82 seconds
Started Mar 24 03:50:41 PM PDT 24
Finished Mar 24 04:09:20 PM PDT 24
Peak memory 611520 kb
Host smart-54a10bf2-d224-480f-acdb-49c2549dd68d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567520198 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.567520198
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2377648349
Short name T14
Test name
Test status
Simulation time 3988311398 ps
CPU time 649.81 seconds
Started Mar 24 03:50:04 PM PDT 24
Finished Mar 24 04:00:54 PM PDT 24
Peak memory 607084 kb
Host smart-89a8a041-362e-46a1-93b0-c3048a6c7bc4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2377648349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2377648349
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481077120
Short name T227
Test name
Test status
Simulation time 4337480652 ps
CPU time 430.51 seconds
Started Mar 24 03:51:48 PM PDT 24
Finished Mar 24 03:58:59 PM PDT 24
Peak memory 636552 kb
Host smart-63a0d668-9a79-460b-b363-afc8b9ebae3e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481077120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1481077120
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.4043475053
Short name T462
Test name
Test status
Simulation time 4727300536 ps
CPU time 577.31 seconds
Started Mar 24 03:50:24 PM PDT 24
Finished Mar 24 04:00:02 PM PDT 24
Peak memory 636564 kb
Host smart-746cb2f5-19a4-4cbe-b492-f81c05a7025f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4043475053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.4043475053
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2077519076
Short name T368
Test name
Test status
Simulation time 5463110935 ps
CPU time 749.82 seconds
Started Mar 24 03:51:14 PM PDT 24
Finished Mar 24 04:03:44 PM PDT 24
Peak memory 608168 kb
Host smart-af66f02d-032b-411e-a243-29a2a7201c21
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2077519076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2077519076
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4055850210
Short name T404
Test name
Test status
Simulation time 4727587960 ps
CPU time 546.31 seconds
Started Mar 24 03:49:44 PM PDT 24
Finished Mar 24 03:58:50 PM PDT 24
Peak memory 607244 kb
Host smart-49e26399-427b-4c65-954f-5308c48a1a72
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4055850210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.4055850210
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128689384
Short name T481
Test name
Test status
Simulation time 3301124580 ps
CPU time 419.02 seconds
Started Mar 24 03:52:06 PM PDT 24
Finished Mar 24 03:59:05 PM PDT 24
Peak memory 636360 kb
Host smart-46ac118e-a1a7-480a-8677-742bf49fe0b4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128689384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2128689384
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.571724865
Short name T831
Test name
Test status
Simulation time 12984113988 ps
CPU time 1870.68 seconds
Started Mar 24 03:50:18 PM PDT 24
Finished Mar 24 04:21:29 PM PDT 24
Peak memory 607244 kb
Host smart-2d8bec51-b92c-45c1-96ba-af961366705e
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=571724865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.571724865
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3430249611
Short name T341
Test name
Test status
Simulation time 14198211370 ps
CPU time 1983.68 seconds
Started Mar 24 03:51:49 PM PDT 24
Finished Mar 24 04:24:53 PM PDT 24
Peak memory 608184 kb
Host smart-1c26c035-d6eb-40e0-b653-bfe5f97c4cab
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3430249611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3430249611
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.927801638
Short name T823
Test name
Test status
Simulation time 22678806662 ps
CPU time 2963.29 seconds
Started Mar 24 03:51:23 PM PDT 24
Finished Mar 24 04:40:47 PM PDT 24
Peak memory 608184 kb
Host smart-7d826655-8146-4c64-b907-838c0c308959
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=927801638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.927801638
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.2371541403
Short name T346
Test name
Test status
Simulation time 13403211580 ps
CPU time 1691.84 seconds
Started Mar 24 03:37:39 PM PDT 24
Finished Mar 24 04:05:51 PM PDT 24
Peak memory 593032 kb
Host smart-01585dec-9c71-4fca-abd4-46d705f94553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371541403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2
371541403
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1138473572
Short name T57
Test name
Test status
Simulation time 4945848506 ps
CPU time 494.35 seconds
Started Mar 24 03:45:37 PM PDT 24
Finished Mar 24 03:53:52 PM PDT 24
Peak memory 607116 kb
Host smart-1ccac8ce-7e59-44e8-a675-edc396eafd7a
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1
138473572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1138473572
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.3841038862
Short name T799
Test name
Test status
Simulation time 3325218864 ps
CPU time 296.25 seconds
Started Mar 24 03:39:14 PM PDT 24
Finished Mar 24 03:44:11 PM PDT 24
Peak memory 599924 kb
Host smart-d7245201-27d4-4799-9deb-d1d343fcbbdd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3841038862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3841038862
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1366402648
Short name T374
Test name
Test status
Simulation time 18732765778 ps
CPU time 718.63 seconds
Started Mar 24 03:44:43 PM PDT 24
Finished Mar 24 03:56:43 PM PDT 24
Peak memory 607252 kb
Host smart-5a3b746b-c052-4df8-9227-ad72ea685ef2
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1366402648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1366402648
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.3135776069
Short name T535
Test name
Test status
Simulation time 2873635720 ps
CPU time 204.99 seconds
Started Mar 24 03:44:44 PM PDT 24
Finished Mar 24 03:48:09 PM PDT 24
Peak memory 599904 kb
Host smart-124684f7-cc87-42fb-aec0-661dd2f88adf
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135776069 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3135776069
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1250096535
Short name T596
Test name
Test status
Simulation time 2564681309 ps
CPU time 241.44 seconds
Started Mar 24 03:43:01 PM PDT 24
Finished Mar 24 03:47:03 PM PDT 24
Peak memory 599908 kb
Host smart-1768712f-3fa5-43ca-b656-b0e5b1d58bd2
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250
096535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1250096535
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.857722692
Short name T942
Test name
Test status
Simulation time 2692115256 ps
CPU time 305.45 seconds
Started Mar 24 03:48:51 PM PDT 24
Finished Mar 24 03:53:56 PM PDT 24
Peak memory 599992 kb
Host smart-7e05fa9a-c8e7-4538-9ba6-b18d75f69646
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=857722692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.857722692
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.46850416
Short name T641
Test name
Test status
Simulation time 2884309122 ps
CPU time 322.01 seconds
Started Mar 24 03:47:15 PM PDT 24
Finished Mar 24 03:52:38 PM PDT 24
Peak memory 600056 kb
Host smart-71ead098-2ec3-4600-9f1b-3a1bfd421f06
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46850416 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.46850416
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.2479803441
Short name T554
Test name
Test status
Simulation time 2689962680 ps
CPU time 211.79 seconds
Started Mar 24 03:41:29 PM PDT 24
Finished Mar 24 03:45:01 PM PDT 24
Peak memory 599816 kb
Host smart-4510716d-96f5-42ca-9016-80f29866ab5d
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479803441 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2479803441
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.2663038787
Short name T444
Test name
Test status
Simulation time 2092416947 ps
CPU time 269.15 seconds
Started Mar 24 03:43:22 PM PDT 24
Finished Mar 24 03:47:51 PM PDT 24
Peak memory 599568 kb
Host smart-83aaa449-d12a-4911-b360-6f6e12e9eaa9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663038787 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2663038787
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.2325748464
Short name T531
Test name
Test status
Simulation time 3131650936 ps
CPU time 316.74 seconds
Started Mar 24 03:49:10 PM PDT 24
Finished Mar 24 03:54:27 PM PDT 24
Peak memory 599836 kb
Host smart-5a7bc93d-0c1a-4993-b60b-17d1f7add31b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325748464 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.2325748464
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.580024821
Short name T867
Test name
Test status
Simulation time 3060598235 ps
CPU time 315.2 seconds
Started Mar 24 03:42:20 PM PDT 24
Finished Mar 24 03:47:36 PM PDT 24
Peak memory 599300 kb
Host smart-2b4f8877-8f50-44d4-ab8f-c3b391cdc544
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=580024821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.580024821
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2420247237
Short name T322
Test name
Test status
Simulation time 3955080064 ps
CPU time 502.13 seconds
Started Mar 24 03:43:03 PM PDT 24
Finished Mar 24 03:51:25 PM PDT 24
Peak memory 607060 kb
Host smart-d7467455-701c-4d46-9408-1dbff3a53ae4
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2420247237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2420247237
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3270121253
Short name T173
Test name
Test status
Simulation time 6709558960 ps
CPU time 1086.83 seconds
Started Mar 24 03:44:24 PM PDT 24
Finished Mar 24 04:02:31 PM PDT 24
Peak memory 599996 kb
Host smart-6f68006f-9f1c-447e-bfe1-887973be4845
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3270121253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3270121253
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1372352142
Short name T743
Test name
Test status
Simulation time 7652623208 ps
CPU time 1476.67 seconds
Started Mar 24 03:44:19 PM PDT 24
Finished Mar 24 04:08:56 PM PDT 24
Peak memory 599360 kb
Host smart-a944491b-882a-47d5-b314-aefc60984fcb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1372352142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg
le.1372352142
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4228390953
Short name T935
Test name
Test status
Simulation time 3140118920 ps
CPU time 409.41 seconds
Started Mar 24 03:43:24 PM PDT 24
Finished Mar 24 03:50:14 PM PDT 24
Peak memory 636440 kb
Host smart-b520b66b-dbf1-4c0a-bfb6-f03f8df90b20
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228390953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4228390953
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3886044855
Short name T165
Test name
Test status
Simulation time 12765073556 ps
CPU time 1234.2 seconds
Started Mar 24 03:46:22 PM PDT 24
Finished Mar 24 04:06:56 PM PDT 24
Peak memory 601092 kb
Host smart-6c888dff-44ff-4487-a94b-90b016717b12
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886044855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.chip_sw_alert_handler_lpg_sleep_mode_pings.3886044855
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2671925650
Short name T684
Test name
Test status
Simulation time 5056415736 ps
CPU time 553.29 seconds
Started Mar 24 03:44:03 PM PDT 24
Finished Mar 24 03:53:17 PM PDT 24
Peak memory 599772 kb
Host smart-af5fae22-4ba4-43d3-88c4-a7e371ae8ec6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2671925650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2671925650
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2945949364
Short name T184
Test name
Test status
Simulation time 254485545360 ps
CPU time 11053.3 seconds
Started Mar 24 03:45:59 PM PDT 24
Finished Mar 24 06:50:13 PM PDT 24
Peak memory 600144 kb
Host smart-ee315eb3-c693-453a-89fa-4d49ba3019e1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945949364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2945949364
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.2497663351
Short name T376
Test name
Test status
Simulation time 4185887180 ps
CPU time 469.03 seconds
Started Mar 24 03:44:39 PM PDT 24
Finished Mar 24 03:52:29 PM PDT 24
Peak memory 599912 kb
Host smart-f95ae676-6555-408c-b983-ae788074c96f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497663351 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2497663351
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3247762802
Short name T275
Test name
Test status
Simulation time 6541901448 ps
CPU time 433.03 seconds
Started Mar 24 03:40:42 PM PDT 24
Finished Mar 24 03:47:55 PM PDT 24
Peak memory 599940 kb
Host smart-6c6c846c-82a1-4b7c-8ed3-b402ef179bc0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3247762802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3247762802
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.778302898
Short name T67
Test name
Test status
Simulation time 3367190700 ps
CPU time 425.65 seconds
Started Mar 24 03:46:48 PM PDT 24
Finished Mar 24 03:53:54 PM PDT 24
Peak memory 599924 kb
Host smart-b66fa591-95d3-45e1-8109-908c618e993b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778302898 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_aon_timer_smoketest.778302898
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4153200898
Short name T664
Test name
Test status
Simulation time 9615810282 ps
CPU time 862.08 seconds
Started Mar 24 03:42:18 PM PDT 24
Finished Mar 24 03:56:41 PM PDT 24
Peak memory 599992 kb
Host smart-ce231d9c-3c20-468b-800a-d9b7dee71afb
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4153200898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.4153200898
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4255304900
Short name T676
Test name
Test status
Simulation time 4837668402 ps
CPU time 770.55 seconds
Started Mar 24 03:42:10 PM PDT 24
Finished Mar 24 03:55:01 PM PDT 24
Peak memory 600040 kb
Host smart-8dede150-9a4f-448f-ab12-ffadf0aca6a0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4255304900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.4255304900
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3205975386
Short name T759
Test name
Test status
Simulation time 6955031400 ps
CPU time 953.92 seconds
Started Mar 24 03:44:32 PM PDT 24
Finished Mar 24 04:00:27 PM PDT 24
Peak memory 606392 kb
Host smart-34be3848-2358-4c4f-933d-36820ad48400
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205975386 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3205975386
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.852093010
Short name T595
Test name
Test status
Simulation time 13225708711 ps
CPU time 997.54 seconds
Started Mar 24 03:45:57 PM PDT 24
Finished Mar 24 04:02:35 PM PDT 24
Peak memory 611508 kb
Host smart-a0ac2b46-cea6-4425-9e95-5498cbdc2e53
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=852093010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.852093010
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.705993336
Short name T930
Test name
Test status
Simulation time 4559259844 ps
CPU time 589.95 seconds
Started Mar 24 03:45:42 PM PDT 24
Finished Mar 24 03:55:32 PM PDT 24
Peak memory 603260 kb
Host smart-2af8e212-f350-4de0-8703-e2922bd6e18e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705993336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_dev.705993336
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.884877326
Short name T620
Test name
Test status
Simulation time 3928123184 ps
CPU time 628.47 seconds
Started Mar 24 03:44:44 PM PDT 24
Finished Mar 24 03:55:13 PM PDT 24
Peak memory 603848 kb
Host smart-0cc21f73-2d88-4cbc-9dbc-4b7be24d777a
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884877326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_rma.884877326
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4065321193
Short name T550
Test name
Test status
Simulation time 3955725416 ps
CPU time 854.49 seconds
Started Mar 24 03:44:11 PM PDT 24
Finished Mar 24 03:58:26 PM PDT 24
Peak memory 602832 kb
Host smart-5fbabe6c-3aa9-456a-b050-c8b47454f2ad
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065321193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4065321193
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2707333564
Short name T751
Test name
Test status
Simulation time 4888084980 ps
CPU time 740.82 seconds
Started Mar 24 03:45:02 PM PDT 24
Finished Mar 24 03:57:24 PM PDT 24
Peak memory 603968 kb
Host smart-9767572b-7a78-4c67-8088-7f62099b60bd
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707333564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.2707333564
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4286951536
Short name T707
Test name
Test status
Simulation time 4367006316 ps
CPU time 677.6 seconds
Started Mar 24 03:45:23 PM PDT 24
Finished Mar 24 03:56:40 PM PDT 24
Peak memory 603960 kb
Host smart-2240869a-0db6-45d5-8542-5af92e0ec8ea
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286951536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.4286951536
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2609685960
Short name T673
Test name
Test status
Simulation time 4063639100 ps
CPU time 602.4 seconds
Started Mar 24 03:45:40 PM PDT 24
Finished Mar 24 03:55:43 PM PDT 24
Peak memory 602776 kb
Host smart-331b6498-5ae2-4aa2-b3fc-48fed34e539e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609685960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2609685960
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2225227413
Short name T830
Test name
Test status
Simulation time 2464793769 ps
CPU time 282.63 seconds
Started Mar 24 03:46:45 PM PDT 24
Finished Mar 24 03:51:27 PM PDT 24
Peak memory 599924 kb
Host smart-8d4ef8db-180a-4a3f-8448-040a0685b032
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225227413 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_clkmgr_jitter.2225227413
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.714064206
Short name T807
Test name
Test status
Simulation time 3561533620 ps
CPU time 419.51 seconds
Started Mar 24 03:46:09 PM PDT 24
Finished Mar 24 03:53:09 PM PDT 24
Peak memory 599936 kb
Host smart-27075b23-1e58-4b09-a6e1-1503fc774117
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714064206 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.714064206
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3630245063
Short name T603
Test name
Test status
Simulation time 2886183161 ps
CPU time 246.49 seconds
Started Mar 24 03:45:02 PM PDT 24
Finished Mar 24 03:49:09 PM PDT 24
Peak memory 599104 kb
Host smart-25acf7d2-4485-43dc-8680-48c9f2ae1fbf
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630245063 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3630245063
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2516668734
Short name T756
Test name
Test status
Simulation time 4914600108 ps
CPU time 433.43 seconds
Started Mar 24 03:44:28 PM PDT 24
Finished Mar 24 03:51:42 PM PDT 24
Peak memory 599928 kb
Host smart-f9494776-a168-42de-9d44-5cdee83aa65b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516668734 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2516668734
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2380319342
Short name T103
Test name
Test status
Simulation time 4384169406 ps
CPU time 423.65 seconds
Started Mar 24 03:43:45 PM PDT 24
Finished Mar 24 03:50:49 PM PDT 24
Peak memory 599988 kb
Host smart-ddf4f01e-6622-4d34-8b7c-6f96857fa792
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380319342 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2380319342
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4193822789
Short name T908
Test name
Test status
Simulation time 4415927910 ps
CPU time 485.32 seconds
Started Mar 24 03:44:12 PM PDT 24
Finished Mar 24 03:52:18 PM PDT 24
Peak memory 600000 kb
Host smart-555680d8-3d12-49cb-acd3-5b13de44a731
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193822789 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.4193822789
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3928597060
Short name T524
Test name
Test status
Simulation time 5288949280 ps
CPU time 657.54 seconds
Started Mar 24 03:45:27 PM PDT 24
Finished Mar 24 03:56:25 PM PDT 24
Peak memory 599988 kb
Host smart-8465dcf6-b5eb-4265-8085-54c7a4e764ee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928597060 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3928597060
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.908721659
Short name T296
Test name
Test status
Simulation time 10247079736 ps
CPU time 1540.64 seconds
Started Mar 24 03:44:33 PM PDT 24
Finished Mar 24 04:10:14 PM PDT 24
Peak memory 600912 kb
Host smart-2401919d-2f90-4b18-8bf7-ac3a432e11e7
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908721659
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.908721659
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1210495281
Short name T692
Test name
Test status
Simulation time 3259277860 ps
CPU time 306.36 seconds
Started Mar 24 03:44:12 PM PDT 24
Finished Mar 24 03:49:18 PM PDT 24
Peak memory 599948 kb
Host smart-d2e8937a-ffd4-4085-a213-4c655dc3f97d
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210495281 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1210495281
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1566984731
Short name T566
Test name
Test status
Simulation time 4496562804 ps
CPU time 664.88 seconds
Started Mar 24 03:46:27 PM PDT 24
Finished Mar 24 03:57:32 PM PDT 24
Peak memory 599416 kb
Host smart-0948044b-9b2d-43d8-82af-9166beb8dbdf
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566984731 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1566984731
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3051979734
Short name T613
Test name
Test status
Simulation time 2438876760 ps
CPU time 316.85 seconds
Started Mar 24 03:47:52 PM PDT 24
Finished Mar 24 03:53:10 PM PDT 24
Peak memory 599944 kb
Host smart-8962513d-949a-4c48-b810-f1b0d8d87e00
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051979734 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_clkmgr_smoketest.3051979734
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3289728323
Short name T281
Test name
Test status
Simulation time 15333845808 ps
CPU time 3901.31 seconds
Started Mar 24 03:43:01 PM PDT 24
Finished Mar 24 04:48:04 PM PDT 24
Peak memory 600104 kb
Host smart-4d9c3dd5-29ba-49db-8846-a275323ab3ff
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289728323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3289728323
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.326634083
Short name T149
Test name
Test status
Simulation time 16500787459 ps
CPU time 2724.15 seconds
Started Mar 24 03:47:34 PM PDT 24
Finished Mar 24 04:32:58 PM PDT 24
Peak memory 600024 kb
Host smart-0743cb54-e9b0-4239-8245-d84e51a407b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326634083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST
_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_
csrng_edn_concurrency_reduced_freq.326634083
Directory /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3122132792
Short name T592
Test name
Test status
Simulation time 4055406032 ps
CPU time 483.58 seconds
Started Mar 24 03:43:15 PM PDT 24
Finished Mar 24 03:51:19 PM PDT 24
Peak memory 599968 kb
Host smart-81040efc-c7f9-4177-af0f-92b94b7eb147
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31221
32792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3122132792
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.741895657
Short name T665
Test name
Test status
Simulation time 2912142676 ps
CPU time 338.25 seconds
Started Mar 24 03:42:08 PM PDT 24
Finished Mar 24 03:47:47 PM PDT 24
Peak memory 599924 kb
Host smart-47a2f1a1-a16c-43f6-9313-160612478d68
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741895657 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.741895657
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.392867319
Short name T105
Test name
Test status
Simulation time 7447625720 ps
CPU time 407.06 seconds
Started Mar 24 03:40:57 PM PDT 24
Finished Mar 24 03:47:45 PM PDT 24
Peak memory 600432 kb
Host smart-fccf086f-c452-45b6-b51e-8295d878f8a1
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392867319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l
c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn
g_lc_hw_debug_en_test.392867319
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.47055518
Short name T523
Test name
Test status
Simulation time 2397655256 ps
CPU time 277.91 seconds
Started Mar 24 03:48:24 PM PDT 24
Finished Mar 24 03:53:02 PM PDT 24
Peak memory 599876 kb
Host smart-7e5678bb-5ff3-4aba-ab4c-d6b00be315c0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47055518 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_csrng_smoketest.47055518
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4182499227
Short name T252
Test name
Test status
Simulation time 6398706514 ps
CPU time 892.72 seconds
Started Mar 24 03:38:34 PM PDT 24
Finished Mar 24 03:53:27 PM PDT 24
Peak memory 600472 kb
Host smart-72554075-37df-411f-b2d9-dc1a79c2fcef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4182499227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.4182499227
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.1235791725
Short name T268
Test name
Test status
Simulation time 6656317170 ps
CPU time 1274.27 seconds
Started Mar 24 03:46:54 PM PDT 24
Finished Mar 24 04:08:09 PM PDT 24
Peak memory 600260 kb
Host smart-7332f488-7377-4951-958b-e8f239c227df
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235791725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
auto_mode.1235791725
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.3651242001
Short name T169
Test name
Test status
Simulation time 3435664040 ps
CPU time 494.59 seconds
Started Mar 24 03:43:09 PM PDT 24
Finished Mar 24 03:51:24 PM PDT 24
Peak memory 599232 kb
Host smart-2ddbcaa2-4e34-4e29-bda6-3dc57e5fb626
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651242001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
boot_mode.3651242001
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1642733142
Short name T387
Test name
Test status
Simulation time 5609646960 ps
CPU time 1153.91 seconds
Started Mar 24 03:43:53 PM PDT 24
Finished Mar 24 04:03:07 PM PDT 24
Peak memory 600116 kb
Host smart-71c88736-df74-4c71-a4b1-8fa2362f5b2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642733142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1642733142
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3547629901
Short name T816
Test name
Test status
Simulation time 4636151915 ps
CPU time 801.11 seconds
Started Mar 24 03:42:11 PM PDT 24
Finished Mar 24 03:55:32 PM PDT 24
Peak memory 600100 kb
Host smart-f74d831f-cd88-4b27-aca3-2c875581b155
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547629901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3547629901
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.3774053308
Short name T945
Test name
Test status
Simulation time 3677265178 ps
CPU time 679.21 seconds
Started Mar 24 03:41:49 PM PDT 24
Finished Mar 24 03:53:08 PM PDT 24
Peak memory 605328 kb
Host smart-d2e73275-c6af-4167-b5b1-edc917e5c316
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774053308 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_edn_kat.3774053308
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.2015246224
Short name T700
Test name
Test status
Simulation time 9318449616 ps
CPU time 1831.22 seconds
Started Mar 24 03:42:13 PM PDT 24
Finished Mar 24 04:12:44 PM PDT 24
Peak memory 599988 kb
Host smart-403cc7aa-04ed-45ec-a550-0ecc44602815
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015246224 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2015246224
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3793726865
Short name T764
Test name
Test status
Simulation time 2242996530 ps
CPU time 312.32 seconds
Started Mar 24 03:42:29 PM PDT 24
Finished Mar 24 03:47:41 PM PDT 24
Peak memory 599900 kb
Host smart-a2c60bb1-d7aa-46fe-842d-f020ea0f5a43
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37
93726865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3793726865
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4066125907
Short name T366
Test name
Test status
Simulation time 6248484312 ps
CPU time 1162.2 seconds
Started Mar 24 03:43:51 PM PDT 24
Finished Mar 24 04:03:14 PM PDT 24
Peak memory 600060 kb
Host smart-e0954590-b983-46be-9bf6-0df1aeac4759
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4066125907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4066125907
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1816484149
Short name T793
Test name
Test status
Simulation time 2712388716 ps
CPU time 291.53 seconds
Started Mar 24 03:43:38 PM PDT 24
Finished Mar 24 03:48:29 PM PDT 24
Peak memory 599912 kb
Host smart-4e956b86-18e9-40fc-8d60-a9c05b7b6936
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816484149
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1816484149
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1565139824
Short name T405
Test name
Test status
Simulation time 3396720728 ps
CPU time 466.49 seconds
Started Mar 24 03:47:20 PM PDT 24
Finished Mar 24 03:55:07 PM PDT 24
Peak memory 599916 kb
Host smart-701dfd8e-a677-4b80-87e5-7040ec3bf620
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1565139824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1565139824
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.3683177507
Short name T912
Test name
Test status
Simulation time 2174059078 ps
CPU time 252.84 seconds
Started Mar 24 03:39:52 PM PDT 24
Finished Mar 24 03:44:06 PM PDT 24
Peak memory 599924 kb
Host smart-9d670345-2cfc-452a-a99e-8fe058069868
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683177507 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_example_concurrency.3683177507
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.1453275741
Short name T614
Test name
Test status
Simulation time 2804985340 ps
CPU time 195.56 seconds
Started Mar 24 03:38:33 PM PDT 24
Finished Mar 24 03:41:49 PM PDT 24
Peak memory 599948 kb
Host smart-9f8d5906-77b7-4ed8-a197-172a542feb88
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453275741 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.1453275741
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.1915462038
Short name T924
Test name
Test status
Simulation time 3194430100 ps
CPU time 214.77 seconds
Started Mar 24 03:40:07 PM PDT 24
Finished Mar 24 03:43:41 PM PDT 24
Peak memory 599936 kb
Host smart-81e571a8-b8a1-4181-bd15-5a2b1a9669c7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915462038 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.1915462038
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.886621220
Short name T548
Test name
Test status
Simulation time 2665746888 ps
CPU time 128.89 seconds
Started Mar 24 03:38:23 PM PDT 24
Finished Mar 24 03:40:32 PM PDT 24
Peak memory 599508 kb
Host smart-cd0039f8-e3f0-4968-aac8-b0f14aceff3a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886621220 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_example_rom.886621220
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.352658161
Short name T51
Test name
Test status
Simulation time 57548737546 ps
CPU time 10256.2 seconds
Started Mar 24 03:39:22 PM PDT 24
Finished Mar 24 06:30:20 PM PDT 24
Peak memory 608336 kb
Host smart-2b1eb9ca-8051-49f3-985c-4882d047c505
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=352658161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.352658161
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.1982176204
Short name T726
Test name
Test status
Simulation time 4208988208 ps
CPU time 495.1 seconds
Started Mar 24 03:46:02 PM PDT 24
Finished Mar 24 03:54:18 PM PDT 24
Peak memory 601220 kb
Host smart-f1bad62d-674a-4bab-bbef-d40f75d15d7f
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=1982176204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1982176204
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2805007446
Short name T906
Test name
Test status
Simulation time 5208102402 ps
CPU time 1192.39 seconds
Started Mar 24 03:39:00 PM PDT 24
Finished Mar 24 03:58:53 PM PDT 24
Peak memory 599912 kb
Host smart-d4cf67f0-9816-4ad2-93db-28fa759c5757
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805007446 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_flash_ctrl_access.2805007446
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1437163315
Short name T615
Test name
Test status
Simulation time 6345577204 ps
CPU time 1172.75 seconds
Started Mar 24 03:42:38 PM PDT 24
Finished Mar 24 04:02:11 PM PDT 24
Peak memory 599952 kb
Host smart-01823042-14b2-4efd-a3e9-e42165f9d096
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437163315 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1437163315
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2830193798
Short name T556
Test name
Test status
Simulation time 7774598802 ps
CPU time 1072.14 seconds
Started Mar 24 03:46:40 PM PDT 24
Finished Mar 24 04:04:32 PM PDT 24
Peak memory 599976 kb
Host smart-1f3aac4c-d94a-499c-bdc4-3d98e90c865c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830193798 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2830193798
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4057455318
Short name T801
Test name
Test status
Simulation time 5757306218 ps
CPU time 1097.64 seconds
Started Mar 24 03:38:45 PM PDT 24
Finished Mar 24 03:57:03 PM PDT 24
Peak memory 599968 kb
Host smart-1fee7721-3276-4e70-8665-d3085bfe5a0f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057455318 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.4057455318
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1656243233
Short name T612
Test name
Test status
Simulation time 3716063928 ps
CPU time 341.19 seconds
Started Mar 24 03:39:44 PM PDT 24
Finished Mar 24 03:45:26 PM PDT 24
Peak memory 599888 kb
Host smart-76fea0ff-7c26-4ac6-8c2b-448238d816b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656243233 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1656243233
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3901795686
Short name T558
Test name
Test status
Simulation time 5176579020 ps
CPU time 1020.09 seconds
Started Mar 24 03:46:10 PM PDT 24
Finished Mar 24 04:03:10 PM PDT 24
Peak memory 600008 kb
Host smart-8b03fcf0-0208-4793-890c-67ccdf67113e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901795686 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3901795686
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3602407122
Short name T363
Test name
Test status
Simulation time 3773471176 ps
CPU time 625.59 seconds
Started Mar 24 03:38:42 PM PDT 24
Finished Mar 24 03:49:07 PM PDT 24
Peak memory 599848 kb
Host smart-00f69eb4-47a6-49f2-8414-a26e441f7ed7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602407122
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3602407122
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.491002891
Short name T372
Test name
Test status
Simulation time 4591917001 ps
CPU time 806.88 seconds
Started Mar 24 03:41:56 PM PDT 24
Finished Mar 24 03:55:24 PM PDT 24
Peak memory 600064 kb
Host smart-ff60e960-57ce-45d0-b47a-577df0c4aa5e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=491002891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.491002891
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4197081922
Short name T659
Test name
Test status
Simulation time 4789772922 ps
CPU time 861.5 seconds
Started Mar 24 03:45:54 PM PDT 24
Finished Mar 24 04:00:17 PM PDT 24
Peak memory 599968 kb
Host smart-86b5331b-d011-4d9f-8be9-d7f89db027f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4197081922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4197081922
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.3547893438
Short name T222
Test name
Test status
Simulation time 16984609350 ps
CPU time 1917.97 seconds
Started Mar 24 03:39:29 PM PDT 24
Finished Mar 24 04:11:28 PM PDT 24
Peak memory 603080 kb
Host smart-8addf77b-a745-4449-a03f-ccc208846555
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547893438 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3547893438
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3325689402
Short name T652
Test name
Test status
Simulation time 23677937291 ps
CPU time 1741.13 seconds
Started Mar 24 03:45:31 PM PDT 24
Finished Mar 24 04:14:32 PM PDT 24
Peak memory 604072 kb
Host smart-1358042e-4007-49c6-b450-7edff481c1b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3325689402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3325689402
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2680897538
Short name T75
Test name
Test status
Simulation time 2293744240 ps
CPU time 278.14 seconds
Started Mar 24 03:52:05 PM PDT 24
Finished Mar 24 03:56:43 PM PDT 24
Peak memory 599892 kb
Host smart-86ff0652-df11-4dfc-a516-65fb59068157
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2680897538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2680897538
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.2202874896
Short name T250
Test name
Test status
Simulation time 2703238531 ps
CPU time 239.31 seconds
Started Mar 24 03:47:47 PM PDT 24
Finished Mar 24 03:51:47 PM PDT 24
Peak memory 601004 kb
Host smart-d1f8416e-fbf7-48a7-b9bf-3a0000dde8b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202874896 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_gpio_smoketest.2202874896
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.4248394208
Short name T93
Test name
Test status
Simulation time 2680030274 ps
CPU time 309.19 seconds
Started Mar 24 03:43:04 PM PDT 24
Finished Mar 24 03:48:13 PM PDT 24
Peak memory 599944 kb
Host smart-e3841257-bfb1-40e6-a924-c6b0893b3dec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248394208 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.4248394208
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.719134503
Short name T606
Test name
Test status
Simulation time 3078691400 ps
CPU time 345.86 seconds
Started Mar 24 03:43:52 PM PDT 24
Finished Mar 24 03:49:38 PM PDT 24
Peak memory 599932 kb
Host smart-49bb0efd-e925-42d8-bf62-39e8b784c7a1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719134503 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_hmac_enc_idle.719134503
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2844239393
Short name T95
Test name
Test status
Simulation time 2918998347 ps
CPU time 301.99 seconds
Started Mar 24 03:43:03 PM PDT 24
Finished Mar 24 03:48:06 PM PDT 24
Peak memory 599948 kb
Host smart-9bdcba31-9d8f-4f89-a551-e7d9e639d554
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844239393 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2844239393
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1858107758
Short name T589
Test name
Test status
Simulation time 3635635400 ps
CPU time 287.21 seconds
Started Mar 24 03:48:56 PM PDT 24
Finished Mar 24 03:53:43 PM PDT 24
Peak memory 599936 kb
Host smart-ecc9a944-eff1-40e2-b9ab-4801f885ea8d
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858107758 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1858107758
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.598430188
Short name T581
Test name
Test status
Simulation time 2753449390 ps
CPU time 391.67 seconds
Started Mar 24 03:47:22 PM PDT 24
Finished Mar 24 03:53:53 PM PDT 24
Peak memory 599940 kb
Host smart-01e9f221-cc5f-4f39-a63a-47a0eef7ff04
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598430188 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_smoketest.598430188
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2401967757
Short name T210
Test name
Test status
Simulation time 3781586728 ps
CPU time 489.14 seconds
Started Mar 24 03:38:59 PM PDT 24
Finished Mar 24 03:47:09 PM PDT 24
Peak memory 600208 kb
Host smart-f6b4179e-1989-47ad-bdff-ae7c32d011f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401967757 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2401967757
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3993260677
Short name T205
Test name
Test status
Simulation time 4337335160 ps
CPU time 992.34 seconds
Started Mar 24 03:38:21 PM PDT 24
Finished Mar 24 03:54:54 PM PDT 24
Peak memory 599876 kb
Host smart-307da5df-6484-41d7-83b6-185d3bf71021
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993260677 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3993260677
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.533150632
Short name T209
Test name
Test status
Simulation time 4809073496 ps
CPU time 744.38 seconds
Started Mar 24 03:40:00 PM PDT 24
Finished Mar 24 03:52:25 PM PDT 24
Peak memory 599800 kb
Host smart-7dfdc086-18ff-476a-9fb0-dc33dfb5feab
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533150632 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.533150632
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4038480726
Short name T217
Test name
Test status
Simulation time 5821108952 ps
CPU time 934.08 seconds
Started Mar 24 03:39:26 PM PDT 24
Finished Mar 24 03:55:01 PM PDT 24
Peak memory 599992 kb
Host smart-90c3a3b6-6341-4bb7-b743-69eeeee734a1
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038480726 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4038480726
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.728710834
Short name T137
Test name
Test status
Simulation time 65027124800 ps
CPU time 11391.1 seconds
Started Mar 24 03:39:21 PM PDT 24
Finished Mar 24 06:49:13 PM PDT 24
Peak memory 616396 kb
Host smart-a0b5e4b2-ebc3-43c6-b40b-550541111039
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=728710834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.728710834
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.658995966
Short name T938
Test name
Test status
Simulation time 3669891528 ps
CPU time 488.77 seconds
Started Mar 24 03:43:50 PM PDT 24
Finished Mar 24 03:51:59 PM PDT 24
Peak memory 606752 kb
Host smart-6b4e11f7-3e12-4286-a609-07fc7abaa8ab
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6589
95966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.658995966
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1830931792
Short name T865
Test name
Test status
Simulation time 3742596505 ps
CPU time 313.02 seconds
Started Mar 24 03:46:21 PM PDT 24
Finished Mar 24 03:51:35 PM PDT 24
Peak memory 607096 kb
Host smart-9caac556-eb7c-46f4-91fe-e955ff6dce55
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830931792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1830931792
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3313786580
Short name T144
Test name
Test status
Simulation time 5349115040 ps
CPU time 582.54 seconds
Started Mar 24 03:46:12 PM PDT 24
Finished Mar 24 03:55:55 PM PDT 24
Peak memory 606772 kb
Host smart-62808fe1-3896-4b8e-88dc-a9c1278c2381
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3313786580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.3313786580
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4006526264
Short name T109
Test name
Test status
Simulation time 4171775936 ps
CPU time 558.07 seconds
Started Mar 24 03:42:36 PM PDT 24
Finished Mar 24 03:51:54 PM PDT 24
Peak memory 605964 kb
Host smart-ea07e60f-4729-4203-b7a7-6cb75e846779
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4006526264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.4006526264
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2653292885
Short name T329
Test name
Test status
Simulation time 3690685768 ps
CPU time 551.74 seconds
Started Mar 24 03:43:37 PM PDT 24
Finished Mar 24 03:52:49 PM PDT 24
Peak memory 600492 kb
Host smart-57fe6d06-30f1-4fc4-a4bb-cffb98aa05d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265329
2885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2653292885
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.798883058
Short name T331
Test name
Test status
Simulation time 16996333240 ps
CPU time 3981.79 seconds
Started Mar 24 03:42:35 PM PDT 24
Finished Mar 24 04:48:57 PM PDT 24
Peak memory 600304 kb
Host smart-d13e8980-264b-441d-89b5-309d846f3a70
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79888
3058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.798883058
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.3957425600
Short name T80
Test name
Test status
Simulation time 2585530520 ps
CPU time 253.03 seconds
Started Mar 24 03:43:00 PM PDT 24
Finished Mar 24 03:47:14 PM PDT 24
Peak memory 599828 kb
Host smart-7dad0d7e-6824-4803-89ee-e4bb405c692b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957425600 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.3957425600
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.2646955266
Short name T838
Test name
Test status
Simulation time 2595833030 ps
CPU time 204.64 seconds
Started Mar 24 03:39:46 PM PDT 24
Finished Mar 24 03:43:11 PM PDT 24
Peak memory 599884 kb
Host smart-4d4a254f-fc8d-4220-9265-99351cf5aecf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646955266 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.2646955266
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.2214538912
Short name T869
Test name
Test status
Simulation time 2518094182 ps
CPU time 252.7 seconds
Started Mar 24 03:43:19 PM PDT 24
Finished Mar 24 03:47:32 PM PDT 24
Peak memory 599920 kb
Host smart-5e24df78-2c7d-4c9a-bc86-64b05308453e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214538912 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.2214538912
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2321710464
Short name T943
Test name
Test status
Simulation time 2671423214 ps
CPU time 313.13 seconds
Started Mar 24 03:45:02 PM PDT 24
Finished Mar 24 03:50:16 PM PDT 24
Peak memory 599844 kb
Host smart-333e6884-fca7-4eac-8b9b-b73a8da8411f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321710464 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2321710464
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.583007686
Short name T875
Test name
Test status
Simulation time 2859765734 ps
CPU time 290.94 seconds
Started Mar 24 03:45:20 PM PDT 24
Finished Mar 24 03:50:12 PM PDT 24
Peak memory 599844 kb
Host smart-9fd75c17-ddf3-40c8-b267-54c6f2d35989
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583007686 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_kmac_mode_kmac.583007686
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2148978288
Short name T303
Test name
Test status
Simulation time 2773198399 ps
CPU time 451.06 seconds
Started Mar 24 03:43:05 PM PDT 24
Finished Mar 24 03:50:36 PM PDT 24
Peak memory 599856 kb
Host smart-35d8bae8-5511-4b27-a740-79a6eed47048
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148978288 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2148978288
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3431852788
Short name T699
Test name
Test status
Simulation time 3167604717 ps
CPU time 294.33 seconds
Started Mar 24 03:48:52 PM PDT 24
Finished Mar 24 03:53:47 PM PDT 24
Peak memory 599828 kb
Host smart-9e9cc577-090e-44a9-add2-44d6904899b5
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318527
88 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3431852788
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.4094039225
Short name T619
Test name
Test status
Simulation time 3440642544 ps
CPU time 378.52 seconds
Started Mar 24 03:47:15 PM PDT 24
Finished Mar 24 03:53:35 PM PDT 24
Peak memory 599864 kb
Host smart-43bec97c-c7f8-4efa-957f-63555ca5fc27
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094039225 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_smoketest.4094039225
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3017297800
Short name T522
Test name
Test status
Simulation time 3545556114 ps
CPU time 327.05 seconds
Started Mar 24 03:39:53 PM PDT 24
Finished Mar 24 03:45:20 PM PDT 24
Peak memory 599876 kb
Host smart-9c3dab4c-10fe-4045-ac4e-64e2adfadec9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017297800 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3017297800
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.276882779
Short name T891
Test name
Test status
Simulation time 3439761374 ps
CPU time 155.1 seconds
Started Mar 24 03:40:18 PM PDT 24
Finished Mar 24 03:42:53 PM PDT 24
Peak memory 609556 kb
Host smart-e8524161-f184-46ce-8ff8-9312fdec1d00
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27688277
9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.276882779
Directory /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2234240875
Short name T300
Test name
Test status
Simulation time 5477023219 ps
CPU time 610.81 seconds
Started Mar 24 03:39:16 PM PDT 24
Finished Mar 24 03:49:28 PM PDT 24
Peak memory 612244 kb
Host smart-8a8e945d-6b5e-4cdd-af09-11cd43a6c1f0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234240875 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2234240875
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3365622434
Short name T298
Test name
Test status
Simulation time 2217667785 ps
CPU time 110.81 seconds
Started Mar 24 03:41:02 PM PDT 24
Finished Mar 24 03:42:53 PM PDT 24
Peak memory 607660 kb
Host smart-fc4001d9-80d1-41e4-a931-98dbf034ced9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3365622434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3365622434
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1413258231
Short name T894
Test name
Test status
Simulation time 2434418110 ps
CPU time 122.83 seconds
Started Mar 24 03:40:47 PM PDT 24
Finished Mar 24 03:42:50 PM PDT 24
Peak memory 606724 kb
Host smart-03f1609d-ab56-4f03-bcc3-1a14e2479d71
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413258231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1413258231
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2948647524
Short name T224
Test name
Test status
Simulation time 49257838410 ps
CPU time 5752.01 seconds
Started Mar 24 03:41:52 PM PDT 24
Finished Mar 24 05:17:45 PM PDT 24
Peak memory 607372 kb
Host smart-96ceb1ad-3651-456e-965f-45f3a96fc2d2
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948647524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi
p_sw_lc_walkthrough_prod.2948647524
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1800874738
Short name T832
Test name
Test status
Simulation time 9334517020 ps
CPU time 979.64 seconds
Started Mar 24 03:40:53 PM PDT 24
Finished Mar 24 03:57:14 PM PDT 24
Peak memory 607276 kb
Host smart-36803af9-9b05-4734-a866-04880604438b
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800874738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1800874738
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3909789942
Short name T714
Test name
Test status
Simulation time 48646780676 ps
CPU time 4907.38 seconds
Started Mar 24 03:40:30 PM PDT 24
Finished Mar 24 05:02:19 PM PDT 24
Peak memory 607344 kb
Host smart-8896fc17-c20a-4dc7-9841-b933fed626e9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909789942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_rma.3909789942
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2930799957
Short name T188
Test name
Test status
Simulation time 24866057190 ps
CPU time 2075.56 seconds
Started Mar 24 03:40:31 PM PDT 24
Finished Mar 24 04:15:07 PM PDT 24
Peak memory 608292 kb
Host smart-38766b92-5334-4c9f-aa8f-c914354e8052
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2930799957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.2930799957
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3937628822
Short name T626
Test name
Test status
Simulation time 17138992600 ps
CPU time 3328.61 seconds
Started Mar 24 03:42:02 PM PDT 24
Finished Mar 24 04:37:32 PM PDT 24
Peak memory 600008 kb
Host smart-8fe8cd15-8fff-4821-9ff2-99639f5dad64
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3937628822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3937628822
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.842670558
Short name T150
Test name
Test status
Simulation time 18412206729 ps
CPU time 3203.36 seconds
Started Mar 24 03:43:01 PM PDT 24
Finished Mar 24 04:36:26 PM PDT 24
Peak memory 599432 kb
Host smart-2965d7c1-257f-4d07-92b6-20b99dc00dd3
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=842670558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.842670558
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.845453124
Short name T391
Test name
Test status
Simulation time 24760367632 ps
CPU time 3104.21 seconds
Started Mar 24 03:46:15 PM PDT 24
Finished Mar 24 04:38:00 PM PDT 24
Peak memory 600100 kb
Host smart-adfdb373-de9b-4e1a-a3aa-034cc307946c
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845453124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc
ed_freq.845453124
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2853017682
Short name T251
Test name
Test status
Simulation time 3447769608 ps
CPU time 592.45 seconds
Started Mar 24 03:41:12 PM PDT 24
Finished Mar 24 03:51:05 PM PDT 24
Peak memory 600000 kb
Host smart-00902d7b-0791-4a74-9254-ae590bfc7041
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853017682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2853017682
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.1518332095
Short name T607
Test name
Test status
Simulation time 6280333032 ps
CPU time 811.53 seconds
Started Mar 24 03:42:15 PM PDT 24
Finished Mar 24 03:55:46 PM PDT 24
Peak memory 600068 kb
Host smart-e836dd6d-23f4-456a-b6fe-daf2c40b67b6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1518332095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1518332095
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.4284652046
Short name T181
Test name
Test status
Simulation time 6266165360 ps
CPU time 1257.33 seconds
Started Mar 24 03:46:54 PM PDT 24
Finished Mar 24 04:07:51 PM PDT 24
Peak memory 600196 kb
Host smart-11ff9674-3ae1-427c-a5c1-fe5a26c19e8e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284652046 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_otbn_smoketest.4284652046
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1552245997
Short name T769
Test name
Test status
Simulation time 7524664008 ps
CPU time 1268.12 seconds
Started Mar 24 03:41:59 PM PDT 24
Finished Mar 24 04:03:08 PM PDT 24
Peak memory 600016 kb
Host smart-ddd8bac6-8350-4472-86fe-289076b5fa45
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1552245997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1552245997
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2178191747
Short name T449
Test name
Test status
Simulation time 7776141896 ps
CPU time 1175.66 seconds
Started Mar 24 03:39:09 PM PDT 24
Finished Mar 24 03:58:45 PM PDT 24
Peak memory 600112 kb
Host smart-435961c3-0a6e-4ef9-ba95-656166feafdc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2178191747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2178191747
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2184982308
Short name T889
Test name
Test status
Simulation time 6188236990 ps
CPU time 1077.83 seconds
Started Mar 24 03:42:11 PM PDT 24
Finished Mar 24 04:00:10 PM PDT 24
Peak memory 600092 kb
Host smart-777bc696-3f76-49b5-9ae9-a14d9c38fca9
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2184982308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2184982308
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3609526504
Short name T565
Test name
Test status
Simulation time 4517589340 ps
CPU time 510.45 seconds
Started Mar 24 03:40:43 PM PDT 24
Finished Mar 24 03:49:14 PM PDT 24
Peak memory 600004 kb
Host smart-fa9a619c-a1ed-4c5a-9397-40b71a5508a7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3609526504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3609526504
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2485269902
Short name T627
Test name
Test status
Simulation time 3003594778 ps
CPU time 221.23 seconds
Started Mar 24 03:47:22 PM PDT 24
Finished Mar 24 03:51:04 PM PDT 24
Peak memory 599940 kb
Host smart-fdaed4cf-7759-4a53-8ec0-2141230c1059
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485269902 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_otp_ctrl_smoketest.2485269902
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.791433996
Short name T236
Test name
Test status
Simulation time 3062186292 ps
CPU time 335.27 seconds
Started Mar 24 03:44:22 PM PDT 24
Finished Mar 24 03:49:58 PM PDT 24
Peak memory 599916 kb
Host smart-ee582a04-d436-44e6-9140-8f65268d8aa8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791433996 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_plic_sw_irq.791433996
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.1582945465
Short name T917
Test name
Test status
Simulation time 4581118474 ps
CPU time 846.99 seconds
Started Mar 24 03:46:02 PM PDT 24
Finished Mar 24 04:00:09 PM PDT 24
Peak memory 599852 kb
Host smart-ec3d2af1-5350-484c-8f32-e402c86a013f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582945465 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1582945465
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.1186723252
Short name T161
Test name
Test status
Simulation time 4655110554 ps
CPU time 434.02 seconds
Started Mar 24 03:46:33 PM PDT 24
Finished Mar 24 03:53:48 PM PDT 24
Peak memory 599916 kb
Host smart-3709ead0-290d-42e8-b0b3-4dd7caa593cd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186723252 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1186723252
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.90504766
Short name T811
Test name
Test status
Simulation time 11074026429 ps
CPU time 1423.45 seconds
Started Mar 24 03:40:56 PM PDT 24
Finished Mar 24 04:04:40 PM PDT 24
Peak memory 600372 kb
Host smart-586987c8-c8f0-4385-9625-c65d749fc3e2
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9050
4766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.90504766
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.919288378
Short name T647
Test name
Test status
Simulation time 23219619288 ps
CPU time 2038.68 seconds
Started Mar 24 03:45:03 PM PDT 24
Finished Mar 24 04:19:02 PM PDT 24
Peak memory 599892 kb
Host smart-dee42d33-4fd0-48f9-8ee3-e1fefb1e2788
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919
288378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.919288378
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1586503452
Short name T698
Test name
Test status
Simulation time 17244749688 ps
CPU time 1314.05 seconds
Started Mar 24 03:39:52 PM PDT 24
Finished Mar 24 04:01:47 PM PDT 24
Peak memory 600384 kb
Host smart-98fc9527-8a37-4ca3-b731-35374adec934
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1586503452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1586503452
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3928282904
Short name T399
Test name
Test status
Simulation time 21267113514 ps
CPU time 1638.1 seconds
Started Mar 24 03:45:18 PM PDT 24
Finished Mar 24 04:12:37 PM PDT 24
Peak memory 601004 kb
Host smart-7cd43703-ec6e-42d3-8e80-217bed8e6f2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3928282904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3928282904
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1364842538
Short name T605
Test name
Test status
Simulation time 6629378356 ps
CPU time 325.7 seconds
Started Mar 24 03:40:16 PM PDT 24
Finished Mar 24 03:45:42 PM PDT 24
Peak memory 605936 kb
Host smart-df0c4efa-f46d-4a31-a4a2-abbe8f1b5ed3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1364842538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1364842538
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2030644195
Short name T438
Test name
Test status
Simulation time 4673987833 ps
CPU time 376.86 seconds
Started Mar 24 03:45:27 PM PDT 24
Finished Mar 24 03:51:44 PM PDT 24
Peak memory 605972 kb
Host smart-d11e862f-5d1c-43ce-8e5d-23b341bd4680
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2030644195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.2030644195
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1230063542
Short name T337
Test name
Test status
Simulation time 11849189516 ps
CPU time 1004.33 seconds
Started Mar 24 03:41:49 PM PDT 24
Finished Mar 24 03:58:34 PM PDT 24
Peak memory 600740 kb
Host smart-5030e6f9-3630-4d09-a225-912ae3428b4a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230063542 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1230063542
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3774073221
Short name T400
Test name
Test status
Simulation time 7176504664 ps
CPU time 494.82 seconds
Started Mar 24 03:46:21 PM PDT 24
Finished Mar 24 03:54:36 PM PDT 24
Peak memory 600024 kb
Host smart-ba2c9a1d-3c3d-4e62-abf7-ac185c4da84c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774073221 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3774073221
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1447748295
Short name T668
Test name
Test status
Simulation time 5687331564 ps
CPU time 896 seconds
Started Mar 24 03:41:27 PM PDT 24
Finished Mar 24 03:56:23 PM PDT 24
Peak memory 599880 kb
Host smart-2e78e30a-6c56-4896-add2-e81889236fe5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447748295 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1447748295
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.658515640
Short name T622
Test name
Test status
Simulation time 24994167781 ps
CPU time 1761.93 seconds
Started Mar 24 03:41:03 PM PDT 24
Finished Mar 24 04:10:26 PM PDT 24
Peak memory 600732 kb
Host smart-4f3c666c-59a6-4155-ace0-e6f755b62694
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=658515640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.658515640
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.983814700
Short name T66
Test name
Test status
Simulation time 18265711400 ps
CPU time 1291 seconds
Started Mar 24 03:44:34 PM PDT 24
Finished Mar 24 04:06:05 PM PDT 24
Peak memory 601268 kb
Host smart-c00a4103-605c-448a-81da-14593c9221a1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=983814700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.983814700
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3074823509
Short name T913
Test name
Test status
Simulation time 29292627976 ps
CPU time 2816.5 seconds
Started Mar 24 03:41:07 PM PDT 24
Finished Mar 24 04:28:04 PM PDT 24
Peak memory 602472 kb
Host smart-c5b7ea5e-aa90-460e-8c4e-c002c01d1c5c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074823509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3074823509
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2261698764
Short name T234
Test name
Test status
Simulation time 2835587430 ps
CPU time 232.32 seconds
Started Mar 24 03:41:49 PM PDT 24
Finished Mar 24 03:45:42 PM PDT 24
Peak memory 599924 kb
Host smart-b86f8f4f-667d-4085-9a2c-0fb5ff36ce7e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261698764 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2261698764
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3729349850
Short name T650
Test name
Test status
Simulation time 3987926614 ps
CPU time 502.81 seconds
Started Mar 24 03:40:12 PM PDT 24
Finished Mar 24 03:48:35 PM PDT 24
Peak memory 606044 kb
Host smart-c1672657-349a-4f18-bb9f-b2fe68f737c6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3729349850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3729349850
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.593584734
Short name T160
Test name
Test status
Simulation time 5368408700 ps
CPU time 512 seconds
Started Mar 24 03:43:45 PM PDT 24
Finished Mar 24 03:52:18 PM PDT 24
Peak memory 600076 kb
Host smart-b48b5f0b-d87b-4d92-9977-c93e4a851c19
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59358473
4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.593584734
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1253258774
Short name T153
Test name
Test status
Simulation time 5894431508 ps
CPU time 585.48 seconds
Started Mar 24 03:45:52 PM PDT 24
Finished Mar 24 03:55:38 PM PDT 24
Peak memory 599604 kb
Host smart-8b71eff8-9cdd-4bd0-b2fd-e592673eb6c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1253258774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1253258774
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2961675918
Short name T553
Test name
Test status
Simulation time 6005623916 ps
CPU time 574.04 seconds
Started Mar 24 03:47:33 PM PDT 24
Finished Mar 24 03:57:07 PM PDT 24
Peak memory 600024 kb
Host smart-856901dc-805f-4cc5-9709-6cefbe3220bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961675918 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2961675918
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.934547586
Short name T792
Test name
Test status
Simulation time 6328623420 ps
CPU time 1032.46 seconds
Started Mar 24 03:40:00 PM PDT 24
Finished Mar 24 03:57:12 PM PDT 24
Peak memory 599704 kb
Host smart-b4797dd4-b9a4-4b2d-a8db-9740cc5e3e0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934547586 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.934547586
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.766989332
Short name T588
Test name
Test status
Simulation time 4707351894 ps
CPU time 363.61 seconds
Started Mar 24 03:40:08 PM PDT 24
Finished Mar 24 03:46:12 PM PDT 24
Peak memory 600004 kb
Host smart-d47af015-1627-4181-9add-d3b43a9497f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766989332 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.766989332
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.442838265
Short name T806
Test name
Test status
Simulation time 5362969280 ps
CPU time 291.01 seconds
Started Mar 24 03:49:15 PM PDT 24
Finished Mar 24 03:54:06 PM PDT 24
Peak memory 600000 kb
Host smart-8ffc144a-a4b3-4f2d-8f81-7717671bad3b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442838265 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.442838265
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2477310204
Short name T527
Test name
Test status
Simulation time 4223399168 ps
CPU time 501.83 seconds
Started Mar 24 03:41:11 PM PDT 24
Finished Mar 24 03:49:33 PM PDT 24
Peak memory 599852 kb
Host smart-32e8056b-50eb-4158-b8b7-d3296841c4d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247
7310204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2477310204
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3428150472
Short name T853
Test name
Test status
Simulation time 9093875778 ps
CPU time 557.08 seconds
Started Mar 24 03:44:22 PM PDT 24
Finished Mar 24 03:53:39 PM PDT 24
Peak memory 600048 kb
Host smart-dc925bb0-a166-4037-8aa6-881b458e1058
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428150472 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3428150472
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.854632533
Short name T206
Test name
Test status
Simulation time 10438402568 ps
CPU time 1258.24 seconds
Started Mar 24 03:45:35 PM PDT 24
Finished Mar 24 04:06:34 PM PDT 24
Peak memory 600028 kb
Host smart-d6adcaed-f3fb-4796-8821-cbadaba0c660
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=854632533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.854632533
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.492716964
Short name T758
Test name
Test status
Simulation time 6123704952 ps
CPU time 725.75 seconds
Started Mar 24 03:39:47 PM PDT 24
Finished Mar 24 03:51:53 PM PDT 24
Peak memory 631596 kb
Host smart-16d390d7-900c-44bf-aecd-5a788d61fd99
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
492716964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.492716964
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.817869022
Short name T884
Test name
Test status
Simulation time 2199050000 ps
CPU time 268.55 seconds
Started Mar 24 03:48:14 PM PDT 24
Finished Mar 24 03:52:43 PM PDT 24
Peak memory 599948 kb
Host smart-398f152a-5433-44bb-9563-4d4a0a1edc54
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817869022 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_rstmgr_smoketest.817869022
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3363180210
Short name T533
Test name
Test status
Simulation time 4650306356 ps
CPU time 346.83 seconds
Started Mar 24 03:41:09 PM PDT 24
Finished Mar 24 03:46:56 PM PDT 24
Peak memory 599928 kb
Host smart-6c20902c-dfb8-477a-b7c6-bb759d50f1e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363180210 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rstmgr_sw_req.3363180210
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3070170196
Short name T85
Test name
Test status
Simulation time 2555771244 ps
CPU time 265.44 seconds
Started Mar 24 03:42:24 PM PDT 24
Finished Mar 24 03:46:50 PM PDT 24
Peak memory 600004 kb
Host smart-7b7a2b1e-ee22-4764-b029-cc9497a0d3d2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070170196 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3070170196
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3572389000
Short name T263
Test name
Test status
Simulation time 2472355316 ps
CPU time 266.06 seconds
Started Mar 24 03:45:36 PM PDT 24
Finished Mar 24 03:50:03 PM PDT 24
Peak memory 599040 kb
Host smart-1e9d2b9b-12de-433c-aa9f-d15a4cab31ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3572389000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3572389000
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1048841228
Short name T310
Test name
Test status
Simulation time 3126623859 ps
CPU time 314.26 seconds
Started Mar 24 03:47:12 PM PDT 24
Finished Mar 24 03:52:27 PM PDT 24
Peak memory 599608 kb
Host smart-e6f82973-c11c-4ca1-8595-c648a0663fc3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048841228 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1048841228
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2583399637
Short name T409
Test name
Test status
Simulation time 4667253120 ps
CPU time 990.42 seconds
Started Mar 24 03:42:54 PM PDT 24
Finished Mar 24 03:59:24 PM PDT 24
Peak memory 599996 kb
Host smart-64f45334-9a44-4d1f-bd9f-d825dfb1431c
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25833
99637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2583399637
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3160805160
Short name T822
Test name
Test status
Simulation time 5492166878 ps
CPU time 1013.93 seconds
Started Mar 24 03:42:32 PM PDT 24
Finished Mar 24 03:59:26 PM PDT 24
Peak memory 599808 kb
Host smart-563565b5-1641-4868-b578-a8115fc8d657
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3160805160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3160805160
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1535974986
Short name T414
Test name
Test status
Simulation time 4236841507 ps
CPU time 613.06 seconds
Started Mar 24 03:45:40 PM PDT 24
Finished Mar 24 03:55:54 PM PDT 24
Peak memory 607208 kb
Host smart-bd89c6f9-67f8-4fe8-b043-f6d1645b7237
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535974986 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1535974986
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2440341739
Short name T45
Test name
Test status
Simulation time 4151702554 ps
CPU time 583.83 seconds
Started Mar 24 03:47:01 PM PDT 24
Finished Mar 24 03:56:45 PM PDT 24
Peak memory 607256 kb
Host smart-dfdc4b08-ae58-486e-a4c3-29b9e8a0b164
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244034
1739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2440341739
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3762085284
Short name T649
Test name
Test status
Simulation time 2690390080 ps
CPU time 294.96 seconds
Started Mar 24 03:48:27 PM PDT 24
Finished Mar 24 03:53:23 PM PDT 24
Peak memory 599860 kb
Host smart-0e828a37-8d14-4423-a71a-5a995cdd9d7a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762085284 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_plic_smoketest.3762085284
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.3484349484
Short name T265
Test name
Test status
Simulation time 2501765180 ps
CPU time 223.09 seconds
Started Mar 24 03:40:16 PM PDT 24
Finished Mar 24 03:43:59 PM PDT 24
Peak memory 599920 kb
Host smart-a4165ad9-aa1d-4450-9e1c-98b38f6a6d85
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484349484 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_irq.3484349484
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1635905677
Short name T850
Test name
Test status
Simulation time 2810571720 ps
CPU time 221.48 seconds
Started Mar 24 03:49:38 PM PDT 24
Finished Mar 24 03:53:20 PM PDT 24
Peak memory 599916 kb
Host smart-e3730166-1bcd-4007-bbc4-2254e97f358c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635905677 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_smoketest.1635905677
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2025678823
Short name T156
Test name
Test status
Simulation time 8630778792 ps
CPU time 985.46 seconds
Started Mar 24 03:43:50 PM PDT 24
Finished Mar 24 04:00:16 PM PDT 24
Peak memory 599956 kb
Host smart-bb74e926-612b-43de-b4fd-f4a56bf9a531
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256788
23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2025678823
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3967649145
Short name T140
Test name
Test status
Simulation time 2485536031 ps
CPU time 259.79 seconds
Started Mar 24 03:44:23 PM PDT 24
Finished Mar 24 03:48:43 PM PDT 24
Peak memory 599908 kb
Host smart-0b31dfe1-53df-4850-8eb3-ae2e49222351
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967649
145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3967649145
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3323417437
Short name T62
Test name
Test status
Simulation time 3412461360 ps
CPU time 262.48 seconds
Started Mar 24 03:39:32 PM PDT 24
Finished Mar 24 03:43:55 PM PDT 24
Peak memory 599256 kb
Host smart-6459cd95-9a33-4e8c-b427-d1ab9f0133f3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323417437 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.3323417437
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.159424545
Short name T795
Test name
Test status
Simulation time 8425527064 ps
CPU time 1470.96 seconds
Started Mar 24 03:38:18 PM PDT 24
Finished Mar 24 04:02:50 PM PDT 24
Peak memory 599792 kb
Host smart-2abfbf3a-f7db-49f4-b916-735aa7881061
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159424545 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.159424545
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.790718002
Short name T562
Test name
Test status
Simulation time 8183291442 ps
CPU time 665.86 seconds
Started Mar 24 03:44:55 PM PDT 24
Finished Mar 24 03:56:01 PM PDT 24
Peak memory 600388 kb
Host smart-45bbf2a8-30d3-4eef-8fd6-414b2472bb4b
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790718002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle
ep_sram_ret_contents_no_scramble.790718002
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3550854268
Short name T198
Test name
Test status
Simulation time 7957802962 ps
CPU time 487.3 seconds
Started Mar 24 03:48:23 PM PDT 24
Finished Mar 24 03:56:31 PM PDT 24
Peak memory 600620 kb
Host smart-45becd4f-f479-45a3-8419-633d99ddea49
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550854268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.3550854268
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1886572291
Short name T166
Test name
Test status
Simulation time 7432443902 ps
CPU time 878.86 seconds
Started Mar 24 03:40:41 PM PDT 24
Finished Mar 24 03:55:20 PM PDT 24
Peak memory 616532 kb
Host smart-f1b843d2-c2a5-4a26-8443-04a43372dd2c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886572291 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1886572291
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2830248555
Short name T88
Test name
Test status
Simulation time 4871995742 ps
CPU time 585.23 seconds
Started Mar 24 03:40:19 PM PDT 24
Finished Mar 24 03:50:05 PM PDT 24
Peak memory 621564 kb
Host smart-a2600376-442e-41a3-b462-018ed23f974e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830248555 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2830248555
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.1537320243
Short name T36
Test name
Test status
Simulation time 3312235430 ps
CPU time 389.18 seconds
Started Mar 24 03:39:24 PM PDT 24
Finished Mar 24 03:45:54 PM PDT 24
Peak memory 607228 kb
Host smart-6aad453c-49de-4ba0-a686-d5b52dd2e1d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537320243 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1537320243
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1322576153
Short name T113
Test name
Test status
Simulation time 10186046090 ps
CPU time 947.57 seconds
Started Mar 24 03:44:25 PM PDT 24
Finished Mar 24 04:00:13 PM PDT 24
Peak memory 600256 kb
Host smart-9f74c094-ae0c-4551-af19-c7d9d5cae7a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322576153 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1322576153
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4125763673
Short name T290
Test name
Test status
Simulation time 4251433896 ps
CPU time 615.69 seconds
Started Mar 24 03:44:27 PM PDT 24
Finished Mar 24 03:54:43 PM PDT 24
Peak memory 600948 kb
Host smart-1639770a-2a3a-4302-ab82-c91175a125b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125763673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw
_sram_ctrl_scrambled_access.4125763673
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3690422224
Short name T885
Test name
Test status
Simulation time 3998341037 ps
CPU time 494.75 seconds
Started Mar 24 03:44:47 PM PDT 24
Finished Mar 24 03:53:02 PM PDT 24
Peak memory 600036 kb
Host smart-d7a93e8a-1dbf-48bd-9cd4-6283f2f7dbdb
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690422224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3690422224
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2166838140
Short name T289
Test name
Test status
Simulation time 4095101305 ps
CPU time 511.87 seconds
Started Mar 24 03:46:47 PM PDT 24
Finished Mar 24 03:55:19 PM PDT 24
Peak memory 600040 kb
Host smart-dc185c20-626b-4c7c-b7d3-99902a4f959d
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166838140 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2166838140
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3818371381
Short name T308
Test name
Test status
Simulation time 2829907870 ps
CPU time 202.71 seconds
Started Mar 24 03:47:27 PM PDT 24
Finished Mar 24 03:50:50 PM PDT 24
Peak memory 599884 kb
Host smart-788b4906-fd73-4096-90eb-ad9b803107c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818371381 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3818371381
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.25141064
Short name T925
Test name
Test status
Simulation time 20718227060 ps
CPU time 2963.34 seconds
Started Mar 24 03:41:15 PM PDT 24
Finished Mar 24 04:30:39 PM PDT 24
Peak memory 599932 kb
Host smart-7bb6cce0-a215-450b-9888-acaeafb72629
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141064 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.25141064
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.607181365
Short name T242
Test name
Test status
Simulation time 3970082894 ps
CPU time 610.37 seconds
Started Mar 24 03:41:35 PM PDT 24
Finished Mar 24 03:51:48 PM PDT 24
Peak memory 602868 kb
Host smart-ab934b66-6998-41df-9102-84abe459929f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607181365 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.607181365
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.50280573
Short name T241
Test name
Test status
Simulation time 3425422038 ps
CPU time 479.7 seconds
Started Mar 24 03:41:38 PM PDT 24
Finished Mar 24 03:49:39 PM PDT 24
Peak memory 602844 kb
Host smart-0ad8c03f-8cf8-4c42-8d37-6bbe6e419d9a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50280573 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.50280573
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292243456
Short name T358
Test name
Test status
Simulation time 22981260664 ps
CPU time 1408.03 seconds
Started Mar 24 03:42:08 PM PDT 24
Finished Mar 24 04:05:37 PM PDT 24
Peak memory 604316 kb
Host smart-9f3560e0-9db6-48c4-afd8-3e621c4c6ad0
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922434
56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1292243456
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4028687481
Short name T932
Test name
Test status
Simulation time 5617720584 ps
CPU time 578.48 seconds
Started Mar 24 03:41:03 PM PDT 24
Finished Mar 24 03:50:42 PM PDT 24
Peak memory 600044 kb
Host smart-1cc80979-db82-468d-8781-7a605a0378d2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028687481 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4028687481
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.3457723453
Short name T563
Test name
Test status
Simulation time 2567358280 ps
CPU time 227.59 seconds
Started Mar 24 03:47:15 PM PDT 24
Finished Mar 24 03:51:03 PM PDT 24
Peak memory 599640 kb
Host smart-7c8bb26b-7e84-49d3-8656-c8a5fc9f9efb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457723453 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_uart_smoketest.3457723453
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3532541506
Short name T293
Test name
Test status
Simulation time 9053046644 ps
CPU time 1760.44 seconds
Started Mar 24 03:51:49 PM PDT 24
Finished Mar 24 04:21:10 PM PDT 24
Peak memory 599112 kb
Host smart-6ed7d669-a835-45af-bab4-497d760d6911
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa
ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3532541506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_smoketest_signed.3532541506
Directory /workspace/2.chip_sw_uart_smoketest_signed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.2684953944
Short name T827
Test name
Test status
Simulation time 5442156543 ps
CPU time 893.15 seconds
Started Mar 24 03:37:50 PM PDT 24
Finished Mar 24 03:52:44 PM PDT 24
Peak memory 608088 kb
Host smart-f0406d0d-dbbd-42cb-95ab-dfe5acc1b43d
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684953944 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2684953944
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2768935571
Short name T675
Test name
Test status
Simulation time 22946522973 ps
CPU time 3398.43 seconds
Started Mar 24 03:38:21 PM PDT 24
Finished Mar 24 04:35:00 PM PDT 24
Peak memory 607176 kb
Host smart-873f563a-e205-439e-8606-b7f1c13a54f2
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768935571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.2768935571
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.322645551
Short name T920
Test name
Test status
Simulation time 78753745332 ps
CPU time 13328 seconds
Started Mar 24 03:39:05 PM PDT 24
Finished Mar 24 07:21:15 PM PDT 24
Peak memory 621568 kb
Host smart-8c0b81eb-688a-42aa-bd32-5142255ca567
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:
1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=322645551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.322645551
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2440717704
Short name T639
Test name
Test status
Simulation time 5756504387 ps
CPU time 920.77 seconds
Started Mar 24 03:38:08 PM PDT 24
Finished Mar 24 03:53:30 PM PDT 24
Peak memory 607148 kb
Host smart-b3eab58c-36b7-4b1e-9c82-6e23ffb43fa7
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440717704 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2440717704
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.566934029
Short name T787
Test name
Test status
Simulation time 5548673541 ps
CPU time 846.35 seconds
Started Mar 24 03:39:02 PM PDT 24
Finished Mar 24 03:53:09 PM PDT 24
Peak memory 608044 kb
Host smart-67f9e05a-dd08-41e8-85b6-6a8eacb8d11e
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566934029 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.566934029
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2196190405
Short name T864
Test name
Test status
Simulation time 5295168533 ps
CPU time 853.97 seconds
Started Mar 24 03:39:33 PM PDT 24
Finished Mar 24 03:53:47 PM PDT 24
Peak memory 607128 kb
Host smart-7daf3843-be27-4658-8d53-be0233f34d98
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196190405 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2196190405
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.141177994
Short name T815
Test name
Test status
Simulation time 4260040626 ps
CPU time 442.06 seconds
Started Mar 24 03:44:17 PM PDT 24
Finished Mar 24 03:51:40 PM PDT 24
Peak memory 609108 kb
Host smart-c7d2b81d-bd64-4985-af86-f5b49cc56fbf
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=141177994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.141177994
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.918808215
Short name T599
Test name
Test status
Simulation time 2714852603 ps
CPU time 136.85 seconds
Started Mar 24 03:45:01 PM PDT 24
Finished Mar 24 03:47:18 PM PDT 24
Peak memory 608576 kb
Host smart-03ab75c0-2cd8-4e53-b0e5-a2b1adc55fc3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=918808215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.918808215
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.chip_tap_straps_rma.1959776865
Short name T862
Test name
Test status
Simulation time 2094167267 ps
CPU time 143 seconds
Started Mar 24 03:47:32 PM PDT 24
Finished Mar 24 03:49:55 PM PDT 24
Peak memory 609012 kb
Host smart-006cf391-7ae0-42bb-bce0-540ea43b4a3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959776865 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1959776865
Directory /workspace/2.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/2.chip_tap_straps_testunlock0.3771241453
Short name T118
Test name
Test status
Simulation time 3257757173 ps
CPU time 234.29 seconds
Started Mar 24 03:46:54 PM PDT 24
Finished Mar 24 03:50:48 PM PDT 24
Peak memory 618820 kb
Host smart-a053abe2-a74f-457d-89c3-f1ca690f4438
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771241453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3771241453
Directory /workspace/2.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.2774443119
Short name T840
Test name
Test status
Simulation time 8733452079 ps
CPU time 1421.78 seconds
Started Mar 24 03:53:33 PM PDT 24
Finished Mar 24 04:17:15 PM PDT 24
Peak memory 600208 kb
Host smart-5234e396-9df6-4a35-b92f-ab6ac1979d71
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774443119 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.rom_e2e_asm_init_dev.2774443119
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.3500707236
Short name T814
Test name
Test status
Simulation time 8507188581 ps
CPU time 1622.84 seconds
Started Mar 24 03:53:56 PM PDT 24
Finished Mar 24 04:21:00 PM PDT 24
Peak memory 600152 kb
Host smart-c481a3ff-04b2-446e-837a-6c5bf18ee500
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500707236 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.rom_e2e_asm_init_prod.3500707236
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.518026688
Short name T750
Test name
Test status
Simulation time 8494916396 ps
CPU time 1649.11 seconds
Started Mar 24 03:50:09 PM PDT 24
Finished Mar 24 04:17:39 PM PDT 24
Peak memory 600456 kb
Host smart-1a655abd-6144-441a-9a0c-4ec434df3e13
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518026688 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rom_e2e_asm_init_prod_end.518026688
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.1976080251
Short name T618
Test name
Test status
Simulation time 9291890785 ps
CPU time 1794.39 seconds
Started Mar 24 03:51:47 PM PDT 24
Finished Mar 24 04:21:42 PM PDT 24
Peak memory 600256 kb
Host smart-4c6e919a-da9a-46fe-a740-b5d6a8a82b2e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla
sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976080251 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.rom_e2e_asm_init_rma.1976080251
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3734564227
Short name T809
Test name
Test status
Simulation time 6853268540 ps
CPU time 1273.55 seconds
Started Mar 24 03:53:56 PM PDT 24
Finished Mar 24 04:15:10 PM PDT 24
Peak memory 600348 kb
Host smart-13b54922-3d07-47f0-8538-ff4052e656cf
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_
flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734564227 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3734564227
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4263178199
Short name T670
Test name
Test status
Simulation time 8317579989 ps
CPU time 1662.81 seconds
Started Mar 24 03:51:18 PM PDT 24
Finished Mar 24 04:19:01 PM PDT 24
Peak memory 599988 kb
Host smart-d8ac9eeb-1cb8-49e4-8827-6da5268acc81
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_
with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4263178199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.4263178199
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.1029459875
Short name T297
Test name
Test status
Simulation time 27171110439 ps
CPU time 2792.52 seconds
Started Mar 24 03:53:33 PM PDT 24
Finished Mar 24 04:40:06 PM PDT 24
Peak memory 600008 kb
Host smart-bd3bea36-487a-4585-81a6-c0c7e7e384d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina
ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029459875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.rom_e2e_shutdown_output.1029459875
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.3770430326
Short name T732
Test name
Test status
Simulation time 8572378946 ps
CPU time 1954.67 seconds
Started Mar 24 03:47:32 PM PDT 24
Finished Mar 24 04:20:07 PM PDT 24
Peak memory 600132 kb
Host smart-2de211af-b55b-46c9-af8e-867becf44361
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0
,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3770430326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3770430326
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.1650764168
Short name T640
Test name
Test status
Simulation time 10979632900 ps
CPU time 2189.87 seconds
Started Mar 24 03:52:40 PM PDT 24
Finished Mar 24 04:29:11 PM PDT 24
Peak memory 600080 kb
Host smart-7638a124-a7a7-4914-bd1f-fe087da42937
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_
fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1650764168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1650764168
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.4237606466
Short name T691
Test name
Test status
Simulation time 5104572580 ps
CPU time 513.76 seconds
Started Mar 24 03:47:29 PM PDT 24
Finished Mar 24 03:56:04 PM PDT 24
Peak memory 599928 kb
Host smart-0964791d-59b6-4763-b75e-e4b6464ba2ab
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237606466 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.4237606466
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.4076314419
Short name T344
Test name
Test status
Simulation time 16438242639 ps
CPU time 1853.43 seconds
Started Mar 24 03:47:50 PM PDT 24
Finished Mar 24 04:18:44 PM PDT 24
Peak memory 607360 kb
Host smart-d7a978cc-5075-4809-a81c-d5d65e33bd5d
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4076314419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.4076314419
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.816814722
Short name T417
Test name
Test status
Simulation time 2613287502 ps
CPU time 106.52 seconds
Started Mar 24 03:48:42 PM PDT 24
Finished Mar 24 03:50:29 PM PDT 24
Peak memory 606672 kb
Host smart-40d8dd64-fe63-4d87-9cc5-d0ba88842c51
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816814722 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.816814722
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1619791346
Short name T232
Test name
Test status
Simulation time 4091049190 ps
CPU time 403.22 seconds
Started Mar 24 03:52:50 PM PDT 24
Finished Mar 24 03:59:34 PM PDT 24
Peak memory 636128 kb
Host smart-beb7a400-a78c-4e86-b6d6-47df45547f95
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619791346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1619791346
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332145607
Short name T789
Test name
Test status
Simulation time 3941171658 ps
CPU time 430.89 seconds
Started Mar 24 03:51:05 PM PDT 24
Finished Mar 24 03:58:16 PM PDT 24
Peak memory 635928 kb
Host smart-4c0a969a-076d-4b31-b4ec-ca5e1dfb429f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332145607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3332145607
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.3232562571
Short name T434
Test name
Test status
Simulation time 5768047998 ps
CPU time 664.22 seconds
Started Mar 24 03:50:35 PM PDT 24
Finished Mar 24 04:01:40 PM PDT 24
Peak memory 635184 kb
Host smart-f0b32e34-744b-455b-bdd2-c351637ceaa3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3232562571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3232562571
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.102239847
Short name T132
Test name
Test status
Simulation time 4340667820 ps
CPU time 830.45 seconds
Started Mar 24 03:50:49 PM PDT 24
Finished Mar 24 04:04:40 PM PDT 24
Peak memory 636288 kb
Host smart-b461a056-fed7-4f28-9f84-a74194398e44
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
102239847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.102239847
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2126053359
Short name T494
Test name
Test status
Simulation time 4003135072 ps
CPU time 327.83 seconds
Started Mar 24 03:51:05 PM PDT 24
Finished Mar 24 03:56:33 PM PDT 24
Peak memory 635932 kb
Host smart-e3bb2fae-8531-4636-8e32-df157b2ad606
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126053359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2126053359
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.581809067
Short name T131
Test name
Test status
Simulation time 3734356470 ps
CPU time 309.15 seconds
Started Mar 24 03:51:19 PM PDT 24
Finished Mar 24 03:56:29 PM PDT 24
Peak memory 636020 kb
Host smart-ccf1ce9f-040a-4ccb-8cca-71333e01e10f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581809067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s
w_alert_handler_lpg_sleep_mode_alerts.581809067
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/28.chip_sw_all_escalation_resets.2471816811
Short name T302
Test name
Test status
Simulation time 4760715280 ps
CPU time 501.07 seconds
Started Mar 24 03:52:19 PM PDT 24
Finished Mar 24 04:00:40 PM PDT 24
Peak memory 635196 kb
Host smart-37541084-c324-4110-9db9-e6d635c8829a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2471816811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.2471816811
Directory /workspace/28.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.3686677858
Short name T451
Test name
Test status
Simulation time 5359912416 ps
CPU time 604.07 seconds
Started Mar 24 03:47:29 PM PDT 24
Finished Mar 24 03:57:33 PM PDT 24
Peak memory 635224 kb
Host smart-5deda6fe-f27c-4b8c-a1d0-02aac6036bfe
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3686677858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3686677858
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.373582710
Short name T537
Test name
Test status
Simulation time 8142997040 ps
CPU time 486.85 seconds
Started Mar 24 03:48:11 PM PDT 24
Finished Mar 24 03:56:19 PM PDT 24
Peak memory 600024 kb
Host smart-3a5e4254-fe1c-498d-b39d-ad7f4fa17fe1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=373582710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.373582710
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3109889620
Short name T844
Test name
Test status
Simulation time 13309610610 ps
CPU time 1224.15 seconds
Started Mar 24 03:47:48 PM PDT 24
Finished Mar 24 04:08:13 PM PDT 24
Peak memory 611600 kb
Host smart-1e5351ca-65c0-4413-96ba-47796f63cf07
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109889620 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.3109889620
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1975287718
Short name T136
Test name
Test status
Simulation time 4485459281 ps
CPU time 737.6 seconds
Started Mar 24 03:48:13 PM PDT 24
Finished Mar 24 04:00:32 PM PDT 24
Peak memory 607184 kb
Host smart-4ab15b67-ef85-4939-824d-c77e86412863
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975287718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq.1975287718
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2968708892
Short name T245
Test name
Test status
Simulation time 4796741672 ps
CPU time 687.03 seconds
Started Mar 24 03:48:26 PM PDT 24
Finished Mar 24 03:59:54 PM PDT 24
Peak memory 607240 kb
Host smart-c3de6c7e-bfd7-4965-a152-dd04095dcbb5
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968708892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2968708892
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1588337403
Short name T246
Test name
Test status
Simulation time 5494593409 ps
CPU time 740.8 seconds
Started Mar 24 03:48:00 PM PDT 24
Finished Mar 24 04:00:21 PM PDT 24
Peak memory 607192 kb
Host smart-a7758619-352b-4515-a717-6f3a17ed61aa
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588337403 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1588337403
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2287091036
Short name T725
Test name
Test status
Simulation time 5291253764 ps
CPU time 737.2 seconds
Started Mar 24 03:48:25 PM PDT 24
Finished Mar 24 04:00:43 PM PDT 24
Peak memory 608120 kb
Host smart-274b2f31-6c28-42dd-b2ba-7b79239fe8e6
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287091036 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2287091036
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.1230920853
Short name T279
Test name
Test status
Simulation time 12180320995 ps
CPU time 1062.05 seconds
Started Mar 24 03:47:35 PM PDT 24
Finished Mar 24 04:05:18 PM PDT 24
Peak memory 609584 kb
Host smart-1079949c-21d8-4720-8190-f2bf914af4cd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1230920853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1230920853
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.2163637343
Short name T810
Test name
Test status
Simulation time 12991414057 ps
CPU time 1105.69 seconds
Started Mar 24 03:47:48 PM PDT 24
Finished Mar 24 04:06:15 PM PDT 24
Peak memory 609560 kb
Host smart-33b3bd14-731b-4ad1-8cdc-24712e02d884
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2163637343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2163637343
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/3.chip_tap_straps_rma.2454876631
Short name T116
Test name
Test status
Simulation time 2907485427 ps
CPU time 138.65 seconds
Started Mar 24 03:47:13 PM PDT 24
Finished Mar 24 03:49:33 PM PDT 24
Peak memory 617660 kb
Host smart-180c5b17-c251-43e0-a7fe-47d05ba0e578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454876631 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2454876631
Directory /workspace/3.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/3.chip_tap_straps_testunlock0.3364494824
Short name T846
Test name
Test status
Simulation time 3748423657 ps
CPU time 357.58 seconds
Started Mar 24 03:47:01 PM PDT 24
Finished Mar 24 03:52:59 PM PDT 24
Peak memory 609540 kb
Host smart-1b352594-08ac-4d29-af77-017c6df60c9d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364494824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3364494824
Directory /workspace/3.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.564572310
Short name T498
Test name
Test status
Simulation time 3481711762 ps
CPU time 372.02 seconds
Started Mar 24 03:52:43 PM PDT 24
Finished Mar 24 03:58:56 PM PDT 24
Peak memory 636224 kb
Host smart-5dc85870-0d9f-4e94-a264-95ae84029dd1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564572310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s
w_alert_handler_lpg_sleep_mode_alerts.564572310
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.758268898
Short name T476
Test name
Test status
Simulation time 4192393988 ps
CPU time 385.83 seconds
Started Mar 24 03:51:37 PM PDT 24
Finished Mar 24 03:58:03 PM PDT 24
Peak memory 635940 kb
Host smart-c41d2814-fa77-4d00-9ca1-dd6b40c8d359
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758268898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s
w_alert_handler_lpg_sleep_mode_alerts.758268898
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_all_escalation_resets.2879011663
Short name T794
Test name
Test status
Simulation time 6094388588 ps
CPU time 641.79 seconds
Started Mar 24 03:51:52 PM PDT 24
Finished Mar 24 04:02:34 PM PDT 24
Peak memory 635076 kb
Host smart-bd934e69-bca5-4572-a7fa-5ccb527da771
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2879011663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2879011663
Directory /workspace/31.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.3961017387
Short name T489
Test name
Test status
Simulation time 5096804516 ps
CPU time 553.57 seconds
Started Mar 24 03:51:37 PM PDT 24
Finished Mar 24 04:00:51 PM PDT 24
Peak memory 636368 kb
Host smart-1643214d-c682-4319-b951-b9ad35daafd2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3961017387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3961017387
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909044307
Short name T929
Test name
Test status
Simulation time 3831163830 ps
CPU time 349.02 seconds
Started Mar 24 03:54:21 PM PDT 24
Finished Mar 24 04:00:10 PM PDT 24
Peak memory 609292 kb
Host smart-042837fc-5d48-43f8-af70-8f1f3172b1a5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909044307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1909044307
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278611887
Short name T433
Test name
Test status
Simulation time 3318324428 ps
CPU time 408.41 seconds
Started Mar 24 03:51:13 PM PDT 24
Finished Mar 24 03:58:02 PM PDT 24
Peak memory 635956 kb
Host smart-00cc6f3e-fcc2-4dc8-9c08-aad698da57e5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278611887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2278611887
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922313595
Short name T851
Test name
Test status
Simulation time 3709768680 ps
CPU time 466.23 seconds
Started Mar 24 03:52:29 PM PDT 24
Finished Mar 24 04:00:16 PM PDT 24
Peak memory 636040 kb
Host smart-2f01a15b-3a44-449a-828f-f053c56b3244
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922313595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1922313595
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.209240679
Short name T254
Test name
Test status
Simulation time 4471519080 ps
CPU time 456.71 seconds
Started Mar 24 03:54:25 PM PDT 24
Finished Mar 24 04:02:02 PM PDT 24
Peak memory 637552 kb
Host smart-6ea420ef-7ff6-4a06-ac69-80ddabb105ae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
209240679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.209240679
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703351525
Short name T427
Test name
Test status
Simulation time 4126476894 ps
CPU time 456.36 seconds
Started Mar 24 03:51:41 PM PDT 24
Finished Mar 24 03:59:18 PM PDT 24
Peak memory 636124 kb
Host smart-af16973f-a71d-49c3-8c85-01b0e46c9cf7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703351525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2703351525
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.1237995029
Short name T483
Test name
Test status
Simulation time 5162991216 ps
CPU time 658.47 seconds
Started Mar 24 03:51:58 PM PDT 24
Finished Mar 24 04:02:57 PM PDT 24
Peak memory 635244 kb
Host smart-1aca7918-f3dc-4da6-a2ca-9b3e377f7630
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1237995029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1237995029
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339653335
Short name T772
Test name
Test status
Simulation time 3633161164 ps
CPU time 493.17 seconds
Started Mar 24 03:51:56 PM PDT 24
Finished Mar 24 04:00:10 PM PDT 24
Peak memory 635912 kb
Host smart-df4b3a36-e574-4374-af84-5a0743b0e276
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339653335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2339653335
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.1495437546
Short name T748
Test name
Test status
Simulation time 5336525916 ps
CPU time 594.88 seconds
Started Mar 24 03:50:59 PM PDT 24
Finished Mar 24 04:00:54 PM PDT 24
Peak memory 636548 kb
Host smart-9d017f3c-dc2d-4b6a-913e-8c866545aa1a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1495437546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1495437546
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153488298
Short name T403
Test name
Test status
Simulation time 3528869700 ps
CPU time 417.37 seconds
Started Mar 24 03:48:14 PM PDT 24
Finished Mar 24 03:55:12 PM PDT 24
Peak memory 636052 kb
Host smart-185ec234-7ebf-41c8-ac6a-222754444771
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153488298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2153488298
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1018959935
Short name T666
Test name
Test status
Simulation time 7742973150 ps
CPU time 355.49 seconds
Started Mar 24 03:51:31 PM PDT 24
Finished Mar 24 03:57:27 PM PDT 24
Peak memory 599468 kb
Host smart-0e21609b-9cfb-485e-adae-3b6972e23740
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1018959935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1018959935
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1288727398
Short name T287
Test name
Test status
Simulation time 4716676700 ps
CPU time 631.88 seconds
Started Mar 24 03:48:17 PM PDT 24
Finished Mar 24 03:58:49 PM PDT 24
Peak memory 600420 kb
Host smart-78d7f62b-5266-4f5a-a5ed-e7d8eb0a23de
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1288727398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1288727398
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.154534998
Short name T569
Test name
Test status
Simulation time 12708250819 ps
CPU time 906.43 seconds
Started Mar 24 03:48:48 PM PDT 24
Finished Mar 24 04:03:55 PM PDT 24
Peak memory 612368 kb
Host smart-d92f7fc0-79bc-4438-be7c-e5de06e96d6a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154534998 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.154534998
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3220569614
Short name T836
Test name
Test status
Simulation time 14670289265 ps
CPU time 1817.97 seconds
Started Mar 24 03:47:52 PM PDT 24
Finished Mar 24 04:18:10 PM PDT 24
Peak memory 607176 kb
Host smart-0a5ed848-a2ed-4721-9afc-5d8af15edb27
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3220569614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3220569614
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1088244475
Short name T593
Test name
Test status
Simulation time 13351326052 ps
CPU time 1826.09 seconds
Started Mar 24 03:49:00 PM PDT 24
Finished Mar 24 04:19:27 PM PDT 24
Peak memory 607260 kb
Host smart-a881ba5f-f457-4cd2-b14e-e8385ca96370
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088244475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq.1088244475
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.259488423
Short name T583
Test name
Test status
Simulation time 22731183235 ps
CPU time 2242.42 seconds
Started Mar 24 03:49:20 PM PDT 24
Finished Mar 24 04:26:44 PM PDT 24
Peak memory 608184 kb
Host smart-11202a24-ecb0-4244-99ac-f1405976ad2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259488423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.259488423
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3970301110
Short name T244
Test name
Test status
Simulation time 5718059725 ps
CPU time 699.78 seconds
Started Mar 24 03:49:42 PM PDT 24
Finished Mar 24 04:01:23 PM PDT 24
Peak memory 608104 kb
Host smart-e372b2ee-6801-4caf-8771-321b11cff50c
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970301110 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3970301110
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.88347935
Short name T768
Test name
Test status
Simulation time 10818205775 ps
CPU time 975.61 seconds
Started Mar 24 03:47:39 PM PDT 24
Finished Mar 24 04:03:55 PM PDT 24
Peak memory 609508 kb
Host smart-0979023c-7bc2-4686-a8fa-8b1ab6fe877f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=88347935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.88347935
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.2152742008
Short name T715
Test name
Test status
Simulation time 2772504838 ps
CPU time 228.05 seconds
Started Mar 24 03:47:25 PM PDT 24
Finished Mar 24 03:51:14 PM PDT 24
Peak memory 609060 kb
Host smart-85dcef4e-3645-4228-9620-31fdb5d0332a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2152742008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2152742008
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/4.chip_tap_straps_rma.3382959530
Short name T878
Test name
Test status
Simulation time 3826874618 ps
CPU time 321.47 seconds
Started Mar 24 03:47:33 PM PDT 24
Finished Mar 24 03:52:55 PM PDT 24
Peak memory 617716 kb
Host smart-672e4106-3cc1-47f4-8f31-9595ea668bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382959530 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3382959530
Directory /workspace/4.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.1120228145
Short name T255
Test name
Test status
Simulation time 4768675150 ps
CPU time 464.46 seconds
Started Mar 24 03:52:36 PM PDT 24
Finished Mar 24 04:00:21 PM PDT 24
Peak memory 636332 kb
Host smart-31dc27e0-83c9-48a9-ab58-dc2666f630fd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1120228145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1120228145
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456362447
Short name T939
Test name
Test status
Simulation time 4120575708 ps
CPU time 315.62 seconds
Started Mar 24 03:53:27 PM PDT 24
Finished Mar 24 03:58:43 PM PDT 24
Peak memory 636372 kb
Host smart-b01b7fef-b445-441b-bfef-d55ad06cf940
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456362447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2456362447
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.3097593596
Short name T464
Test name
Test status
Simulation time 5162211996 ps
CPU time 378.52 seconds
Started Mar 24 03:53:19 PM PDT 24
Finished Mar 24 03:59:37 PM PDT 24
Peak memory 636572 kb
Host smart-3fdd8be4-e065-492f-804a-aa85e15273b2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3097593596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3097593596
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.1832246680
Short name T465
Test name
Test status
Simulation time 4804178664 ps
CPU time 501.66 seconds
Started Mar 24 03:53:19 PM PDT 24
Finished Mar 24 04:01:41 PM PDT 24
Peak memory 636720 kb
Host smart-e147aa1c-715c-45b1-af0a-05b07d0d834a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1832246680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1832246680
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171776605
Short name T514
Test name
Test status
Simulation time 3730256688 ps
CPU time 258.24 seconds
Started Mar 24 03:54:25 PM PDT 24
Finished Mar 24 03:58:44 PM PDT 24
Peak memory 635864 kb
Host smart-d2a10433-70b8-4ca7-a1b9-14f46917156d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171776605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1171776605
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.543322551
Short name T441
Test name
Test status
Simulation time 3933113396 ps
CPU time 373.71 seconds
Started Mar 24 03:52:19 PM PDT 24
Finished Mar 24 03:58:33 PM PDT 24
Peak memory 635988 kb
Host smart-a4660d10-0d51-48e3-bdb3-b316506ade35
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543322551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s
w_alert_handler_lpg_sleep_mode_alerts.543322551
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.1108964777
Short name T480
Test name
Test status
Simulation time 5971540624 ps
CPU time 728.39 seconds
Started Mar 24 03:52:03 PM PDT 24
Finished Mar 24 04:04:12 PM PDT 24
Peak memory 635632 kb
Host smart-87d75c46-6f7e-445e-9523-e83c3cb16e3d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1108964777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1108964777
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983972182
Short name T385
Test name
Test status
Simulation time 3829590236 ps
CPU time 395.05 seconds
Started Mar 24 03:53:14 PM PDT 24
Finished Mar 24 03:59:49 PM PDT 24
Peak memory 635920 kb
Host smart-4ca9c616-534f-40bd-afa5-d41493ddd618
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983972182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2983972182
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.844769526
Short name T502
Test name
Test status
Simulation time 5272554608 ps
CPU time 519.49 seconds
Started Mar 24 03:53:00 PM PDT 24
Finished Mar 24 04:01:39 PM PDT 24
Peak memory 636256 kb
Host smart-42351554-a49e-4406-99ae-70bfcd29c32f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
844769526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.844769526
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.795583486
Short name T497
Test name
Test status
Simulation time 3585376244 ps
CPU time 357.79 seconds
Started Mar 24 03:52:32 PM PDT 24
Finished Mar 24 03:58:30 PM PDT 24
Peak memory 636084 kb
Host smart-ed6b15a8-c6a2-4260-a1cb-d3895f157b37
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795583486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s
w_alert_handler_lpg_sleep_mode_alerts.795583486
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.3620221114
Short name T855
Test name
Test status
Simulation time 5509634534 ps
CPU time 612.64 seconds
Started Mar 24 03:52:17 PM PDT 24
Finished Mar 24 04:02:29 PM PDT 24
Peak memory 636244 kb
Host smart-0f59266b-be02-42a4-b5b5-af2989b9c244
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3620221114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3620221114
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411929277
Short name T396
Test name
Test status
Simulation time 3601918388 ps
CPU time 633.69 seconds
Started Mar 24 03:49:37 PM PDT 24
Finished Mar 24 04:00:11 PM PDT 24
Peak memory 636440 kb
Host smart-4e698e0e-a95e-42ba-a1ec-5c7f87bc0206
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411929277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1411929277
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.226942140
Short name T349
Test name
Test status
Simulation time 5715204100 ps
CPU time 668.09 seconds
Started Mar 24 03:50:07 PM PDT 24
Finished Mar 24 04:01:16 PM PDT 24
Peak memory 635208 kb
Host smart-7fa5ba59-9323-4f5a-a9a4-cadcf75b7728
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
226942140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.226942140
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2175244304
Short name T278
Test name
Test status
Simulation time 5985579764 ps
CPU time 577.25 seconds
Started Mar 24 03:48:52 PM PDT 24
Finished Mar 24 03:58:30 PM PDT 24
Peak memory 599988 kb
Host smart-0c3e30de-6d1e-4a6c-841a-6119cb0e33f6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2175244304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2175244304
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2576330691
Short name T812
Test name
Test status
Simulation time 9471437412 ps
CPU time 1010.36 seconds
Started Mar 24 03:49:02 PM PDT 24
Finished Mar 24 04:05:54 PM PDT 24
Peak memory 612420 kb
Host smart-f7400107-7c2e-45fc-a928-5b8d919ac197
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576330691 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2576330691
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.312544140
Short name T467
Test name
Test status
Simulation time 3512145020 ps
CPU time 308.98 seconds
Started Mar 24 03:52:58 PM PDT 24
Finished Mar 24 03:58:07 PM PDT 24
Peak memory 636316 kb
Host smart-31a9480a-9d7c-44bc-9f27-afcf108bab9b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312544140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s
w_alert_handler_lpg_sleep_mode_alerts.312544140
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.729062
Short name T474
Test name
Test status
Simulation time 3868299672 ps
CPU time 336.82 seconds
Started Mar 24 03:52:31 PM PDT 24
Finished Mar 24 03:58:08 PM PDT 24
Peak memory 635880 kb
Host smart-260ca4d1-7eac-4433-92f5-8ce17d211897
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es
calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_a
lert_handler_lpg_sleep_mode_alerts.729062
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.2617965449
Short name T730
Test name
Test status
Simulation time 4650610980 ps
CPU time 515.78 seconds
Started Mar 24 03:52:05 PM PDT 24
Finished Mar 24 04:00:41 PM PDT 24
Peak memory 635192 kb
Host smart-3fb73a65-71ff-4d61-9dad-aa2d50e63e3e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2617965449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.2617965449
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.3734110361
Short name T513
Test name
Test status
Simulation time 5162655072 ps
CPU time 620.35 seconds
Started Mar 24 03:53:21 PM PDT 24
Finished Mar 24 04:03:41 PM PDT 24
Peak memory 635352 kb
Host smart-a0548990-2980-4e1a-bf69-85e9b4d2deff
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3734110361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3734110361
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238282058
Short name T488
Test name
Test status
Simulation time 4073106600 ps
CPU time 397.42 seconds
Started Mar 24 03:53:21 PM PDT 24
Finished Mar 24 03:59:58 PM PDT 24
Peak memory 635860 kb
Host smart-7da8d552-1fb5-4a22-bea4-44ea28530e20
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238282058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1238282058
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.1882260089
Short name T511
Test name
Test status
Simulation time 4426397944 ps
CPU time 534.66 seconds
Started Mar 24 03:53:11 PM PDT 24
Finished Mar 24 04:02:06 PM PDT 24
Peak memory 635484 kb
Host smart-d0ff060e-fa33-4622-8b87-ab37e915956c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1882260089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1882260089
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.552616659
Short name T295
Test name
Test status
Simulation time 4993594710 ps
CPU time 590.55 seconds
Started Mar 24 03:55:09 PM PDT 24
Finished Mar 24 04:05:00 PM PDT 24
Peak memory 636364 kb
Host smart-d7ca1d61-9374-47f7-b84c-de1f334e1383
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
552616659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.552616659
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.250760579
Short name T824
Test name
Test status
Simulation time 2949297340 ps
CPU time 310.72 seconds
Started Mar 24 03:54:05 PM PDT 24
Finished Mar 24 03:59:16 PM PDT 24
Peak memory 635868 kb
Host smart-8ccbb22a-7c01-48ed-92b1-ca059322ab26
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250760579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s
w_alert_handler_lpg_sleep_mode_alerts.250760579
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835180601
Short name T351
Test name
Test status
Simulation time 3706420096 ps
CPU time 448.48 seconds
Started Mar 24 03:57:45 PM PDT 24
Finished Mar 24 04:05:14 PM PDT 24
Peak memory 635848 kb
Host smart-a4409ca5-fe76-4a6e-a6b2-e10a1c03869c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835180601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3835180601
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1644380853
Short name T475
Test name
Test status
Simulation time 3379467828 ps
CPU time 378.94 seconds
Started Mar 24 03:54:25 PM PDT 24
Finished Mar 24 04:00:44 PM PDT 24
Peak memory 636096 kb
Host smart-1025627b-43aa-4e2b-9b94-910ec3cb5bc1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644380853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1644380853
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844070610
Short name T443
Test name
Test status
Simulation time 4038602910 ps
CPU time 373.86 seconds
Started Mar 24 03:50:09 PM PDT 24
Finished Mar 24 03:56:23 PM PDT 24
Peak memory 635896 kb
Host smart-0e3b9574-d65b-4d2e-adef-19bd2a8fa67c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844070610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3844070610
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.1645594752
Short name T458
Test name
Test status
Simulation time 6073195770 ps
CPU time 837.2 seconds
Started Mar 24 03:50:00 PM PDT 24
Finished Mar 24 04:03:58 PM PDT 24
Peak memory 636768 kb
Host smart-6cd10d55-cdd6-43d8-a0ff-c05361247396
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1645594752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1645594752
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1693026314
Short name T542
Test name
Test status
Simulation time 10395044216 ps
CPU time 896.05 seconds
Started Mar 24 03:49:34 PM PDT 24
Finished Mar 24 04:04:31 PM PDT 24
Peak memory 612580 kb
Host smart-febcf575-f119-48b0-a1ee-3ba1a1edbb80
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693026314 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1693026314
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3016936737
Short name T643
Test name
Test status
Simulation time 5087053033 ps
CPU time 720.21 seconds
Started Mar 24 03:49:30 PM PDT 24
Finished Mar 24 04:01:31 PM PDT 24
Peak memory 607260 kb
Host smart-73e1dcdf-09dc-49d3-a631-f77393be6917
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3016936737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3016936737
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.439895999
Short name T576
Test name
Test status
Simulation time 3311037570 ps
CPU time 291.46 seconds
Started Mar 24 03:54:46 PM PDT 24
Finished Mar 24 03:59:37 PM PDT 24
Peak memory 636148 kb
Host smart-a1f0e54e-eb87-4e3d-b45c-759363164f8c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439895999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s
w_alert_handler_lpg_sleep_mode_alerts.439895999
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.88976671
Short name T728
Test name
Test status
Simulation time 5995886898 ps
CPU time 570.87 seconds
Started Mar 24 03:53:55 PM PDT 24
Finished Mar 24 04:03:27 PM PDT 24
Peak memory 635324 kb
Host smart-872fae50-d629-4efe-add9-17ed02bc29f8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
88976671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.88976671
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3466036698
Short name T492
Test name
Test status
Simulation time 4049976338 ps
CPU time 328 seconds
Started Mar 24 03:54:01 PM PDT 24
Finished Mar 24 03:59:29 PM PDT 24
Peak memory 635964 kb
Host smart-b478419f-37b1-4a36-9a54-69ec77187a63
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466036698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3466036698
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.4067779976
Short name T446
Test name
Test status
Simulation time 6150245168 ps
CPU time 550.27 seconds
Started Mar 24 03:54:35 PM PDT 24
Finished Mar 24 04:03:46 PM PDT 24
Peak memory 636708 kb
Host smart-ff710f8c-43cc-4ef6-978e-b424259510f1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4067779976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.4067779976
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.2406502236
Short name T457
Test name
Test status
Simulation time 4690999368 ps
CPU time 663.67 seconds
Started Mar 24 03:56:36 PM PDT 24
Finished Mar 24 04:07:40 PM PDT 24
Peak memory 636596 kb
Host smart-24c35e37-2252-4fe6-8929-af1bd3b43478
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2406502236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2406502236
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909689702
Short name T508
Test name
Test status
Simulation time 3031347688 ps
CPU time 362.84 seconds
Started Mar 24 03:53:57 PM PDT 24
Finished Mar 24 04:00:01 PM PDT 24
Peak memory 635844 kb
Host smart-81437048-61e0-4cb3-a0e3-b7587561e663
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909689702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1909689702
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/63.chip_sw_all_escalation_resets.1457364958
Short name T506
Test name
Test status
Simulation time 5053406048 ps
CPU time 530.83 seconds
Started Mar 24 03:57:16 PM PDT 24
Finished Mar 24 04:06:07 PM PDT 24
Peak memory 635216 kb
Host smart-21701fc0-d839-4876-9d71-1808033ff950
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1457364958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1457364958
Directory /workspace/63.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927920069
Short name T274
Test name
Test status
Simulation time 3866608200 ps
CPU time 351.79 seconds
Started Mar 24 03:54:38 PM PDT 24
Finished Mar 24 04:00:30 PM PDT 24
Peak memory 635928 kb
Host smart-486f0587-821d-4f14-a10c-f45c24921528
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927920069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1927920069
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.4249483138
Short name T918
Test name
Test status
Simulation time 5360628678 ps
CPU time 633.55 seconds
Started Mar 24 03:53:50 PM PDT 24
Finished Mar 24 04:04:24 PM PDT 24
Peak memory 635204 kb
Host smart-caa923e6-f861-44c8-8daa-80079525515f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4249483138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.4249483138
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936172292
Short name T360
Test name
Test status
Simulation time 3636128572 ps
CPU time 359.8 seconds
Started Mar 24 03:57:54 PM PDT 24
Finished Mar 24 04:03:54 PM PDT 24
Peak memory 636048 kb
Host smart-5437a382-3431-4987-adc6-b06c9d8f96cd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936172292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2936172292
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.2967099679
Short name T353
Test name
Test status
Simulation time 5151970360 ps
CPU time 530 seconds
Started Mar 24 03:54:00 PM PDT 24
Finished Mar 24 04:02:51 PM PDT 24
Peak memory 636232 kb
Host smart-7fdc489a-ae51-431e-bc67-4fd57452b752
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2967099679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2967099679
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287674767
Short name T879
Test name
Test status
Simulation time 3637393976 ps
CPU time 408.64 seconds
Started Mar 24 03:56:05 PM PDT 24
Finished Mar 24 04:02:54 PM PDT 24
Peak memory 636244 kb
Host smart-26047b88-8452-466e-b068-3038e3c65cef
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287674767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4287674767
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.3390550323
Short name T229
Test name
Test status
Simulation time 4265903866 ps
CPU time 553.43 seconds
Started Mar 24 03:59:32 PM PDT 24
Finished Mar 24 04:08:46 PM PDT 24
Peak memory 635172 kb
Host smart-bdce3f07-a8bb-4e84-9170-53ea979c7ac3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3390550323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3390550323
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227074138
Short name T426
Test name
Test status
Simulation time 4147413892 ps
CPU time 459.17 seconds
Started Mar 24 03:54:22 PM PDT 24
Finished Mar 24 04:02:02 PM PDT 24
Peak memory 635964 kb
Host smart-beb24db5-ba17-48b7-bbbf-ae9b5118fe6d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227074138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3227074138
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.3445164491
Short name T191
Test name
Test status
Simulation time 4558427260 ps
CPU time 470.01 seconds
Started Mar 24 03:53:49 PM PDT 24
Finished Mar 24 04:01:40 PM PDT 24
Peak memory 607492 kb
Host smart-e4f454bd-8866-4cc5-b82d-1c9595f40e96
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3445164491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3445164491
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2891109239
Short name T778
Test name
Test status
Simulation time 3866634908 ps
CPU time 423.05 seconds
Started Mar 24 04:00:14 PM PDT 24
Finished Mar 24 04:07:17 PM PDT 24
Peak memory 637228 kb
Host smart-a89eae0b-cf89-4d4a-bb7c-c5987dc20ec8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891109239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2891109239
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.919164317
Short name T919
Test name
Test status
Simulation time 5434013776 ps
CPU time 514.79 seconds
Started Mar 24 03:55:53 PM PDT 24
Finished Mar 24 04:04:29 PM PDT 24
Peak memory 635408 kb
Host smart-d8e1b6ef-904b-4fb1-a3f1-541ddb66c949
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
919164317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.919164317
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465663304
Short name T499
Test name
Test status
Simulation time 3492112412 ps
CPU time 366.79 seconds
Started Mar 24 03:54:34 PM PDT 24
Finished Mar 24 04:00:41 PM PDT 24
Peak memory 636248 kb
Host smart-ea344bdd-a9e0-4f43-8dd8-6c2c18c279b7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465663304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1465663304
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.2333551830
Short name T330
Test name
Test status
Simulation time 4540870934 ps
CPU time 561.89 seconds
Started Mar 24 03:54:30 PM PDT 24
Finished Mar 24 04:03:52 PM PDT 24
Peak memory 635312 kb
Host smart-7beaa6f1-0e53-461b-889f-949bb7ff2015
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2333551830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2333551830
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.2222622376
Short name T940
Test name
Test status
Simulation time 4943428300 ps
CPU time 565.26 seconds
Started Mar 24 03:50:05 PM PDT 24
Finished Mar 24 03:59:30 PM PDT 24
Peak memory 636468 kb
Host smart-ad050154-d707-4d74-97a4-7bc0e027eef8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2222622376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2222622376
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2280706052
Short name T687
Test name
Test status
Simulation time 7115141715 ps
CPU time 624.93 seconds
Started Mar 24 03:49:08 PM PDT 24
Finished Mar 24 03:59:34 PM PDT 24
Peak memory 612284 kb
Host smart-3aed2ee4-1fa8-40ad-8f56-5764673f3806
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280706052 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2280706052
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3254916715
Short name T610
Test name
Test status
Simulation time 12737962083 ps
CPU time 1936.11 seconds
Started Mar 24 03:48:45 PM PDT 24
Finished Mar 24 04:21:02 PM PDT 24
Peak memory 607236 kb
Host smart-56647694-09c4-4a51-947e-00fa4ed44c89
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3254916715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3254916715
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/70.chip_sw_all_escalation_resets.1807644219
Short name T486
Test name
Test status
Simulation time 6404253908 ps
CPU time 588.21 seconds
Started Mar 24 03:55:20 PM PDT 24
Finished Mar 24 04:05:08 PM PDT 24
Peak memory 636128 kb
Host smart-86b6fcc4-96ac-4e49-b267-3021874b8417
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1807644219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1807644219
Directory /workspace/70.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190030168
Short name T183
Test name
Test status
Simulation time 3575030560 ps
CPU time 368.51 seconds
Started Mar 24 03:55:33 PM PDT 24
Finished Mar 24 04:01:42 PM PDT 24
Peak memory 636028 kb
Host smart-0b656e32-12f4-4569-96a5-f5051b4c5564
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190030168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1190030168
Directory /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.2082366115
Short name T429
Test name
Test status
Simulation time 4704722468 ps
CPU time 747.88 seconds
Started Mar 24 03:56:51 PM PDT 24
Finished Mar 24 04:09:20 PM PDT 24
Peak memory 636408 kb
Host smart-4e06282b-f40e-4bde-a90d-4869077cb0b9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2082366115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2082366115
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277978776
Short name T397
Test name
Test status
Simulation time 3773663984 ps
CPU time 444.24 seconds
Started Mar 24 03:56:28 PM PDT 24
Finished Mar 24 04:03:52 PM PDT 24
Peak memory 636272 kb
Host smart-c5692c49-2bbe-441d-bd17-edf2dd14ae6b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277978776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1277978776
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.328635338
Short name T471
Test name
Test status
Simulation time 3960091428 ps
CPU time 317.27 seconds
Started Mar 24 03:57:26 PM PDT 24
Finished Mar 24 04:02:43 PM PDT 24
Peak memory 636048 kb
Host smart-29b08182-06f5-4084-9c46-fe4cac63c392
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328635338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_s
w_alert_handler_lpg_sleep_mode_alerts.328635338
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.2211852441
Short name T873
Test name
Test status
Simulation time 4652581000 ps
CPU time 428.2 seconds
Started Mar 24 03:54:47 PM PDT 24
Finished Mar 24 04:01:55 PM PDT 24
Peak memory 636436 kb
Host smart-8e4722f8-16d2-4c68-8c6f-7210f6c6610f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2211852441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2211852441
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.2201703078
Short name T803
Test name
Test status
Simulation time 5025245548 ps
CPU time 678.75 seconds
Started Mar 24 03:54:23 PM PDT 24
Finished Mar 24 04:05:43 PM PDT 24
Peak memory 635296 kb
Host smart-df852328-6c99-4e61-933c-4ed7e56ddd89
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2201703078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2201703078
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003162666
Short name T180
Test name
Test status
Simulation time 3489907780 ps
CPU time 355.07 seconds
Started Mar 24 04:02:01 PM PDT 24
Finished Mar 24 04:07:56 PM PDT 24
Peak memory 635992 kb
Host smart-3dee2466-33e9-4973-971d-b24d9f40afcf
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003162666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1003162666
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581722623
Short name T125
Test name
Test status
Simulation time 3788589648 ps
CPU time 382.31 seconds
Started Mar 24 03:58:32 PM PDT 24
Finished Mar 24 04:04:55 PM PDT 24
Peak memory 636500 kb
Host smart-e2a962b2-0746-4d12-8f51-d3a50f1d0683
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581722623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2581722623
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.2994869821
Short name T479
Test name
Test status
Simulation time 5069547476 ps
CPU time 508.12 seconds
Started Mar 24 03:56:40 PM PDT 24
Finished Mar 24 04:05:09 PM PDT 24
Peak memory 636580 kb
Host smart-67d12bc9-6d10-425a-8ba3-6f18c9810a02
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2994869821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2994869821
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229062145
Short name T292
Test name
Test status
Simulation time 3241512876 ps
CPU time 361.64 seconds
Started Mar 24 04:01:09 PM PDT 24
Finished Mar 24 04:07:11 PM PDT 24
Peak memory 636004 kb
Host smart-190611b3-2e50-4294-ae1e-4dfb4d286e28
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229062145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4229062145
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_all_escalation_resets.4271839426
Short name T436
Test name
Test status
Simulation time 5458200680 ps
CPU time 490.58 seconds
Started Mar 24 03:56:26 PM PDT 24
Finished Mar 24 04:04:37 PM PDT 24
Peak memory 636124 kb
Host smart-b8e564ff-2d0f-47eb-b794-6cf95e4dcb65
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4271839426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.4271839426
Directory /workspace/77.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3534763769
Short name T505
Test name
Test status
Simulation time 4226684160 ps
CPU time 312.16 seconds
Started Mar 24 03:55:43 PM PDT 24
Finished Mar 24 04:00:55 PM PDT 24
Peak memory 635880 kb
Host smart-2e633b0f-a3ad-4a41-a109-e305fe3868d5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534763769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3534763769
Directory /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/78.chip_sw_all_escalation_resets.2278982972
Short name T425
Test name
Test status
Simulation time 5512940594 ps
CPU time 517.96 seconds
Started Mar 24 04:01:13 PM PDT 24
Finished Mar 24 04:09:52 PM PDT 24
Peak memory 635224 kb
Host smart-0444bd1a-d3bb-4c91-ac15-3ee9cb0ac071
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2278982972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.2278982972
Directory /workspace/78.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783276926
Short name T324
Test name
Test status
Simulation time 3337728028 ps
CPU time 467.72 seconds
Started Mar 24 03:55:30 PM PDT 24
Finished Mar 24 04:03:18 PM PDT 24
Peak memory 635956 kb
Host smart-057952d0-4bee-4d1a-9494-60cca4c00869
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783276926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2783276926
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/79.chip_sw_all_escalation_resets.3610843298
Short name T886
Test name
Test status
Simulation time 4879534704 ps
CPU time 470.58 seconds
Started Mar 24 03:54:46 PM PDT 24
Finished Mar 24 04:02:37 PM PDT 24
Peak memory 635340 kb
Host smart-e9c2bd7d-ef08-4bce-9c42-3c22ffb9a63d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3610843298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3610843298
Directory /workspace/79.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1306132700
Short name T453
Test name
Test status
Simulation time 3497072662 ps
CPU time 358.27 seconds
Started Mar 24 03:49:05 PM PDT 24
Finished Mar 24 03:55:04 PM PDT 24
Peak memory 635972 kb
Host smart-adc59127-20b8-44ae-ae1f-d3f98592e8c7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306132700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1306132700
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.1109701582
Short name T53
Test name
Test status
Simulation time 5390122570 ps
CPU time 617.16 seconds
Started Mar 24 03:49:16 PM PDT 24
Finished Mar 24 03:59:34 PM PDT 24
Peak memory 636184 kb
Host smart-004a6955-371d-4e63-bb91-4ed0f424bf75
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1109701582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1109701582
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3697153127
Short name T219
Test name
Test status
Simulation time 5708066199 ps
CPU time 526.13 seconds
Started Mar 24 03:48:55 PM PDT 24
Finished Mar 24 03:57:41 PM PDT 24
Peak memory 612532 kb
Host smart-4bc52021-77a9-4a2d-9781-093f5fd62872
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697153127 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3697153127
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.358405035
Short name T926
Test name
Test status
Simulation time 3859018205 ps
CPU time 584.02 seconds
Started Mar 24 03:50:37 PM PDT 24
Finished Mar 24 04:00:21 PM PDT 24
Peak memory 607340 kb
Host smart-49e240a2-8d5d-49f1-9813-e552b644f159
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=358405035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.358405035
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.2549310185
Short name T315
Test name
Test status
Simulation time 5544797952 ps
CPU time 522.44 seconds
Started Mar 24 03:55:20 PM PDT 24
Finished Mar 24 04:04:03 PM PDT 24
Peak memory 635236 kb
Host smart-16ff89e1-cd01-4ef0-9db4-4df076aebf8c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2549310185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2549310185
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471524846
Short name T226
Test name
Test status
Simulation time 3040103666 ps
CPU time 340.68 seconds
Started Mar 24 03:55:08 PM PDT 24
Finished Mar 24 04:00:49 PM PDT 24
Peak memory 635984 kb
Host smart-7c1baab2-d7a3-4b66-a975-7b29668f0ddb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471524846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1471524846
Directory /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.3927807345
Short name T398
Test name
Test status
Simulation time 5150170920 ps
CPU time 455.38 seconds
Started Mar 24 03:54:28 PM PDT 24
Finished Mar 24 04:02:04 PM PDT 24
Peak memory 636656 kb
Host smart-a83c3d94-a9f7-41f1-9449-3e5a150f9a60
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3927807345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3927807345
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.755829238
Short name T350
Test name
Test status
Simulation time 4226699146 ps
CPU time 315.48 seconds
Started Mar 24 04:02:08 PM PDT 24
Finished Mar 24 04:07:23 PM PDT 24
Peak memory 636004 kb
Host smart-d8e56466-3e20-4a8d-9835-f753cd8eb1cf
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755829238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s
w_alert_handler_lpg_sleep_mode_alerts.755829238
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.2524446516
Short name T683
Test name
Test status
Simulation time 4614238500 ps
CPU time 489.94 seconds
Started Mar 24 03:55:29 PM PDT 24
Finished Mar 24 04:03:39 PM PDT 24
Peak memory 635532 kb
Host smart-45d18f84-b6c9-43dd-b5e9-c362b014f3f0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2524446516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2524446516
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601339788
Short name T507
Test name
Test status
Simulation time 3455465842 ps
CPU time 423.78 seconds
Started Mar 24 03:56:00 PM PDT 24
Finished Mar 24 04:03:04 PM PDT 24
Peak memory 635888 kb
Host smart-a84a1ad7-0dec-450b-a33d-6fdc87b14a29
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601339788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2601339788
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4205105010
Short name T334
Test name
Test status
Simulation time 3919952920 ps
CPU time 331.75 seconds
Started Mar 24 03:56:00 PM PDT 24
Finished Mar 24 04:01:32 PM PDT 24
Peak memory 636156 kb
Host smart-dd96593e-cd33-4518-9e5b-7d08e116fe2e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205105010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4205105010
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.585412894
Short name T469
Test name
Test status
Simulation time 5461594224 ps
CPU time 449.59 seconds
Started Mar 24 03:56:40 PM PDT 24
Finished Mar 24 04:04:11 PM PDT 24
Peak memory 635416 kb
Host smart-557d0afe-538b-4a4b-845b-ead2203c8bae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
585412894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.585412894
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.381618123
Short name T510
Test name
Test status
Simulation time 5935567774 ps
CPU time 554.53 seconds
Started Mar 24 03:55:59 PM PDT 24
Finished Mar 24 04:05:14 PM PDT 24
Peak memory 635256 kb
Host smart-4327f52e-6a9e-48a8-8b33-4eb56ea01505
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
381618123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.381618123
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.472383791
Short name T379
Test name
Test status
Simulation time 3545061822 ps
CPU time 363.47 seconds
Started Mar 24 03:56:04 PM PDT 24
Finished Mar 24 04:02:08 PM PDT 24
Peak memory 636188 kb
Host smart-f2207e6a-72b9-435e-b93b-07881058a6f0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472383791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s
w_alert_handler_lpg_sleep_mode_alerts.472383791
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002534396
Short name T515
Test name
Test status
Simulation time 3629994600 ps
CPU time 394.3 seconds
Started Mar 24 03:56:17 PM PDT 24
Finished Mar 24 04:02:51 PM PDT 24
Peak memory 636036 kb
Host smart-18e36efc-dfc7-4cc3-88e2-760a043e32a9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002534396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4002534396
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/88.chip_sw_all_escalation_resets.2377672740
Short name T422
Test name
Test status
Simulation time 5585818628 ps
CPU time 590.45 seconds
Started Mar 24 03:56:13 PM PDT 24
Finished Mar 24 04:06:04 PM PDT 24
Peak memory 635200 kb
Host smart-e547c52e-a386-45a6-9fd7-067263a2e46d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2377672740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2377672740
Directory /workspace/88.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931864184
Short name T500
Test name
Test status
Simulation time 4392056840 ps
CPU time 358.63 seconds
Started Mar 24 03:56:41 PM PDT 24
Finished Mar 24 04:02:41 PM PDT 24
Peak memory 636644 kb
Host smart-85278aaa-1d9d-41cb-9a44-b36cebfe1643
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931864184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1931864184
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.3045046473
Short name T833
Test name
Test status
Simulation time 5098232300 ps
CPU time 558.75 seconds
Started Mar 24 03:57:01 PM PDT 24
Finished Mar 24 04:06:20 PM PDT 24
Peak memory 635308 kb
Host smart-7a6f2f13-de0a-457c-b5cc-c7306e7383c1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3045046473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3045046473
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4277720702
Short name T286
Test name
Test status
Simulation time 4107802328 ps
CPU time 404.76 seconds
Started Mar 24 03:50:28 PM PDT 24
Finished Mar 24 03:57:13 PM PDT 24
Peak memory 635932 kb
Host smart-258aaceb-4fe8-4af5-9283-49e47e392fa3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277720702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4277720702
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.3900881426
Short name T517
Test name
Test status
Simulation time 5970242564 ps
CPU time 812.87 seconds
Started Mar 24 03:48:54 PM PDT 24
Finished Mar 24 04:02:27 PM PDT 24
Peak memory 636276 kb
Host smart-e183439d-91f6-4fba-bc41-640ae3d46baf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3900881426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3900881426
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1392900553
Short name T41
Test name
Test status
Simulation time 13036190621 ps
CPU time 749.79 seconds
Started Mar 24 03:50:28 PM PDT 24
Finished Mar 24 04:02:58 PM PDT 24
Peak memory 612284 kb
Host smart-7ffd2200-4494-44ed-8868-1ab3ba5f7ca9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392900553 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1392900553
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.4044203807
Short name T424
Test name
Test status
Simulation time 4053286136 ps
CPU time 470.71 seconds
Started Mar 24 03:56:41 PM PDT 24
Finished Mar 24 04:04:32 PM PDT 24
Peak memory 635972 kb
Host smart-18827d89-86ec-47cd-80aa-0e723028cf4c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4044203807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4044203807
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.981860142
Short name T185
Test name
Test status
Simulation time 5564398424 ps
CPU time 759.67 seconds
Started Mar 24 03:56:26 PM PDT 24
Finished Mar 24 04:09:06 PM PDT 24
Peak memory 607488 kb
Host smart-2b79e48a-b325-42f0-88e4-eb47d0a6fc34
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
981860142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.981860142
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.1162816563
Short name T736
Test name
Test status
Simulation time 5563926768 ps
CPU time 490.66 seconds
Started Mar 24 03:57:02 PM PDT 24
Finished Mar 24 04:05:13 PM PDT 24
Peak memory 607472 kb
Host smart-7dc503b5-6bc7-4060-8bd9-bfe26f0aeacd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1162816563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1162816563
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.3399008579
Short name T944
Test name
Test status
Simulation time 4396198364 ps
CPU time 472.71 seconds
Started Mar 24 03:56:12 PM PDT 24
Finished Mar 24 04:04:05 PM PDT 24
Peak memory 636240 kb
Host smart-6643355c-e175-4720-acdd-a337e523c298
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3399008579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3399008579
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.3179799400
Short name T259
Test name
Test status
Simulation time 6357001792 ps
CPU time 827.53 seconds
Started Mar 24 03:57:01 PM PDT 24
Finished Mar 24 04:10:49 PM PDT 24
Peak memory 636256 kb
Host smart-a51e1d5c-8972-4459-834d-8984d38a8697
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3179799400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3179799400
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.544977679
Short name T946
Test name
Test status
Simulation time 4922084510 ps
CPU time 307.16 seconds
Started Mar 24 03:12:25 PM PDT 24
Finished Mar 24 03:17:32 PM PDT 24
Peak memory 637540 kb
Host smart-b4804861-5660-4e41-9177-1c519d2eba9a
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544977679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 1.chip_padctrl_attributes.544977679
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2942050370
Short name T27
Test name
Test status
Simulation time 4501824868 ps
CPU time 328.82 seconds
Started Mar 24 03:12:22 PM PDT 24
Finished Mar 24 03:17:51 PM PDT 24
Peak memory 637548 kb
Host smart-b01f6833-34af-46bb-bd5c-2d8596839013
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942050370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.2942050370
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4245583464
Short name T949
Test name
Test status
Simulation time 5364260376 ps
CPU time 272.3 seconds
Started Mar 24 03:12:24 PM PDT 24
Finished Mar 24 03:16:56 PM PDT 24
Peak memory 636704 kb
Host smart-e39f7c85-7a36-41d4-a688-5f1213b78976
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245583464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.4245583464
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.416558801
Short name T419
Test name
Test status
Simulation time 4209247538 ps
CPU time 182.93 seconds
Started Mar 24 03:12:25 PM PDT 24
Finished Mar 24 03:15:28 PM PDT 24
Peak memory 637572 kb
Host smart-de6e7b67-13f7-4507-9f5e-9bd36b4f6958
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416558801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 5.chip_padctrl_attributes.416558801
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3897033507
Short name T29
Test name
Test status
Simulation time 4701275016 ps
CPU time 353.13 seconds
Started Mar 24 03:12:24 PM PDT 24
Finished Mar 24 03:18:17 PM PDT 24
Peak memory 637608 kb
Host smart-206eba37-943b-4487-9a21-27bb07d17f85
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897033507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 6.chip_padctrl_attributes.3897033507
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1337577864
Short name T948
Test name
Test status
Simulation time 4844723098 ps
CPU time 421.45 seconds
Started Mar 24 03:12:27 PM PDT 24
Finished Mar 24 03:19:29 PM PDT 24
Peak memory 637600 kb
Host smart-c1b5d818-e13b-4b86-9943-64ee00c625b3
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337577864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 7.chip_padctrl_attributes.1337577864
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2468304837
Short name T420
Test name
Test status
Simulation time 4077925984 ps
CPU time 235.23 seconds
Started Mar 24 03:12:26 PM PDT 24
Finished Mar 24 03:16:22 PM PDT 24
Peak memory 637568 kb
Host smart-355580fe-c17d-4aaf-aea5-6d8138c4c64e
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468304837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 8.chip_padctrl_attributes.2468304837
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3120781847
Short name T33
Test name
Test status
Simulation time 3661062240 ps
CPU time 238.36 seconds
Started Mar 24 03:12:26 PM PDT 24
Finished Mar 24 03:16:24 PM PDT 24
Peak memory 637616 kb
Host smart-a1efa225-09db-4f34-9e7b-ad7ecd2f4925
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120781847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 9.chip_padctrl_attributes.3120781847
Directory /workspace/9.chip_padctrl_attributes/latest
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