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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_wkup_detector_en_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
41.67 50.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.24 93.33 63.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.45 90.91 90.91 100.00 100.00 u_wkup_detector_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 100.00 81.82 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_detector_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 100.00 81.82 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_detector_4_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
41.67 50.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.79 93.33 81.82 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.45 90.91 90.91 100.00 100.00 u_wkup_detector_5_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_6_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
41.67 50.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.24 93.33 63.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.45 90.91 90.91 100.00 100.00 u_wkup_detector_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 100.00 81.82 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_detector_cnt_th_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_4_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_5_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_6_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.67 0.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 80.00 27.27 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.45 45.45 36.36 50.00 50.00 u_wkup_detector_cnt_th_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.50 88.00 72.09 73.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.33 93.88 69.39 86.05 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_wkup_cause_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT53
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT53
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT51
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT51
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT55
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT55
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT48,T49,T50
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT48,T49,T50
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN10000
CONT_ASSIGN284100.00
CONT_ASSIGN285100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 0 1
285 0 1
300 unreachable


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504488.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS1406583.33
ALWAYS15610990.00
CONT_ASSIGN18411100.00
ALWAYS188191789.47
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 0 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 0 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 0 1
212 0 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb
TotalCoveredPercent
Conditions433172.09
Logical433172.09
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT15,T56,T52
11CoveredT15,T25,T26

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T25,T26

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT15,T25,T26
10Not Covered
11Not Covered

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT15,T25,T26
101Not Covered
110CoveredT15,T25,T26
111Not Covered

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T25,T26
10Not Covered

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT15,T25,T26
11CoveredT15,T25,T26

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT15,T25,T26
10Not Covered
11CoveredT15,T25,T26

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT15,T25,T26

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT15,T25,T26

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT15,T25,T26
1Not Covered

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT15,T25,T26
100CoveredT15,T25,T26

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T25,T26
11CoveredT15,T25,T26

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT15,T25,T26
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT15,T25,T26
10CoveredT15,T25,T26
11CoveredT15,T25,T26

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T25,T26

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 17 73.91
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 3 75.00
IF 156 6 5 83.33
CASE 198 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T15,T25,T26
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T15,T25,T26
0 0 1 - - Covered T15,T25,T26
0 0 0 1 - Covered T15,T25,T26
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T15,T25,T26
StIdle 0 1 - - Covered T15,T25,T26
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T15,T25,T26
StWait - - - 1 Covered T15,T25,T26
StWait - - - 0 Covered T15,T25,T26
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 1243598 28 0 925
gen_wr_req.HwIdSelCheck_A 1243598 28 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1243598 28 0 925
T13 1589 0 0 1
T15 4087 2 0 1
T25 0 2 0 0
T26 0 6 0 0
T34 840 0 0 1
T35 894 0 0 1
T51 0 1 0 0
T52 0 2 0 0
T55 0 1 0 0
T56 0 1 0 0
T74 569 0 0 1
T75 577 0 0 1
T81 373 0 0 1
T82 429 0 0 1
T95 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T98 474 0 0 1
T99 3253 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1243598 28 0 0
T13 1589 0 0 0
T15 4087 2 0 0
T25 0 2 0 0
T26 0 6 0 0
T34 840 0 0 0
T35 894 0 0 0
T51 0 1 0 0
T52 0 2 0 0
T55 0 1 0 0
T56 0 1 0 0
T74 569 0 0 0
T75 577 0 0 0
T81 373 0 0 0
T82 429 0 0 0
T95 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T98 474 0 0 0
T99 3253 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%