Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83325840	144147	0	0
DepthKnown_A	83325840	83302090	0	0
RvalidKnown_A	83325840	83302090	0	0
WreadyKnown_A	83325840	83302090	0	0
gen_passthru_fifo.paramCheckPass	160	160	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83325840	144147	0	0
T1	988254	384	0	0
T2	670308	78	0	0
T3	673374	198	0	0
T4	355692	17804	0	0
T5	379054	20308	0	0
T6	325088	15258	0	0
T7	670176	199	0	0
T8	4114416	208	0	0
T9	5999460	393	0	0
T10	309548	14760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83325840	83302090	0	0
T1	1647090	1646970	0	0
T2	1117180	1117060	0	0
T3	1122290	1122180	0	0
T4	1778460	1776820	0	0
T5	1895270	1893530	0	0
T6	1625440	1623690	0	0
T7	1116960	1116850	0	0
T8	6857360	6856300	0	0
T9	9999100	9998010	0	0
T10	1547740	1545990	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83325840	83302090	0	0
T1	1647090	1646970	0	0
T2	1117180	1117060	0	0
T3	1122290	1122180	0	0
T4	1778460	1776820	0	0
T5	1895270	1893530	0	0
T6	1625440	1623690	0	0
T7	1116960	1116850	0	0
T8	6857360	6856300	0	0
T9	9999100	9998010	0	0
T10	1547740	1545990	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83325840	83302090	0	0
T1	1647090	1646970	0	0
T2	1117180	1117060	0	0
T3	1122290	1122180	0	0
T4	1778460	1776820	0	0
T5	1895270	1893530	0	0
T6	1625440	1623690	0	0
T7	1116960	1116850	0	0
T8	6857360	6856300	0	0
T9	9999100	9998010	0	0
T10	1547740	1545990	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	160	160	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	10	10	0	0
T8	10	10	0	0
T9	10	10	0	0
T10	10	10	0	0