Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	0	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	0	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	40018	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	40018	0	0
T1	164709	39	0	0
T2	111718	39	0	0
T3	112229	39	0	0
T4	177846	3819	0	0
T5	189527	4415	0	0
T6	162544	3267	0	0
T7	111696	39	0	0
T8	685736	39	0	0
T9	999910	39	0	0
T10	154774	3233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	103761	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	103761	0	0
T1	164709	161	0	0
T2	111718	39	0	0
T3	112229	159	0	0
T4	177846	13985	0	0
T5	189527	15893	0	0
T6	162544	11991	0	0
T7	111696	160	0	0
T8	685736	169	0	0
T9	999910	170	0	0
T10	154774	11527	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	92	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	92	0	0
T1	164709	46	0	0
T2	111718	0	0	0
T3	112229	0	0	0
T7	111696	0	0	0
T8	685736	0	0	0
T9	999910	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	92	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	92	0	0
T1	164709	46	0	0
T2	111718	0	0	0
T3	112229	0	0	0
T7	111696	0	0	0
T8	685736	0	0	0
T9	999910	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	0	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	0	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	92	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	92	0	0
T1	164709	46	0	0
T2	111718	0	0	0
T3	112229	0	0	0
T7	111696	0	0	0
T8	685736	0	0	0
T9	999910	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8332584	92	0	0
DepthKnown_A	8332584	8330209	0	0
RvalidKnown_A	8332584	8330209	0	0
WreadyKnown_A	8332584	8330209	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	92	0	0
T1	164709	46	0	0
T2	111718	0	0	0
T3	112229	0	0	0
T7	111696	0	0	0
T8	685736	0	0	0
T9	999910	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8332584	8330209	0	0
T1	164709	164697	0	0
T2	111718	111706	0	0
T3	112229	112218	0	0
T4	177846	177682	0	0
T5	189527	189353	0	0
T6	162544	162369	0	0
T7	111696	111685	0	0
T8	685736	685630	0	0
T9	999910	999801	0	0
T10	154774	154599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0