Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.09 31.09

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 24.07 24.07
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 29.74 29.74


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
24.07 24.07


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
24.07 24.07


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.63 55.20 74.71 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
29.74 29.74


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
29.74 29.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.63 55.20 74.71 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 26 40.62
Total Bits 1158 360 31.09
Total Bits 0->1 579 180 31.09
Total Bits 1->0 579 180 31.09

Ports 64 26 40.62
Port Bits 1158 360 31.09
Port Bits 0->1 579 180 31.09
Port Bits 1->0 579 180 31.09

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] No No No INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,*T9,T8 Yes T1,T9,T8 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] No No No INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid No No No INPUT
regs_tl_o.a_ready No No No OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] No No No OUTPUT
regs_tl_o.d_data[31:0] No No No OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[5:0] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] No No No OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] No No No OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid No No No OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p No No No INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p No No No OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[2:1] No No No INPUT
otp_en_sram_ifetch_i[3] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[4] No No No INPUT
otp_en_sram_ifetch_i[6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7] No No No INPUT
sram_otp_key_o.req No No No OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 20 33.33
Total Bits 1130 272 24.07
Total Bits 0->1 565 136 24.07
Total Bits 1->0 565 136 24.07

Ports 60 20 33.33
Port Bits 1130 272 24.07
Port Bits 0->1 565 136 24.07
Port Bits 1->0 565 136 24.07

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[14:2] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[16:15] No No No INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[0] No No No INPUT
ram_tl_i.a_source[1] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_source[5:2] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[1:0] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[0] No No No OUTPUT
ram_tl_o.d_source[1] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:0] No No No INPUT
regs_tl_i.a_user.instr_type[3:0] No No No INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] No No No INPUT
regs_tl_i.a_mask[3:0] No No No INPUT
regs_tl_i.a_address[4:0] No No No INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] No No No INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] No No No INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] No No No INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] No No No INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] No No No INPUT
regs_tl_i.a_valid No No No INPUT
regs_tl_o.a_ready No No No OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] No No No OUTPUT
regs_tl_o.d_data[31:0] No No No OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[5:0] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] No No No OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] No No No OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid No No No OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p No No No INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p No No No OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[2:1] No No No INPUT
otp_en_sram_ifetch_i[3] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[4] No No No INPUT
otp_en_sram_ifetch_i[6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7] No No No INPUT
sram_otp_key_o.req No No No OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 25 43.10
Total Bits 1096 326 29.74
Total Bits 0->1 548 163 29.74
Total Bits 1->0 548 163 29.74

Ports 58 25 43.10
Port Bits 1096 326 29.74
Port Bits 0->1 548 163 29.74
Port Bits 1->0 548 163 29.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_source[5:1] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] No No No INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T8 Yes T1,T8 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid No No No INPUT
regs_tl_o.a_ready No No No OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] No No No OUTPUT
regs_tl_o.d_data[31:0] No No No OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[5:0] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] No No No OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] No No No OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid No No No OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p No No No INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p No No No OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req No No No OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%