Unified Coverage Report :: Module :: top_earlgrey

Module : top_earlgrey

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.66	55.20		47.79			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey	76.63	55.20		74.71			100.00

---

Module Instance : tb.dut.top_earlgrey

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.63	55.20		74.71			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.62	66.79	62.35	35.44		74.89	83.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.90	76.19	50.00	95.52				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clk_ctrl_and_main_pd_sva_if	92.86			92.86
u_adc_ctrl_aon	23.46			23.46
u_aes	1.55			1.55
u_alert_handler	35.70			35.70
u_aon_timer_aon	25.48			25.48
u_clkmgr_aon	52.94			52.94
u_csrng	2.13			2.13
u_dft_tap_breakout	0.00	0.00		0.00
u_edn0	1.99			1.99
u_edn1	1.97			1.97
u_entropy_src	1.14			1.14
u_flash_ctrl	4.20			4.20
u_gpio	24.44			24.44
u_hmac	5.70			5.70
u_i2c0	21.51			21.51
u_i2c1	21.97			21.97
u_i2c2	21.97			21.97
u_keymgr	22.37			22.37
u_kmac	29.16			29.16
u_lc_ctrl	42.11			42.11
u_otbn	11.51			11.51
u_otp_ctrl	39.51			39.51
u_pattgen	85.33			85.33
u_pinmux_aon	90.23	90.39	78.04	93.28		91.89	97.54
u_pwm_aon	88.24			88.24
u_pwrmgr_aon	79.78			79.78
u_rom_ctrl	95.61			95.61
u_rstmgr_aon	85.31			85.31
u_rv_core_ibex	65.64	80.55	67.44	37.20		83.73	59.29
u_rv_dm	81.24			81.24
u_rv_plic	37.33	22.22	34.86	2.46		55.66	71.43
u_rv_timer	25.34			25.34
u_sensor_ctrl_aon	47.33	40.55	44.50	20.18		62.66	68.75
u_spi_device	31.58			31.58
u_spi_host0	10.23			10.23
u_spi_host1	4.94			4.94
u_sram_ctrl_main	24.07			24.07
u_sram_ctrl_ret_aon	29.74			29.74
u_sysrst_ctrl_aon	31.14			31.14
u_uart0	22.52			22.52
u_uart1	23.03			23.03
u_uart2	23.03			23.03
u_uart3	23.53			23.53
u_usbdev	5.94			5.94
u_xbar_main	36.52			36.52
u_xbar_peri	46.69			46.69

Line Coverage for Module : top_earlgrey

	Line No.	Total	Covered	Percent
TOTAL		279	154	55.20
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	755	1	0	0.00
CONT_ASSIGN	756	1	0	0.00
CONT_ASSIGN	757	1	0	0.00
CONT_ASSIGN	770	1	0	0.00
CONT_ASSIGN	771	1	0	0.00
CONT_ASSIGN	772	1	0	0.00
CONT_ASSIGN	773	1	0	0.00
CONT_ASSIGN	774	1	0	0.00
CONT_ASSIGN	775	1	0	0.00
CONT_ASSIGN	776	1	0	0.00
CONT_ASSIGN	777	1	0	0.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	793	1	1	100.00
CONT_ASSIGN	795	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	820	1	0	0.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	874	1	0	0.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	877	1	0	0.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	881	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	889	1	1	100.00
CONT_ASSIGN	890	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	904	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	907	1	1	100.00
CONT_ASSIGN	908	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	911	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	920	0	0
CONT_ASSIGN	922	0	0
CONT_ASSIGN	924	0	0
CONT_ASSIGN	926	0	0
CONT_ASSIGN	928	0	0
CONT_ASSIGN	930	0	0
CONT_ASSIGN	932	0	0
CONT_ASSIGN	934	0	0
CONT_ASSIGN	936	0	0
CONT_ASSIGN	938	0	0
CONT_ASSIGN	940	0	0
CONT_ASSIGN	942	0	0
CONT_ASSIGN	944	0	0
CONT_ASSIGN	946	0	0
CONT_ASSIGN	948	0	0
CONT_ASSIGN	950	0	0
CONT_ASSIGN	952	0	0
CONT_ASSIGN	954	0	0
CONT_ASSIGN	956	0	0
CONT_ASSIGN	958	0	0
CONT_ASSIGN	960	0	0
CONT_ASSIGN	962	0	0
CONT_ASSIGN	964	0	0
CONT_ASSIGN	966	0	0
CONT_ASSIGN	968	0	0
CONT_ASSIGN	970	0	0
CONT_ASSIGN	972	0	0
CONT_ASSIGN	974	0	0
CONT_ASSIGN	976	0	0
CONT_ASSIGN	978	0	0
CONT_ASSIGN	980	0	0
CONT_ASSIGN	982	0	0
CONT_ASSIGN	984	0	0
CONT_ASSIGN	986	0	0
CONT_ASSIGN	988	0	0
CONT_ASSIGN	990	0	0
CONT_ASSIGN	992	0	0
CONT_ASSIGN	994	0	0
CONT_ASSIGN	996	0	0
CONT_ASSIGN	998	0	0
CONT_ASSIGN	1000	0	0
CONT_ASSIGN	1002	0	0
CONT_ASSIGN	1004	0	0
CONT_ASSIGN	1006	0	0
CONT_ASSIGN	1008	0	0
CONT_ASSIGN	1010	0	0
CONT_ASSIGN	1012	0	0
CONT_ASSIGN	2648	1	0	0.00
CONT_ASSIGN	3048	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3051	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3054	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3057	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3060	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
CONT_ASSIGN	3065	1	1	100.00
CONT_ASSIGN	3066	1	1	100.00
CONT_ASSIGN	3067	1	1	100.00
CONT_ASSIGN	3068	1	1	100.00
CONT_ASSIGN	3069	1	1	100.00
CONT_ASSIGN	3070	1	1	100.00
CONT_ASSIGN	3071	1	1	100.00
CONT_ASSIGN	3072	1	1	100.00
CONT_ASSIGN	3073	1	1	100.00
CONT_ASSIGN	3074	1	1	100.00
CONT_ASSIGN	3075	1	1	100.00
CONT_ASSIGN	3076	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3078	1	1	100.00
CONT_ASSIGN	3079	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3081	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3084	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3088	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3090	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3092	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3096	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3107	1	0	0.00
CONT_ASSIGN	3108	1	0	0.00
CONT_ASSIGN	3109	1	0	0.00
CONT_ASSIGN	3110	1	0	0.00
CONT_ASSIGN	3111	1	0	0.00
CONT_ASSIGN	3112	1	0	0.00
CONT_ASSIGN	3113	1	0	0.00
CONT_ASSIGN	3114	1	0	0.00
CONT_ASSIGN	3115	1	0	0.00
CONT_ASSIGN	3116	1	0	0.00
CONT_ASSIGN	3117	1	0	0.00
CONT_ASSIGN	3118	1	0	0.00
CONT_ASSIGN	3119	1	0	0.00
CONT_ASSIGN	3120	1	0	0.00
CONT_ASSIGN	3121	1	0	0.00
CONT_ASSIGN	3122	1	0	0.00
CONT_ASSIGN	3123	1	0	0.00
CONT_ASSIGN	3124	1	0	0.00
CONT_ASSIGN	3125	1	0	0.00
CONT_ASSIGN	3126	1	0	0.00
CONT_ASSIGN	3127	1	0	0.00
CONT_ASSIGN	3128	1	0	0.00
CONT_ASSIGN	3129	1	0	0.00
CONT_ASSIGN	3130	1	0	0.00
CONT_ASSIGN	3131	1	0	0.00
CONT_ASSIGN	3132	1	0	0.00
CONT_ASSIGN	3133	1	0	0.00
CONT_ASSIGN	3134	1	0	0.00
CONT_ASSIGN	3135	1	0	0.00
CONT_ASSIGN	3136	1	0	0.00
CONT_ASSIGN	3137	1	0	0.00
CONT_ASSIGN	3138	1	0	0.00
CONT_ASSIGN	3139	0	0
CONT_ASSIGN	3140	0	0
CONT_ASSIGN	3141	0	0
CONT_ASSIGN	3142	0	0
CONT_ASSIGN	3143	0	0
CONT_ASSIGN	3144	0	0
CONT_ASSIGN	3145	1	0	0.00
CONT_ASSIGN	3146	1	0	0.00
CONT_ASSIGN	3147	1	0	0.00
CONT_ASSIGN	3148	1	0	0.00
CONT_ASSIGN	3149	1	0	0.00
CONT_ASSIGN	3150	1	0	0.00
CONT_ASSIGN	3151	1	0	0.00
CONT_ASSIGN	3152	1	0	0.00
CONT_ASSIGN	3153	1	0	0.00
CONT_ASSIGN	3154	1	1	100.00
CONT_ASSIGN	3155	1	0	0.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3157	1	0	0.00
CONT_ASSIGN	3158	1	0	0.00
CONT_ASSIGN	3159	1	0	0.00
CONT_ASSIGN	3160	0	0
CONT_ASSIGN	3161	0	0
CONT_ASSIGN	3162	0	0
CONT_ASSIGN	3163	0	0
CONT_ASSIGN	3164	0	0
CONT_ASSIGN	3165	0	0
CONT_ASSIGN	3166	0	0
CONT_ASSIGN	3167	0	0
CONT_ASSIGN	3168	0	0
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3172	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3175	1	0	0.00
CONT_ASSIGN	3176	1	0	0.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3181	1	0	0.00
CONT_ASSIGN	3184	1	0	0.00
CONT_ASSIGN	3185	1	0	0.00
CONT_ASSIGN	3186	1	0	0.00
CONT_ASSIGN	3187	1	0	0.00
CONT_ASSIGN	3188	1	0	0.00
CONT_ASSIGN	3189	1	0	0.00
CONT_ASSIGN	3190	1	0	0.00
CONT_ASSIGN	3191	1	0	0.00
CONT_ASSIGN	3192	1	0	0.00
CONT_ASSIGN	3193	1	0	0.00
CONT_ASSIGN	3194	1	0	0.00
CONT_ASSIGN	3195	1	0	0.00
CONT_ASSIGN	3196	1	0	0.00
CONT_ASSIGN	3197	1	0	0.00
CONT_ASSIGN	3198	1	0	0.00
CONT_ASSIGN	3199	1	0	0.00
CONT_ASSIGN	3200	1	0	0.00
CONT_ASSIGN	3201	1	0	0.00
CONT_ASSIGN	3202	1	0	0.00
CONT_ASSIGN	3203	1	0	0.00
CONT_ASSIGN	3204	1	0	0.00
CONT_ASSIGN	3205	1	0	0.00
CONT_ASSIGN	3206	1	0	0.00
CONT_ASSIGN	3207	1	0	0.00
CONT_ASSIGN	3208	1	0	0.00
CONT_ASSIGN	3209	1	0	0.00
CONT_ASSIGN	3210	1	0	0.00
CONT_ASSIGN	3211	1	0	0.00
CONT_ASSIGN	3212	1	0	0.00
CONT_ASSIGN	3213	1	0	0.00
CONT_ASSIGN	3214	1	0	0.00
CONT_ASSIGN	3215	1	0	0.00
CONT_ASSIGN	3216	1	0	0.00
CONT_ASSIGN	3217	1	0	0.00
CONT_ASSIGN	3218	1	0	0.00
CONT_ASSIGN	3219	1	0	0.00
CONT_ASSIGN	3220	1	0	0.00
CONT_ASSIGN	3221	1	0	0.00
CONT_ASSIGN	3222	1	0	0.00
CONT_ASSIGN	3223	1	0	0.00
CONT_ASSIGN	3224	1	0	0.00
CONT_ASSIGN	3225	1	0	0.00
CONT_ASSIGN	3226	0	0
CONT_ASSIGN	3227	0	0
CONT_ASSIGN	3228	0	0
CONT_ASSIGN	3229	0	0
CONT_ASSIGN	3230	0	0
CONT_ASSIGN	3231	0	0
CONT_ASSIGN	3232	0	0
CONT_ASSIGN	3233	0	0
CONT_ASSIGN	3234	1	0	0.00
CONT_ASSIGN	3235	1	0	0.00
CONT_ASSIGN	3236	1	0	0.00
CONT_ASSIGN	3237	0	0
CONT_ASSIGN	3238	0	0
CONT_ASSIGN	3239	0	0
CONT_ASSIGN	3240	0	0
CONT_ASSIGN	3241	0	0
CONT_ASSIGN	3242	0	0
CONT_ASSIGN	3243	0	0
CONT_ASSIGN	3244	0	0
CONT_ASSIGN	3245	0	0
CONT_ASSIGN	3246	0	0
CONT_ASSIGN	3247	0	0
CONT_ASSIGN	3248	0	0
CONT_ASSIGN	3249	0	0
CONT_ASSIGN	3250	0	0
CONT_ASSIGN	3251	0	0
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3253	0	0
CONT_ASSIGN	3254	0	0
CONT_ASSIGN	3255	0	0
CONT_ASSIGN	3256	0	0
CONT_ASSIGN	3257	0	0
CONT_ASSIGN	3258	0	0
CONT_ASSIGN	3262	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3265	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3268	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3275	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3279	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3281	1	0	0.00
CONT_ASSIGN	3282	1	0	0.00
CONT_ASSIGN	3283	1	0	0.00
CONT_ASSIGN	3284	1	0	0.00
CONT_ASSIGN	3285	1	1	100.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3287	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
CONT_ASSIGN	3289	1	0	0.00
CONT_ASSIGN	3290	1	0	0.00
CONT_ASSIGN	3293	1	0	0.00
CONT_ASSIGN	3294	1	0	0.00
CONT_ASSIGN	3297	1	1	100.00
CONT_ASSIGN	3298	1	1	100.00
CONT_ASSIGN	3299	1	0	0.00
CONT_ASSIGN	3300	1	0	0.00
CONT_ASSIGN	3301	1	0	0.00
CONT_ASSIGN	3302	1	0	0.00
CONT_ASSIGN	3303	1	1	100.00
CONT_ASSIGN	3304	1	1	100.00
CONT_ASSIGN	3305	1	1	100.00
CONT_ASSIGN	3306	1	1	100.00
CONT_ASSIGN	3307	0	0
CONT_ASSIGN	3308	0	0
CONT_ASSIGN	3311	1	0	0.00
CONT_ASSIGN	3312	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
750	1	1
751	0	1
752	1	1
753	0	1
754	0	1
755	0	1
756	0	1
757	0	1
770	0	1
771	0	1
772	0	1
773	0	1
774	0	1
775	0	1
776	0	1
777	0	1
791	1	1
793	1	1
795	1	1
797	1	1
799	1	1
801	1	1
805	1	1
815	1	1
816	1	1
820	0	1
844	1	1
845	1	1
847	1	1
848	1	1
850	1	1
851	1	1
853	1	1
854	1	1
856	1	1
857	1	1
859	1	1
860	1	1
862	1	1
863	1	1
865	1	1
866	1	1
868	1	1
869	1	1
871	1	1
872	1	1
874	0	1
875	1	1
877	0	1
878	1	1
880	1	1
881	1	1
883	1	1
884	1	1
886	1	1
887	1	1
889	1	1
890	1	1
892	1	1
893	1	1
895	1	1
896	1	1
898	1	1
899	1	1
901	1	1
902	1	1
904	1	1
905	1	1
907	1	1
908	1	1
910	1	1
911	1	1
913	1	1
914	1	1
920		unreachable
922		unreachable
924		unreachable
926		unreachable
928		unreachable
930		unreachable
932		unreachable
934		unreachable
936		unreachable
938		unreachable
940		unreachable
942		unreachable
944		unreachable
946		unreachable
948		unreachable
950		unreachable
952		unreachable
954		unreachable
956		unreachable
958		unreachable
960		unreachable
962		unreachable
964		unreachable
966		unreachable
968		unreachable
970		unreachable
972		unreachable
974		unreachable
976		unreachable
978		unreachable
980		unreachable
982		unreachable
984		unreachable
986		unreachable
988		unreachable
990		unreachable
992		unreachable
994		unreachable
996		unreachable
998		unreachable
1000		unreachable
1002		unreachable
1004		unreachable
1006		unreachable
1008		unreachable
1010		unreachable
1012		unreachable
2648	0	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3107	0	1
3108	0	1
3109	0	1
3110	0	1
3111	0	1
3112	0	1
3113	0	1
3114	0	1
3115	0	1
3116	0	1
3117	0	1
3118	0	1
3119	0	1
3120	0	1
3121	0	1
3122	0	1
3123	0	1
3124	0	1
3125	0	1
3126	0	1
3127	0	1
3128	0	1
3129	0	1
3130	0	1
3131	0	1
3132	0	1
3133	0	1
3134	0	1
3135	0	1
3136	0	1
3137	0	1
3138	0	1
3139		unreachable
3140		unreachable
3141		unreachable
3142		unreachable
3143		unreachable
3144		unreachable
3145	0	1
3146	0	1
3147	0	1
3148	0	1
3149	0	1
3150	0	1
3151	0	1
3152	0	1
3153	0	1
3154	1	1
3155	0	1
3156	1	1
3157	0	1
3158	0	1
3159	0	1
3160		unreachable
3161		unreachable
3162		unreachable
3163		unreachable
3164		unreachable
3165		unreachable
3166		unreachable
3167		unreachable
3168		unreachable
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3173	1	1
3174	1	1
3175	0	1
3176	0	1
3177	1	1
3178	1	1
3179	1	1
3180	1	1
3181	0	1
3184	0	1
3185	0	1
3186	0	1
3187	0	1
3188	0	1
3189	0	1
3190	0	1
3191	0	1
3192	0	1
3193	0	1
3194	0	1
3195	0	1
3196	0	1
3197	0	1
3198	0	1
3199	0	1
3200	0	1
3201	0	1
3202	0	1
3203	0	1
3204	0	1
3205	0	1
3206	0	1
3207	0	1
3208	0	1
3209	0	1
3210	0	1
3211	0	1
3212	0	1
3213	0	1
3214	0	1
3215	0	1
3216	0	1
3217	0	1
3218	0	1
3219	0	1
3220	0	1
3221	0	1
3222	0	1
3223	0	1
3224	0	1
3225	0	1
3226		unreachable
3227		unreachable
3228		unreachable
3229		unreachable
3230		unreachable
3231		unreachable
3232		unreachable
3233		unreachable
3234	0	1
3235	0	1
3236	0	1
3237		unreachable
3238		unreachable
3239		unreachable
3240		unreachable
3241		unreachable
3242		unreachable
3243		unreachable
3244		unreachable
3245		unreachable
3246		unreachable
3247		unreachable
3248		unreachable
3249		unreachable
3250		unreachable
3251		unreachable
3252	1	1
3253		unreachable
3254		unreachable
3255		unreachable
3256		unreachable
3257		unreachable
3258		unreachable
3262	1	1
3263	1	1
3264	1	1
3265	1	1
3266	1	1
3267	1	1
3268	1	1
3269	1	1
3270	1	1
3271	1	1
3272	1	1
3273	1	1
3274	1	1
3275	1	1
3276	1	1
3279	1	1
3280	1	1
3281	0	1
3282	0	1
3283	0	1
3284	0	1
3285	1	1
3286	1	1
3287	1	1
3288	1	1
3289	0	1
3290	0	1
3293	0	1
3294	0	1
3297	1	1
3298	1	1
3299	0	1
3300	0	1
3301	0	1
3302	0	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307		unreachable
3308		unreachable
3311	0	1
3312	0	1

---

Toggle Coverage for Module : top_earlgrey

	Total	Covered	Percent
Totals	788	323	40.99
Total Bits	2938	1404	47.79
Total Bits 0->1	1469	703	47.86
Total Bits 1->0	1469	701	47.72

Ports	788	323	40.99
Port Bits	2938	1404	47.79
Port Bits 0->1	1469	703	47.86
Port Bits 1->0	1469	701	47.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
mio_in_i[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
mio_out_o[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_in_i[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
dio_out_o[11:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].keep_en	No	No		No		OUTPUT
mio_attr_o[0].schmitt_en	No	No		No		OUTPUT
mio_attr_o[0].od_en	No	No		No		OUTPUT
mio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[1].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].keep_en	No	No		No		OUTPUT
mio_attr_o[1].schmitt_en	No	No		No		OUTPUT
mio_attr_o[1].od_en	No	No		No		OUTPUT
mio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[2].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].keep_en	No	No		No		OUTPUT
mio_attr_o[2].schmitt_en	No	No		No		OUTPUT
mio_attr_o[2].od_en	No	No		No		OUTPUT
mio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[3].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].keep_en	No	No		No		OUTPUT
mio_attr_o[3].schmitt_en	No	No		No		OUTPUT
mio_attr_o[3].od_en	No	No		No		OUTPUT
mio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[4].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].keep_en	No	No		No		OUTPUT
mio_attr_o[4].schmitt_en	No	No		No		OUTPUT
mio_attr_o[4].od_en	No	No		No		OUTPUT
mio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[5].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].keep_en	No	No		No		OUTPUT
mio_attr_o[5].schmitt_en	No	No		No		OUTPUT
mio_attr_o[5].od_en	No	No		No		OUTPUT
mio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[6].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].keep_en	No	No		No		OUTPUT
mio_attr_o[6].schmitt_en	No	No		No		OUTPUT
mio_attr_o[6].od_en	No	No		No		OUTPUT
mio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[7].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].keep_en	No	No		No		OUTPUT
mio_attr_o[7].schmitt_en	No	No		No		OUTPUT
mio_attr_o[7].od_en	No	No		No		OUTPUT
mio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[8].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].keep_en	No	No		No		OUTPUT
mio_attr_o[8].schmitt_en	No	No		No		OUTPUT
mio_attr_o[8].od_en	No	No		No		OUTPUT
mio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[9].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].keep_en	No	No		No		OUTPUT
mio_attr_o[9].schmitt_en	No	No		No		OUTPUT
mio_attr_o[9].od_en	No	No		No		OUTPUT
mio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[10].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].keep_en	No	No		No		OUTPUT
mio_attr_o[10].schmitt_en	No	No		No		OUTPUT
mio_attr_o[10].od_en	No	No		No		OUTPUT
mio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[11].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].keep_en	No	No		No		OUTPUT
mio_attr_o[11].schmitt_en	No	No		No		OUTPUT
mio_attr_o[11].od_en	No	No		No		OUTPUT
mio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[12].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].keep_en	No	No		No		OUTPUT
mio_attr_o[12].schmitt_en	No	No		No		OUTPUT
mio_attr_o[12].od_en	No	No		No		OUTPUT
mio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[13].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].keep_en	No	No		No		OUTPUT
mio_attr_o[13].schmitt_en	No	No		No		OUTPUT
mio_attr_o[13].od_en	No	No		No		OUTPUT
mio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[14].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].keep_en	No	No		No		OUTPUT
mio_attr_o[14].schmitt_en	No	No		No		OUTPUT
mio_attr_o[14].od_en	No	No		No		OUTPUT
mio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[15].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].keep_en	No	No		No		OUTPUT
mio_attr_o[15].schmitt_en	No	No		No		OUTPUT
mio_attr_o[15].od_en	No	No		No		OUTPUT
mio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[16].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].keep_en	No	No		No		OUTPUT
mio_attr_o[16].schmitt_en	No	No		No		OUTPUT
mio_attr_o[16].od_en	No	No		No		OUTPUT
mio_attr_o[16].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[17].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].keep_en	No	No		No		OUTPUT
mio_attr_o[17].schmitt_en	No	No		No		OUTPUT
mio_attr_o[17].od_en	No	No		No		OUTPUT
mio_attr_o[17].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[18].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].keep_en	No	No		No		OUTPUT
mio_attr_o[18].schmitt_en	No	No		No		OUTPUT
mio_attr_o[18].od_en	No	No		No		OUTPUT
mio_attr_o[18].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[19].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].keep_en	No	No		No		OUTPUT
mio_attr_o[19].schmitt_en	No	No		No		OUTPUT
mio_attr_o[19].od_en	No	No		No		OUTPUT
mio_attr_o[19].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[20].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].keep_en	No	No		No		OUTPUT
mio_attr_o[20].schmitt_en	No	No		No		OUTPUT
mio_attr_o[20].od_en	No	No		No		OUTPUT
mio_attr_o[20].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[21].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].keep_en	No	No		No		OUTPUT
mio_attr_o[21].schmitt_en	No	No		No		OUTPUT
mio_attr_o[21].od_en	No	No		No		OUTPUT
mio_attr_o[21].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[22].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].keep_en	No	No		No		OUTPUT
mio_attr_o[22].schmitt_en	No	No		No		OUTPUT
mio_attr_o[22].od_en	No	No		No		OUTPUT
mio_attr_o[22].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[23].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].keep_en	No	No		No		OUTPUT
mio_attr_o[23].schmitt_en	No	No		No		OUTPUT
mio_attr_o[23].od_en	No	No		No		OUTPUT
mio_attr_o[23].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[24].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].keep_en	No	No		No		OUTPUT
mio_attr_o[24].schmitt_en	No	No		No		OUTPUT
mio_attr_o[24].od_en	No	No		No		OUTPUT
mio_attr_o[24].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[25].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].keep_en	No	No		No		OUTPUT
mio_attr_o[25].schmitt_en	No	No		No		OUTPUT
mio_attr_o[25].od_en	No	No		No		OUTPUT
mio_attr_o[25].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[26].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].keep_en	No	No		No		OUTPUT
mio_attr_o[26].schmitt_en	No	No		No		OUTPUT
mio_attr_o[26].od_en	No	No		No		OUTPUT
mio_attr_o[26].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[27].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].keep_en	No	No		No		OUTPUT
mio_attr_o[27].schmitt_en	No	No		No		OUTPUT
mio_attr_o[27].od_en	No	No		No		OUTPUT
mio_attr_o[27].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[28].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].keep_en	No	No		No		OUTPUT
mio_attr_o[28].schmitt_en	No	No		No		OUTPUT
mio_attr_o[28].od_en	No	No		No		OUTPUT
mio_attr_o[28].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[29].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].keep_en	No	No		No		OUTPUT
mio_attr_o[29].schmitt_en	No	No		No		OUTPUT
mio_attr_o[29].od_en	No	No		No		OUTPUT
mio_attr_o[29].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[30].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].keep_en	No	No		No		OUTPUT
mio_attr_o[30].schmitt_en	No	No		No		OUTPUT
mio_attr_o[30].od_en	No	No		No		OUTPUT
mio_attr_o[30].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[31].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].keep_en	No	No		No		OUTPUT
mio_attr_o[31].schmitt_en	No	No		No		OUTPUT
mio_attr_o[31].od_en	No	No		No		OUTPUT
mio_attr_o[31].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[32].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].keep_en	No	No		No		OUTPUT
mio_attr_o[32].schmitt_en	No	No		No		OUTPUT
mio_attr_o[32].od_en	No	No		No		OUTPUT
mio_attr_o[32].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[33].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].keep_en	No	No		No		OUTPUT
mio_attr_o[33].schmitt_en	No	No		No		OUTPUT
mio_attr_o[33].od_en	No	No		No		OUTPUT
mio_attr_o[33].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[34].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].keep_en	No	No		No		OUTPUT
mio_attr_o[34].schmitt_en	No	No		No		OUTPUT
mio_attr_o[34].od_en	No	No		No		OUTPUT
mio_attr_o[34].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[35].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].keep_en	No	No		No		OUTPUT
mio_attr_o[35].schmitt_en	No	No		No		OUTPUT
mio_attr_o[35].od_en	No	No		No		OUTPUT
mio_attr_o[35].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[36].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].keep_en	No	No		No		OUTPUT
mio_attr_o[36].schmitt_en	No	No		No		OUTPUT
mio_attr_o[36].od_en	No	No		No		OUTPUT
mio_attr_o[36].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[37].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].keep_en	No	No		No		OUTPUT
mio_attr_o[37].schmitt_en	No	No		No		OUTPUT
mio_attr_o[37].od_en	No	No		No		OUTPUT
mio_attr_o[37].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[38].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].keep_en	No	No		No		OUTPUT
mio_attr_o[38].schmitt_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].od_en	No	No		No		OUTPUT
mio_attr_o[38].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[39].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].keep_en	No	No		No		OUTPUT
mio_attr_o[39].schmitt_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].od_en	No	No		No		OUTPUT
mio_attr_o[39].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[40].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].keep_en	No	No		No		OUTPUT
mio_attr_o[40].schmitt_en	No	No		No		OUTPUT
mio_attr_o[40].od_en	No	No		No		OUTPUT
mio_attr_o[40].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[41].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].keep_en	No	No		No		OUTPUT
mio_attr_o[41].schmitt_en	No	No		No		OUTPUT
mio_attr_o[41].od_en	No	No		No		OUTPUT
mio_attr_o[41].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[42].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].keep_en	No	No		No		OUTPUT
mio_attr_o[42].schmitt_en	No	No		No		OUTPUT
mio_attr_o[42].od_en	No	No		No		OUTPUT
mio_attr_o[42].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[43].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].keep_en	No	No		No		OUTPUT
mio_attr_o[43].schmitt_en	No	No		No		OUTPUT
mio_attr_o[43].od_en	No	No		No		OUTPUT
mio_attr_o[43].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[44].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].keep_en	No	No		No		OUTPUT
mio_attr_o[44].schmitt_en	No	No		No		OUTPUT
mio_attr_o[44].od_en	No	No		No		OUTPUT
mio_attr_o[44].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[45].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].keep_en	No	No		No		OUTPUT
mio_attr_o[45].schmitt_en	No	No		No		OUTPUT
mio_attr_o[45].od_en	No	No		No		OUTPUT
mio_attr_o[45].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[46].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].keep_en	No	No		No		OUTPUT
mio_attr_o[46].schmitt_en	No	No		No		OUTPUT
mio_attr_o[46].od_en	No	No		No		OUTPUT
mio_attr_o[46].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[0].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[1].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].keep_en	No	No		No		OUTPUT
dio_attr_o[1].schmitt_en	No	No		No		OUTPUT
dio_attr_o[1].od_en	No	No		No		OUTPUT
dio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[2].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].keep_en	No	No		No		OUTPUT
dio_attr_o[2].schmitt_en	No	No		No		OUTPUT
dio_attr_o[2].od_en	No	No		No		OUTPUT
dio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[3].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].keep_en	No	No		No		OUTPUT
dio_attr_o[3].schmitt_en	No	No		No		OUTPUT
dio_attr_o[3].od_en	No	No		No		OUTPUT
dio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[4].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].keep_en	No	No		No		OUTPUT
dio_attr_o[4].schmitt_en	No	No		No		OUTPUT
dio_attr_o[4].od_en	No	No		No		OUTPUT
dio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[5].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].keep_en	No	No		No		OUTPUT
dio_attr_o[5].schmitt_en	No	No		No		OUTPUT
dio_attr_o[5].od_en	No	No		No		OUTPUT
dio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[6].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].keep_en	No	No		No		OUTPUT
dio_attr_o[6].schmitt_en	No	No		No		OUTPUT
dio_attr_o[6].od_en	No	No		No		OUTPUT
dio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[7].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].keep_en	No	No		No		OUTPUT
dio_attr_o[7].schmitt_en	No	No		No		OUTPUT
dio_attr_o[7].od_en	No	No		No		OUTPUT
dio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[8].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].keep_en	No	No		No		OUTPUT
dio_attr_o[8].schmitt_en	No	No		No		OUTPUT
dio_attr_o[8].od_en	No	No		No		OUTPUT
dio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[9].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].keep_en	No	No		No		OUTPUT
dio_attr_o[9].schmitt_en	No	No		No		OUTPUT
dio_attr_o[9].od_en	No	No		No		OUTPUT
dio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[10].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].keep_en	No	No		No		OUTPUT
dio_attr_o[10].schmitt_en	No	No		No		OUTPUT
dio_attr_o[10].od_en	No	No		No		OUTPUT
dio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[11].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].keep_en	No	No		No		OUTPUT
dio_attr_o[11].schmitt_en	No	No		No		OUTPUT
dio_attr_o[11].od_en	No	No		No		OUTPUT
dio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[12].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].virt_od_en	No	No		No		OUTPUT
dio_attr_o[12].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].keep_en	No	No		No		OUTPUT
dio_attr_o[12].schmitt_en	No	No		No		OUTPUT
dio_attr_o[12].od_en	No	No		No		OUTPUT
dio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[13].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].virt_od_en	No	No		No		OUTPUT
dio_attr_o[13].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].keep_en	No	No		No		OUTPUT
dio_attr_o[13].schmitt_en	No	No		No		OUTPUT
dio_attr_o[13].od_en	No	No		No		OUTPUT
dio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[14].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].keep_en	No	No		No		OUTPUT
dio_attr_o[14].schmitt_en	No	No		No		OUTPUT
dio_attr_o[14].od_en	No	No		No		OUTPUT
dio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[15].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].keep_en	No	No		No		OUTPUT
dio_attr_o[15].schmitt_en	No	No		No		OUTPUT
dio_attr_o[15].od_en	No	No		No		OUTPUT
dio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
adc_req_o.pd	No	No		No		OUTPUT
adc_req_o.channel_sel[1:0]	No	No		No		OUTPUT
adc_rsp_i.data_valid	No	No		No		INPUT
adc_rsp_i.data[9:0]	No	No		No		INPUT
ast_edn_req_i.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_edn_rsp_o.edn_bus[31:0]	No	No		No		OUTPUT
ast_edn_rsp_o.edn_fips	No	No		No		OUTPUT
ast_edn_rsp_o.edn_ack	No	No		No		OUTPUT
ast_lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
clk_main_jitter_en_o[3:0]	No	No		No		OUTPUT
io_clk_byp_req_o[3:0]	No	No		No		OUTPUT
io_clk_byp_ack_i[3:0]	No	No		No		INPUT
all_clk_byp_req_o[3:0]	No	No		No		OUTPUT
all_clk_byp_ack_i[3:0]	No	No		No		INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
div_step_down_req_i[3:0]	No	No		No		INPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	No	Yes	T1,T2,T3	No		INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	No	No		No		INOUT
flash_test_voltage_h_io	No	No		No		INOUT
flash_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
es_rng_req_o.rng_enable	No	No		No		OUTPUT
es_rng_rsp_i.rng_b[3:0]	No	No		No		INPUT
es_rng_rsp_i.rng_valid	No	No		No		INPUT
es_rng_fips_o	No	No		No		OUTPUT
ast_tl_req_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
ast_tl_req_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_source[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ast_tl_req_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_opcode[1]	No	No		No		OUTPUT
ast_tl_req_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_rsp_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_error	No	No		No		INPUT
ast_tl_rsp_i.d_user.data_intg[6:0]	No	No		No		INPUT
ast_tl_rsp_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
ast_tl_rsp_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
ast_tl_rsp_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_sink	No	No		No		INPUT
ast_tl_rsp_i.d_source[0]	No	No		No		INPUT
ast_tl_rsp_i.d_source[5:1]	Yes	Yes	*T1,T2,T7	Yes	T1,T2,T7	INPUT
ast_tl_rsp_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_size[0]	No	No		No		INPUT
ast_tl_rsp_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_opcode[0]	No	No		No		INPUT
ast_tl_rsp_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dft_strap_test_o.straps[1:0]	No	No		No		OUTPUT
dft_strap_test_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
usb_dp_pullup_en_o	No	No		No		OUTPUT
usb_dn_pullup_en_o	No	No		No		OUTPUT
pwrmgr_ast_req_o.usb_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.io_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.core_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.slow_clk_en	No	No		No		OUTPUT
pwrmgr_ast_req_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.main_pd_n	No	No		No		OUTPUT
pwrmgr_ast_rsp_i.main_pok	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.usb_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.io_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.core_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.slow_clk_val	No	No		Yes	T1,T2,T3	INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0]	No	No		No		INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1]	No	Yes	T1,T2,T3	No		INPUT
otp_ext_voltage_h_io	No	No		No		INOUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
por_n_i[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p	No	No		No		INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p	No	No		No		OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0]	No	No		Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sck_monitor_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usbdev_usb_rx_d_i	No	No		No		INPUT
usbdev_usb_tx_d_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usbdev_usb_tx_se0_o	No	No		No		OUTPUT
usbdev_usb_tx_use_d_se0_o	No	No		No		OUTPUT
usbdev_usb_rx_enable_o	No	No		No		OUTPUT
usbdev_usb_ref_val_o	No	No		No		OUTPUT
usbdev_usb_ref_pulse_o	No	No		No		OUTPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clks_ast_o.clk_usb_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_otbn	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_kmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_hmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_aes	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c2_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c2_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c1_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c0_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_aon_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_aon_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host1_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host0_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_device_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_device_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_lc_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div4_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div2_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div2_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_aon_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : top_earlgrey

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
scanmodeKnown	8413551	8413551	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	8413551	8413551	0	0
T1	165195	165195	0	0
T2	112216	112216	0	0
T3	112862	112862	0	0
T4	183491	183491	0	0
T5	193026	193026	0	0
T6	166569	166569	0	0
T7	112167	112167	0	0
T8	688848	688848	0	0
T9	100245	100245	0	0
T10	160922	160922	0	0

Line Coverage for Instance : tb.dut.top_earlgrey

	Line No.	Total	Covered	Percent
TOTAL		279	154	55.20
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	755	1	0	0.00
CONT_ASSIGN	756	1	0	0.00
CONT_ASSIGN	757	1	0	0.00
CONT_ASSIGN	770	1	0	0.00
CONT_ASSIGN	771	1	0	0.00
CONT_ASSIGN	772	1	0	0.00
CONT_ASSIGN	773	1	0	0.00
CONT_ASSIGN	774	1	0	0.00
CONT_ASSIGN	775	1	0	0.00
CONT_ASSIGN	776	1	0	0.00
CONT_ASSIGN	777	1	0	0.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	793	1	1	100.00
CONT_ASSIGN	795	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	820	1	0	0.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	874	1	0	0.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	877	1	0	0.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	881	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	889	1	1	100.00
CONT_ASSIGN	890	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	904	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	907	1	1	100.00
CONT_ASSIGN	908	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	911	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	920	0	0
CONT_ASSIGN	922	0	0
CONT_ASSIGN	924	0	0
CONT_ASSIGN	926	0	0
CONT_ASSIGN	928	0	0
CONT_ASSIGN	930	0	0
CONT_ASSIGN	932	0	0
CONT_ASSIGN	934	0	0
CONT_ASSIGN	936	0	0
CONT_ASSIGN	938	0	0
CONT_ASSIGN	940	0	0
CONT_ASSIGN	942	0	0
CONT_ASSIGN	944	0	0
CONT_ASSIGN	946	0	0
CONT_ASSIGN	948	0	0
CONT_ASSIGN	950	0	0
CONT_ASSIGN	952	0	0
CONT_ASSIGN	954	0	0
CONT_ASSIGN	956	0	0
CONT_ASSIGN	958	0	0
CONT_ASSIGN	960	0	0
CONT_ASSIGN	962	0	0
CONT_ASSIGN	964	0	0
CONT_ASSIGN	966	0	0
CONT_ASSIGN	968	0	0
CONT_ASSIGN	970	0	0
CONT_ASSIGN	972	0	0
CONT_ASSIGN	974	0	0
CONT_ASSIGN	976	0	0
CONT_ASSIGN	978	0	0
CONT_ASSIGN	980	0	0
CONT_ASSIGN	982	0	0
CONT_ASSIGN	984	0	0
CONT_ASSIGN	986	0	0
CONT_ASSIGN	988	0	0
CONT_ASSIGN	990	0	0
CONT_ASSIGN	992	0	0
CONT_ASSIGN	994	0	0
CONT_ASSIGN	996	0	0
CONT_ASSIGN	998	0	0
CONT_ASSIGN	1000	0	0
CONT_ASSIGN	1002	0	0
CONT_ASSIGN	1004	0	0
CONT_ASSIGN	1006	0	0
CONT_ASSIGN	1008	0	0
CONT_ASSIGN	1010	0	0
CONT_ASSIGN	1012	0	0
CONT_ASSIGN	2648	1	0	0.00
CONT_ASSIGN	3048	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3051	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3054	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3057	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3060	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
CONT_ASSIGN	3065	1	1	100.00
CONT_ASSIGN	3066	1	1	100.00
CONT_ASSIGN	3067	1	1	100.00
CONT_ASSIGN	3068	1	1	100.00
CONT_ASSIGN	3069	1	1	100.00
CONT_ASSIGN	3070	1	1	100.00
CONT_ASSIGN	3071	1	1	100.00
CONT_ASSIGN	3072	1	1	100.00
CONT_ASSIGN	3073	1	1	100.00
CONT_ASSIGN	3074	1	1	100.00
CONT_ASSIGN	3075	1	1	100.00
CONT_ASSIGN	3076	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3078	1	1	100.00
CONT_ASSIGN	3079	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3081	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3084	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3088	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3090	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3092	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3096	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3107	1	0	0.00
CONT_ASSIGN	3108	1	0	0.00
CONT_ASSIGN	3109	1	0	0.00
CONT_ASSIGN	3110	1	0	0.00
CONT_ASSIGN	3111	1	0	0.00
CONT_ASSIGN	3112	1	0	0.00
CONT_ASSIGN	3113	1	0	0.00
CONT_ASSIGN	3114	1	0	0.00
CONT_ASSIGN	3115	1	0	0.00
CONT_ASSIGN	3116	1	0	0.00
CONT_ASSIGN	3117	1	0	0.00
CONT_ASSIGN	3118	1	0	0.00
CONT_ASSIGN	3119	1	0	0.00
CONT_ASSIGN	3120	1	0	0.00
CONT_ASSIGN	3121	1	0	0.00
CONT_ASSIGN	3122	1	0	0.00
CONT_ASSIGN	3123	1	0	0.00
CONT_ASSIGN	3124	1	0	0.00
CONT_ASSIGN	3125	1	0	0.00
CONT_ASSIGN	3126	1	0	0.00
CONT_ASSIGN	3127	1	0	0.00
CONT_ASSIGN	3128	1	0	0.00
CONT_ASSIGN	3129	1	0	0.00
CONT_ASSIGN	3130	1	0	0.00
CONT_ASSIGN	3131	1	0	0.00
CONT_ASSIGN	3132	1	0	0.00
CONT_ASSIGN	3133	1	0	0.00
CONT_ASSIGN	3134	1	0	0.00
CONT_ASSIGN	3135	1	0	0.00
CONT_ASSIGN	3136	1	0	0.00
CONT_ASSIGN	3137	1	0	0.00
CONT_ASSIGN	3138	1	0	0.00
CONT_ASSIGN	3139	0	0
CONT_ASSIGN	3140	0	0
CONT_ASSIGN	3141	0	0
CONT_ASSIGN	3142	0	0
CONT_ASSIGN	3143	0	0
CONT_ASSIGN	3144	0	0
CONT_ASSIGN	3145	1	0	0.00
CONT_ASSIGN	3146	1	0	0.00
CONT_ASSIGN	3147	1	0	0.00
CONT_ASSIGN	3148	1	0	0.00
CONT_ASSIGN	3149	1	0	0.00
CONT_ASSIGN	3150	1	0	0.00
CONT_ASSIGN	3151	1	0	0.00
CONT_ASSIGN	3152	1	0	0.00
CONT_ASSIGN	3153	1	0	0.00
CONT_ASSIGN	3154	1	1	100.00
CONT_ASSIGN	3155	1	0	0.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3157	1	0	0.00
CONT_ASSIGN	3158	1	0	0.00
CONT_ASSIGN	3159	1	0	0.00
CONT_ASSIGN	3160	0	0
CONT_ASSIGN	3161	0	0
CONT_ASSIGN	3162	0	0
CONT_ASSIGN	3163	0	0
CONT_ASSIGN	3164	0	0
CONT_ASSIGN	3165	0	0
CONT_ASSIGN	3166	0	0
CONT_ASSIGN	3167	0	0
CONT_ASSIGN	3168	0	0
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3172	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3175	1	0	0.00
CONT_ASSIGN	3176	1	0	0.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3181	1	0	0.00
CONT_ASSIGN	3184	1	0	0.00
CONT_ASSIGN	3185	1	0	0.00
CONT_ASSIGN	3186	1	0	0.00
CONT_ASSIGN	3187	1	0	0.00
CONT_ASSIGN	3188	1	0	0.00
CONT_ASSIGN	3189	1	0	0.00
CONT_ASSIGN	3190	1	0	0.00
CONT_ASSIGN	3191	1	0	0.00
CONT_ASSIGN	3192	1	0	0.00
CONT_ASSIGN	3193	1	0	0.00
CONT_ASSIGN	3194	1	0	0.00
CONT_ASSIGN	3195	1	0	0.00
CONT_ASSIGN	3196	1	0	0.00
CONT_ASSIGN	3197	1	0	0.00
CONT_ASSIGN	3198	1	0	0.00
CONT_ASSIGN	3199	1	0	0.00
CONT_ASSIGN	3200	1	0	0.00
CONT_ASSIGN	3201	1	0	0.00
CONT_ASSIGN	3202	1	0	0.00
CONT_ASSIGN	3203	1	0	0.00
CONT_ASSIGN	3204	1	0	0.00
CONT_ASSIGN	3205	1	0	0.00
CONT_ASSIGN	3206	1	0	0.00
CONT_ASSIGN	3207	1	0	0.00
CONT_ASSIGN	3208	1	0	0.00
CONT_ASSIGN	3209	1	0	0.00
CONT_ASSIGN	3210	1	0	0.00
CONT_ASSIGN	3211	1	0	0.00
CONT_ASSIGN	3212	1	0	0.00
CONT_ASSIGN	3213	1	0	0.00
CONT_ASSIGN	3214	1	0	0.00
CONT_ASSIGN	3215	1	0	0.00
CONT_ASSIGN	3216	1	0	0.00
CONT_ASSIGN	3217	1	0	0.00
CONT_ASSIGN	3218	1	0	0.00
CONT_ASSIGN	3219	1	0	0.00
CONT_ASSIGN	3220	1	0	0.00
CONT_ASSIGN	3221	1	0	0.00
CONT_ASSIGN	3222	1	0	0.00
CONT_ASSIGN	3223	1	0	0.00
CONT_ASSIGN	3224	1	0	0.00
CONT_ASSIGN	3225	1	0	0.00
CONT_ASSIGN	3226	0	0
CONT_ASSIGN	3227	0	0
CONT_ASSIGN	3228	0	0
CONT_ASSIGN	3229	0	0
CONT_ASSIGN	3230	0	0
CONT_ASSIGN	3231	0	0
CONT_ASSIGN	3232	0	0
CONT_ASSIGN	3233	0	0
CONT_ASSIGN	3234	1	0	0.00
CONT_ASSIGN	3235	1	0	0.00
CONT_ASSIGN	3236	1	0	0.00
CONT_ASSIGN	3237	0	0
CONT_ASSIGN	3238	0	0
CONT_ASSIGN	3239	0	0
CONT_ASSIGN	3240	0	0
CONT_ASSIGN	3241	0	0
CONT_ASSIGN	3242	0	0
CONT_ASSIGN	3243	0	0
CONT_ASSIGN	3244	0	0
CONT_ASSIGN	3245	0	0
CONT_ASSIGN	3246	0	0
CONT_ASSIGN	3247	0	0
CONT_ASSIGN	3248	0	0
CONT_ASSIGN	3249	0	0
CONT_ASSIGN	3250	0	0
CONT_ASSIGN	3251	0	0
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3253	0	0
CONT_ASSIGN	3254	0	0
CONT_ASSIGN	3255	0	0
CONT_ASSIGN	3256	0	0
CONT_ASSIGN	3257	0	0
CONT_ASSIGN	3258	0	0
CONT_ASSIGN	3262	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3265	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3268	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3275	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3279	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3281	1	0	0.00
CONT_ASSIGN	3282	1	0	0.00
CONT_ASSIGN	3283	1	0	0.00
CONT_ASSIGN	3284	1	0	0.00
CONT_ASSIGN	3285	1	1	100.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3287	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
CONT_ASSIGN	3289	1	0	0.00
CONT_ASSIGN	3290	1	0	0.00
CONT_ASSIGN	3293	1	0	0.00
CONT_ASSIGN	3294	1	0	0.00
CONT_ASSIGN	3297	1	1	100.00
CONT_ASSIGN	3298	1	1	100.00
CONT_ASSIGN	3299	1	0	0.00
CONT_ASSIGN	3300	1	0	0.00
CONT_ASSIGN	3301	1	0	0.00
CONT_ASSIGN	3302	1	0	0.00
CONT_ASSIGN	3303	1	1	100.00
CONT_ASSIGN	3304	1	1	100.00
CONT_ASSIGN	3305	1	1	100.00
CONT_ASSIGN	3306	1	1	100.00
CONT_ASSIGN	3307	0	0
CONT_ASSIGN	3308	0	0
CONT_ASSIGN	3311	1	0	0.00
CONT_ASSIGN	3312	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
750	1	1
751	0	1
752	1	1
753	0	1
754	0	1
755	0	1
756	0	1
757	0	1
770	0	1
771	0	1
772	0	1
773	0	1
774	0	1
775	0	1
776	0	1
777	0	1
791	1	1
793	1	1
795	1	1
797	1	1
799	1	1
801	1	1
805	1	1
815	1	1
816	1	1
820	0	1
844	1	1
845	1	1
847	1	1
848	1	1
850	1	1
851	1	1
853	1	1
854	1	1
856	1	1
857	1	1
859	1	1
860	1	1
862	1	1
863	1	1
865	1	1
866	1	1
868	1	1
869	1	1
871	1	1
872	1	1
874	0	1
875	1	1
877	0	1
878	1	1
880	1	1
881	1	1
883	1	1
884	1	1
886	1	1
887	1	1
889	1	1
890	1	1
892	1	1
893	1	1
895	1	1
896	1	1
898	1	1
899	1	1
901	1	1
902	1	1
904	1	1
905	1	1
907	1	1
908	1	1
910	1	1
911	1	1
913	1	1
914	1	1
920		unreachable
922		unreachable
924		unreachable
926		unreachable
928		unreachable
930		unreachable
932		unreachable
934		unreachable
936		unreachable
938		unreachable
940		unreachable
942		unreachable
944		unreachable
946		unreachable
948		unreachable
950		unreachable
952		unreachable
954		unreachable
956		unreachable
958		unreachable
960		unreachable
962		unreachable
964		unreachable
966		unreachable
968		unreachable
970		unreachable
972		unreachable
974		unreachable
976		unreachable
978		unreachable
980		unreachable
982		unreachable
984		unreachable
986		unreachable
988		unreachable
990		unreachable
992		unreachable
994		unreachable
996		unreachable
998		unreachable
1000		unreachable
1002		unreachable
1004		unreachable
1006		unreachable
1008		unreachable
1010		unreachable
1012		unreachable
2648	0	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3107	0	1
3108	0	1
3109	0	1
3110	0	1
3111	0	1
3112	0	1
3113	0	1
3114	0	1
3115	0	1
3116	0	1
3117	0	1
3118	0	1
3119	0	1
3120	0	1
3121	0	1
3122	0	1
3123	0	1
3124	0	1
3125	0	1
3126	0	1
3127	0	1
3128	0	1
3129	0	1
3130	0	1
3131	0	1
3132	0	1
3133	0	1
3134	0	1
3135	0	1
3136	0	1
3137	0	1
3138	0	1
3139		unreachable
3140		unreachable
3141		unreachable
3142		unreachable
3143		unreachable
3144		unreachable
3145	0	1
3146	0	1
3147	0	1
3148	0	1
3149	0	1
3150	0	1
3151	0	1
3152	0	1
3153	0	1
3154	1	1
3155	0	1
3156	1	1
3157	0	1
3158	0	1
3159	0	1
3160		unreachable
3161		unreachable
3162		unreachable
3163		unreachable
3164		unreachable
3165		unreachable
3166		unreachable
3167		unreachable
3168		unreachable
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3173	1	1
3174	1	1
3175	0	1
3176	0	1
3177	1	1
3178	1	1
3179	1	1
3180	1	1
3181	0	1
3184	0	1
3185	0	1
3186	0	1
3187	0	1
3188	0	1
3189	0	1
3190	0	1
3191	0	1
3192	0	1
3193	0	1
3194	0	1
3195	0	1
3196	0	1
3197	0	1
3198	0	1
3199	0	1
3200	0	1
3201	0	1
3202	0	1
3203	0	1
3204	0	1
3205	0	1
3206	0	1
3207	0	1
3208	0	1
3209	0	1
3210	0	1
3211	0	1
3212	0	1
3213	0	1
3214	0	1
3215	0	1
3216	0	1
3217	0	1
3218	0	1
3219	0	1
3220	0	1
3221	0	1
3222	0	1
3223	0	1
3224	0	1
3225	0	1
3226		unreachable
3227		unreachable
3228		unreachable
3229		unreachable
3230		unreachable
3231		unreachable
3232		unreachable
3233		unreachable
3234	0	1
3235	0	1
3236	0	1
3237		unreachable
3238		unreachable
3239		unreachable
3240		unreachable
3241		unreachable
3242		unreachable
3243		unreachable
3244		unreachable
3245		unreachable
3246		unreachable
3247		unreachable
3248		unreachable
3249		unreachable
3250		unreachable
3251		unreachable
3252	1	1
3253		unreachable
3254		unreachable
3255		unreachable
3256		unreachable
3257		unreachable
3258		unreachable
3262	1	1
3263	1	1
3264	1	1
3265	1	1
3266	1	1
3267	1	1
3268	1	1
3269	1	1
3270	1	1
3271	1	1
3272	1	1
3273	1	1
3274	1	1
3275	1	1
3276	1	1
3279	1	1
3280	1	1
3281	0	1
3282	0	1
3283	0	1
3284	0	1
3285	1	1
3286	1	1
3287	1	1
3288	1	1
3289	0	1
3290	0	1
3293	0	1
3294	0	1
3297	1	1
3298	1	1
3299	0	1
3300	0	1
3301	0	1
3302	0	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307		unreachable
3308		unreachable
3311	0	1
3312	0	1

---

Toggle Coverage for Instance : tb.dut.top_earlgrey

	Total	Covered	Percent
Totals	526	382	72.62
Total Bits	1874	1400	74.71
Total Bits 0->1	937	701	74.81
Total Bits 1->0	937	699	74.60

Ports	526	382	72.62
Port Bits	1874	1400	74.71
Port Bits 0->1	937	701	74.81
Port Bits 1->0	937	699	74.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
mio_in_i[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
mio_out_o[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_in_i[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
dio_out_o[11:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[16].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[17].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[18].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[19].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[20].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[21].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[22].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[23].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[24].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[25].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[26].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[27].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[28].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[29].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[30].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[31].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[32].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[33].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[34].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[35].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[36].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[37].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[38].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[39].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[40].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[41].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[42].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[43].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[44].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[45].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
mio_attr_o[46].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[0].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].invert	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
dio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
adc_req_o.pd	No	No		No		OUTPUT
adc_req_o.channel_sel[1:0]	No	No		No		OUTPUT
adc_rsp_i.data_valid	No	No		No		INPUT
adc_rsp_i.data[9:0]	No	No		No		INPUT
ast_edn_req_i.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_edn_rsp_o.edn_bus[31:0]	No	No		No		OUTPUT
ast_edn_rsp_o.edn_fips	No	No		No		OUTPUT
ast_edn_rsp_o.edn_ack	No	No		No		OUTPUT
ast_lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
obs_ctrl_i.obmen[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
ram_1p_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
rom_cfg_i.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
clk_main_jitter_en_o[3:0]	No	No		No		OUTPUT
io_clk_byp_req_o[3:0]	No	No		No		OUTPUT
io_clk_byp_ack_i[3:0]	No	No		No		INPUT
all_clk_byp_req_o[3:0]	No	No		No		OUTPUT
all_clk_byp_ack_i[3:0]	No	No		No		INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
div_step_down_req_i[3:0]	No	No		No		INPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	No	Yes	T1,T2,T3	No		INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
es_rng_req_o.rng_enable	No	No		No		OUTPUT
es_rng_rsp_i.rng_b[3:0]	No	No		No		INPUT
es_rng_rsp_i.rng_valid	No	No		No		INPUT
es_rng_fips_o	No	No		No		OUTPUT
ast_tl_req_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
ast_tl_req_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_source[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ast_tl_req_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_opcode[1]	No	No		No		OUTPUT
ast_tl_req_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_rsp_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_error	No	No		No		INPUT
ast_tl_rsp_i.d_user.data_intg[6:0]	No	No		No		INPUT
ast_tl_rsp_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
ast_tl_rsp_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
ast_tl_rsp_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_sink	No	No		No		INPUT
ast_tl_rsp_i.d_source[0]	No	No		No		INPUT
ast_tl_rsp_i.d_source[5:1]	Yes	Yes	*T1,T2,T7	Yes	T1,T2,T7	INPUT
ast_tl_rsp_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_size[0]	No	No		No		INPUT
ast_tl_rsp_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_opcode[0]	No	No		No		INPUT
ast_tl_rsp_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dft_strap_test_o.straps[1:0]	No	No		No		OUTPUT
dft_strap_test_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
usb_dp_pullup_en_o	No	No		No		OUTPUT
usb_dn_pullup_en_o	No	No		No		OUTPUT
pwrmgr_ast_req_o.usb_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.io_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.core_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.slow_clk_en	No	No		No		OUTPUT
pwrmgr_ast_req_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.main_pd_n	No	No		No		OUTPUT
pwrmgr_ast_rsp_i.main_pok	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.usb_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.io_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.core_clk_val	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.slow_clk_val	No	No		Yes	T1,T2,T3	INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0]	No	No		No		INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1]	No	Yes	T1,T2,T3	No		INPUT
otp_ext_voltage_h_io[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
por_n_i[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n	No	No		No		INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p	No	No		No		INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n	No	No		No		OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p	No	No		No		OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0]	No	No		Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sck_monitor_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usbdev_usb_rx_d_i	No	No		No		INPUT
usbdev_usb_tx_d_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usbdev_usb_tx_se0_o	No	No		No		OUTPUT
usbdev_usb_tx_use_d_se0_o	No	No		No		OUTPUT
usbdev_usb_rx_enable_o	No	No		No		OUTPUT
usbdev_usb_ref_val_o	No	No		No		OUTPUT
usbdev_usb_ref_pulse_o	No	No		No		OUTPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clks_ast_o.clk_usb_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_otbn	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_kmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_hmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_aes	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c2_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c2_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c1_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c0_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_aon_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_aon_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host1_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host0_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_device_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_device_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_lc_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div4_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div2_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div2_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_n[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_aon_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Instance : tb.dut.top_earlgrey

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
scanmodeKnown	8413551	8413551	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	8413551	8413551	0	0
T1	165195	165195	0	0
T2	112216	112216	0	0
T3	112862	112862	0	0
T4	183491	183491	0	0
T5	193026	193026	0	0
T6	166569	166569	0	0
T7	112167	112167	0	0
T8	688848	688848	0	0
T9	100245	100245	0	0
T10	160922	160922	0	0