Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.94	66.67	50.00	90.14

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	73.90	76.19	50.00	95.52

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.90	76.19	50.00	95.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.04	67.31	64.84	36.65		75.78	85.61

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	64.62	66.79	62.35	35.44		74.89	83.62
u_ast	54.04			54.04
u_padring	98.93	99.77	100.00	94.86		100.00	100.00
u_prim_usb_diff_rx	44.44	50.00	33.33			50.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		24	16	66.67
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	808	1	0	0.00
CONT_ASSIGN	833	1	0	0.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	862	1	0	0.00
CONT_ASSIGN	865	1	1	100.00
ALWAYS	1010	3	0	0.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1060	1	1	100.00
CONT_ASSIGN	1061	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00
CONT_ASSIGN	1067	1	1	100.00
CONT_ASSIGN	1068	1	1	100.00
CONT_ASSIGN	1069	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
213	1	1
214	1	1
797	0	1
808	0	1
833	0	1
840	0	1
847	1	1
850	1	1
856	1	1
858	1	1
862	0	1
865	1	1
1010	0	1
1011	0	1
1012	0	1
1042	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	142	128	90.14
Total Bits 0->1	71	64	90.14
Total Bits 1->0	71	64	90.14

Ports	71	64	90.14
Port Bits	142	128	90.14
Port Bits 0->1	71	64	90.14
Port Bits 1->0	71	64	90.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
USB_N	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
CC1	No	No		No		INOUT
CC2	No	No		No		INOUT
FLASH_TEST_VOLT	No	No		No		INOUT
FLASH_TEST_MODE0	No	No		No		INOUT
FLASH_TEST_MODE1	No	No		No		INOUT
OTP_EXT_VOLT	No	No		No		INOUT
SPI_HOST_D0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_CLK	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_CS_L	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_CLK	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_CS_L	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
AST_MISC	No	No		No		INOUT
IOA0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR0	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR1	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR2	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR3	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR4	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR13	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		21	16	76.19
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	808	1	0	0.00
CONT_ASSIGN	833	1	0	0.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	862	1	0	0.00
CONT_ASSIGN	865	1	1	100.00
ALWAYS	1010	0	0
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1060	1	1	100.00
CONT_ASSIGN	1061	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00
CONT_ASSIGN	1067	1	1	100.00
CONT_ASSIGN	1068	1	1	100.00
CONT_ASSIGN	1069	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
213	1	1
214	1	1
797	0	1
808	0	1
833	0	1
840	0	1
847	1	1
850	1	1
856	1	1
858	1	1
862	0	1
865	1	1
1010		excluded
			Exclude Annotation: [UNR] Tied off.
1011		excluded
			Exclude Annotation: [UNR] Tied off.
1012		excluded
			Exclude Annotation: [UNR] Tied off.
1042	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	67	64	95.52
Total Bits	134	128	95.52
Total Bits 0->1	67	64	95.52
Total Bits 1->0	67	64	95.52

Ports	67	64	95.52
Port Bits	134	128	95.52
Port Bits 0->1	67	64	95.52
Port Bits 1->0	67	64	95.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
USB_N	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
CC1	No	No		No		INOUT
CC2	No	No		No		INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_D3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_CLK	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_HOST_CS_L	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_D3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_CLK	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
SPI_DEV_CS_L	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
AST_MISC	No	No		No		INOUT
IOA0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOA8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOB12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC0	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC1	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC2	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC3	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC4	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC8	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC9	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOC12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR0	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR1	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR2	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR3	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR4	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INOUT
IOR5	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR6	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR7	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR10	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR11	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR12	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT
IOR13	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INOUT