Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.88	95.29	89.29	86.64		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	88.10	95.29	89.29	87.72		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.10	95.29	89.29	87.72		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.12	96.03	81.35	90.62		95.47	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	75.00			75.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	92.37	97.67	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	92.81	95.74	80.12			95.38	100.00
u_sim_win_rsp	80.88	77.55	68.18			77.78	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	81	95.29
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	0	0.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	0	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T98,T269
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T140,T243,T270
1	0	Covered	T32,T5,T139

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T5,T139

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T106,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T32,T139,T228

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T32,T5,T139
0	1	0	Covered	T31,T98,T269
1	0	0	Covered	T271,T272,T273

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T31
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	91	75.21
Total Bits	1624	1407	86.64
Total Bits 0->1	812	704	86.70
Total Bits 1->0	812	703	86.58

Ports	121	91	75.21
Port Bits	1624	1407	86.64
Port Bits 0->1	812	704	86.70
Port Bits 1->0	812	703	86.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T164,T169,T274	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T31,T98,*T269	Yes	T31,T98,T269	OUTPUT
corei_tl_h_o.a_address[30]	No	No		No		OUTPUT
corei_tl_h_o.a_address[31]	Yes	Yes	T202,T203,T275	Yes	T202,T203,T275	OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T98,*T95	Yes	T31,T98,T95	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T49,T60,T52	Yes	T49,T60,T52	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T99,T30,T100	Yes	T99,T30,T100	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T99,T30,T100	Yes	T99,T30,T100	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T99,T28,T29	Yes	T99,T28,T29	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T33,T101	Yes	T31,T33,T101	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_timer_i	Yes	Yes	T3,T276,T165	Yes	T3,T276,T165	INPUT
irq_external_i	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
nmi_wdog_i	Yes	Yes	T118,T198,T277	Yes	T118,T198,T277	INPUT
debug_req_i	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T31,T67,T118	Yes	T31,T67,T68	INPUT
edn_i.edn_fips	Yes	Yes	T66,T135,T205	Yes	T66,T127,T135	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T201,T202,T142	Yes	T201,T202,T142	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T31,T67,T32	Yes	T1,T2,T31	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T68,T118,T32	INPUT
icache_otp_key_i.ack	Yes	Yes	T201,T202,T203	Yes	T201,T202,T203	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T32,T139,T228	Yes	T32,T139,T228	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T31,T98,T271	Yes	T31,T98,T271	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T147,T148,T158	Yes	T148,T158,T278	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T148,T158,T278	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T32,T139,T228	Yes	T32,T139,T228	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T31,T98,T271	Yes	T31,T98,T271	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T5,T139
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T140,T243,T270
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	428806449	10	0	0
FpvSecCmIbexFetchEnable1_A	428806449	23451853	0	88
FpvSecCmIbexFetchEnable2_A	428806449	62182360	0	76
FpvSecCmIbexFetchEnable3Rev_A	428806449	361966622	0	1884
FpvSecCmIbexFetchEnable3_A	428806449	361968404	0	1783
FpvSecCmIbexInstrIntgErrCheck_A	428806449	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	428806449	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	428806449	0	0	0
FpvSecCmIbexPcMismatchCheck_A	428806449	0	0	0
FpvSecCmIbexRfEccErrCheck_A	428806449	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	428806449	0	0	0
FpvSecCmRegWeOnehotCheck_A	428806449	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	428806449	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	428806449	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	428806449	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	954	954	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	954	954	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	428806449	162	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	428806449	201	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	10	0	0
T49	997570	0	0	0
T140	229892	1	0	0
T141	0	1	0	0
T189	167221	0	0	0
T228	238066	0	0	0
T243	264382	1	0	0
T254	91155	0	0	0
T270	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	0	1	0	0
T282	0	1	0	0
T283	0	1	0	0
T284	0	1	0	0
T285	75185	0	0	0
T286	59730	0	0	0
T287	177591	0	0	0
T288	112840	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	23451853	0	88
T1	149174	9931	0	0
T2	128270	9927	0	0
T3	86994	9923	0	0
T31	306371	40866	0	0
T32	264387	62964	0	0
T33	288121	41119	0	0
T44	0	0	0	2
T49	0	0	0	2
T67	147442	9923	0	0
T68	87045	9923	0	0
T118	135546	9927	0	0
T159	162226	9931	0	0
T181	0	0	0	2
T182	0	0	0	2
T185	0	0	0	2
T192	0	0	0	2
T195	0	0	0	2
T196	0	0	0	2
T289	0	0	0	2
T290	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	62182360	0	76
T1	149174	38801	0	0
T2	128270	38312	0	0
T3	86994	34775	0	0
T7	0	0	0	2
T31	306371	69551	0	0
T32	264387	69555	0	0
T33	288121	69554	0	0
T44	0	0	0	2
T49	0	0	0	2
T67	147442	37815	0	0
T68	87045	34775	0	0
T108	0	0	0	2
T118	135546	34790	0	0
T159	162226	34775	0	0
T185	0	0	0	2
T192	0	0	0	2
T193	0	0	0	2
T195	0	0	0	2
T196	0	0	0	2
T291	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	361966622	0	1884
T1	149174	110310	0	2
T2	128270	89895	0	2
T3	86994	52161	0	2
T31	306371	215691	0	2
T32	264387	151612	0	2
T33	288121	197184	0	2
T67	147442	109567	0	2
T68	87045	52212	0	2
T118	135546	100694	0	2
T159	162226	127390	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	361968404	0	1783
T1	149174	110313	0	2
T2	128270	89898	0	2
T3	86994	52162	0	2
T31	306371	215692	0	2
T32	264387	151614	0	2
T33	288121	197186	0	2
T67	147442	109570	0	2
T68	87045	52213	0	2
T118	135546	100696	0	2
T159	162226	127391	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	76	0	0
T62	602118	0	0	0
T92	197144	0	0	0
T172	151279	0	0	0
T186	162742	0	0	0
T205	180794	0	0	0
T253	100270	0	0	0
T269	254426	76	0	0
T292	183087	0	0	0
T293	940642	0	0	0
T294	205965	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	586	0	0
T31	306371	1	0	0
T32	264387	0	0	0
T33	288121	0	0	0
T67	147442	0	0	0
T68	87045	0	0	0
T98	0	1	0	0
T118	135546	0	0	0
T119	195127	0	0	0
T123	86893	0	0	0
T134	241418	0	0	0
T144	0	32	0	0
T159	162226	0	0	0
T199	0	32	0	0
T295	0	1	0	0
T296	0	100	0	0
T297	0	31	0	0
T298	0	32	0	0
T299	0	1	0	0
T300	0	30	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	5	0	0
T10	210143	0	0	0
T14	203136	0	0	0
T15	640530	0	0	0
T21	109928	0	0	0
T88	253546	0	0	0
T124	97142	0	0	0
T239	189367	0	0	0
T240	197600	0	0	0
T271	285020	1	0	0
T272	0	1	0	0
T273	0	1	0	0
T277	132713	0	0	0
T301	0	1	0	0
T302	0	1	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	162	0	0
T43	125007	0	0	0
T201	85434	21	0	0
T202	0	16	0	0
T203	0	17	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	17	0	0
T303	0	46	0	0
T304	0	45	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	201	0	0
T43	125007	0	0	0
T142	0	16	0	0
T143	0	16	0	0
T145	0	16	0	0
T201	85434	5	0	0
T202	0	42	0	0
T203	0	42	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	42	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	81	95.29
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	0	0.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	0	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T98,T269
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T140,T243,T270
1	0	Covered	T32,T5,T139

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T5,T139

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T106,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T32,T139,T228

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T139,T228
1	0	Covered	T1,T2,T3
1	1	Covered	T106,T151,T152

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T32,T5,T139
0	1	0	Covered	T31,T98,T269
1	0	0	Covered	T271,T272,T273

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T31
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	91	77.78
Total Bits	1604	1407	87.72
Total Bits 0->1	802	704	87.78
Total Bits 1->0	802	703	87.66

Ports	117	91	77.78
Port Bits	1604	1407	87.72
Port Bits 0->1	802	704	87.78
Port Bits 1->0	802	703	87.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T164,T169,T274	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T31,T98,*T269	Yes	T31,T98,T269	OUTPUT
corei_tl_h_o.a_address[30]	No	No		No		OUTPUT
corei_tl_h_o.a_address[31]	Yes	Yes	T202,T203,T275	Yes	T202,T203,T275	OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T98,*T95	Yes	T31,T98,T95	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T49,T60,T52	Yes	T49,T60,T52	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T99,T30,T100	Yes	T99,T30,T100	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T99,T30,T100	Yes	T99,T30,T100	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T99,T28,T29	Yes	T99,T28,T29	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T33,T101	Yes	T31,T33,T101	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_timer_i	Yes	Yes	T3,T276,T165	Yes	T3,T276,T165	INPUT
irq_external_i	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
nmi_wdog_i	Yes	Yes	T118,T198,T277	Yes	T118,T198,T277	INPUT
debug_req_i	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T31,T67,T118	Yes	T31,T67,T68	INPUT
edn_i.edn_fips	Yes	Yes	T66,T135,T205	Yes	T66,T127,T135	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T201,T202,T142	Yes	T201,T202,T142	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T31,T67,T32	Yes	T1,T2,T31	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T68,T118,T32	INPUT
icache_otp_key_i.ack	Yes	Yes	T201,T202,T203	Yes	T201,T202,T203	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T32,T139,T228	Yes	T32,T139,T228	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T31,T98,T271	Yes	T31,T98,T271	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T147,T148,T158	Yes	T148,T158,T278	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T148,T158,T278	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T32,T139,T228	Yes	T32,T139,T228	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T31,T98,T271	Yes	T31,T98,T271	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T5,T139
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T140,T243,T270
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T31
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	428806449	10	0	0
FpvSecCmIbexFetchEnable1_A	428806449	23451853	0	88
FpvSecCmIbexFetchEnable2_A	428806449	62182360	0	76
FpvSecCmIbexFetchEnable3Rev_A	428806449	361966622	0	1884
FpvSecCmIbexFetchEnable3_A	428806449	361968404	0	1783
FpvSecCmIbexInstrIntgErrCheck_A	428806449	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	428806449	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	428806449	0	0	0
FpvSecCmIbexPcMismatchCheck_A	428806449	0	0	0
FpvSecCmIbexRfEccErrCheck_A	428806449	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	428806449	0	0	0
FpvSecCmRegWeOnehotCheck_A	428806449	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	428806449	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	428806449	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	428806449	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	954	954	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	954	954	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	954	954	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	428806449	162	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	428806449	201	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	10	0	0
T49	997570	0	0	0
T140	229892	1	0	0
T141	0	1	0	0
T189	167221	0	0	0
T228	238066	0	0	0
T243	264382	1	0	0
T254	91155	0	0	0
T270	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	0	1	0	0
T282	0	1	0	0
T283	0	1	0	0
T284	0	1	0	0
T285	75185	0	0	0
T286	59730	0	0	0
T287	177591	0	0	0
T288	112840	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	23451853	0	88
T1	149174	9931	0	0
T2	128270	9927	0	0
T3	86994	9923	0	0
T31	306371	40866	0	0
T32	264387	62964	0	0
T33	288121	41119	0	0
T44	0	0	0	2
T49	0	0	0	2
T67	147442	9923	0	0
T68	87045	9923	0	0
T118	135546	9927	0	0
T159	162226	9931	0	0
T181	0	0	0	2
T182	0	0	0	2
T185	0	0	0	2
T192	0	0	0	2
T195	0	0	0	2
T196	0	0	0	2
T289	0	0	0	2
T290	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	62182360	0	76
T1	149174	38801	0	0
T2	128270	38312	0	0
T3	86994	34775	0	0
T7	0	0	0	2
T31	306371	69551	0	0
T32	264387	69555	0	0
T33	288121	69554	0	0
T44	0	0	0	2
T49	0	0	0	2
T67	147442	37815	0	0
T68	87045	34775	0	0
T108	0	0	0	2
T118	135546	34790	0	0
T159	162226	34775	0	0
T185	0	0	0	2
T192	0	0	0	2
T193	0	0	0	2
T195	0	0	0	2
T196	0	0	0	2
T291	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	361966622	0	1884
T1	149174	110310	0	2
T2	128270	89895	0	2
T3	86994	52161	0	2
T31	306371	215691	0	2
T32	264387	151612	0	2
T33	288121	197184	0	2
T67	147442	109567	0	2
T68	87045	52212	0	2
T118	135546	100694	0	2
T159	162226	127390	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	361968404	0	1783
T1	149174	110313	0	2
T2	128270	89898	0	2
T3	86994	52162	0	2
T31	306371	215692	0	2
T32	264387	151614	0	2
T33	288121	197186	0	2
T67	147442	109570	0	2
T68	87045	52213	0	2
T118	135546	100696	0	2
T159	162226	127391	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	76	0	0
T62	602118	0	0	0
T92	197144	0	0	0
T172	151279	0	0	0
T186	162742	0	0	0
T205	180794	0	0	0
T253	100270	0	0	0
T269	254426	76	0	0
T292	183087	0	0	0
T293	940642	0	0	0
T294	205965	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	586	0	0
T31	306371	1	0	0
T32	264387	0	0	0
T33	288121	0	0	0
T67	147442	0	0	0
T68	87045	0	0	0
T98	0	1	0	0
T118	135546	0	0	0
T119	195127	0	0	0
T123	86893	0	0	0
T134	241418	0	0	0
T144	0	32	0	0
T159	162226	0	0	0
T199	0	32	0	0
T295	0	1	0	0
T296	0	100	0	0
T297	0	31	0	0
T298	0	32	0	0
T299	0	1	0	0
T300	0	30	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	5	0	0
T10	210143	0	0	0
T14	203136	0	0	0
T15	640530	0	0	0
T21	109928	0	0	0
T88	253546	0	0	0
T124	97142	0	0	0
T239	189367	0	0	0
T240	197600	0	0	0
T271	285020	1	0	0
T272	0	1	0	0
T273	0	1	0	0
T277	132713	0	0	0
T301	0	1	0	0
T302	0	1	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	162	0	0
T43	125007	0	0	0
T201	85434	21	0	0
T202	0	16	0	0
T203	0	17	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	17	0	0
T303	0	46	0	0
T304	0	45	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	201	0	0
T43	125007	0	0	0
T142	0	16	0	0
T143	0	16	0	0
T145	0	16	0	0
T201	85434	5	0	0
T202	0	42	0	0
T203	0	42	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	42	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0