Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.10	95.29	89.29	87.72		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	857612898	3680	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	857612898	3680	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	3680	0	0
T1	149174	2	0	0
T2	128270	2	0	0
T3	86994	1	0	0
T31	306371	4	0	0
T32	264387	2	0	0
T33	288121	4	0	0
T43	125007	0	0	0
T67	147442	2	0	0
T68	87045	1	0	0
T118	135546	2	0	0
T159	162226	1	0	0
T201	85434	5	0	0
T202	0	4	0	0
T203	0	4	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	4	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	3680	0	0
T1	149174	2	0	0
T2	128270	2	0	0
T3	86994	1	0	0
T31	306371	4	0	0
T32	264387	2	0	0
T33	288121	4	0	0
T43	125007	0	0	0
T67	147442	2	0	0
T68	87045	1	0	0
T118	135546	2	0	0
T159	162226	1	0	0
T201	85434	5	0	0
T202	0	4	0	0
T203	0	4	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	4	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	428806449	39	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	428806449	39	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	39	0	0
T43	125007	0	0	0
T201	85434	5	0	0
T202	0	4	0	0
T203	0	4	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	4	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	39	0	0
T43	125007	0	0	0
T201	85434	5	0	0
T202	0	4	0	0
T203	0	4	0	0
T211	541202	0	0	0
T242	372781	0	0	0
T251	220503	0	0	0
T275	0	4	0	0
T303	0	11	0	0
T304	0	11	0	0
T305	88925	0	0	0
T306	222929	0	0	0
T307	235512	0	0	0
T308	250666	0	0	0
T309	87008	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	428806449	3641	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	428806449	3641	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	3641	0	0
T1	149174	2	0	0
T2	128270	2	0	0
T3	86994	1	0	0
T31	306371	4	0	0
T32	264387	2	0	0
T33	288121	4	0	0
T67	147442	2	0	0
T68	87045	1	0	0
T118	135546	2	0	0
T159	162226	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	3641	0	0
T1	149174	2	0	0
T2	128270	2	0	0
T3	86994	1	0	0
T31	306371	4	0	0
T32	264387	2	0	0
T33	288121	4	0	0
T67	147442	2	0	0
T68	87045	1	0	0
T118	135546	2	0	0
T159	162226	1	0	0