Module Definition
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Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 135677468 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 20830 20830 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 135677468 0 0
T1 1909370 76470 0 0
T2 2901490 87487 0 0
T3 1945990 45973 0 0
T4 1647410 567416 0 0
T5 7411570 2016962 0 0
T34 2263530 78213 0 0
T67 2068130 64453 0 0
T91 1652090 55871 0 0
T92 659930 18970 0 0
T93 1907740 57161 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1909370 1908750 0 0
T2 2901490 2900290 0 0
T3 1945990 1944830 0 0
T4 1647410 1646700 0 0
T5 7411570 7411460 0 0
T34 2263530 2262400 0 0
T67 2068130 2067510 0 0
T91 1652090 1650930 0 0
T92 659930 659380 0 0
T93 1907740 1907160 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1909370 1908750 0 0
T2 2901490 2900290 0 0
T3 1945990 1944830 0 0
T4 1647410 1646700 0 0
T5 7411570 7411460 0 0
T34 2263530 2262400 0 0
T67 2068130 2067510 0 0
T91 1652090 1650930 0 0
T92 659930 659380 0 0
T93 1907740 1907160 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1909370 1908750 0 0
T2 2901490 2900290 0 0
T3 1945990 1944830 0 0
T4 1647410 1646700 0 0
T5 7411570 7411460 0 0
T34 2263530 2262400 0 0
T67 2068130 2067510 0 0
T91 1652090 1650930 0 0
T92 659930 659380 0 0
T93 1907740 1907160 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 20830 20830 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T4 10 10 0 0
T5 10 10 0 0
T34 10 10 0 0
T67 10 10 0 0
T91 10 10 0 0
T92 10 10 0 0
T93 10 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%