Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430652425	45025376	0	0
DepthKnown_A	430652425	430551645	0	0
RvalidKnown_A	430652425	430551645	0	0
WreadyKnown_A	430652425	430551645	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	45025376	0	0
T1	190937	27202	0	0
T2	290149	30702	0	0
T3	194599	16291	0	0
T4	164741	198768	0	0
T5	741157	476124	0	0
T34	226353	29388	0	0
T67	206813	28092	0	0
T91	165209	19138	0	0
T92	65993	6585	0	0
T93	190774	25983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430652425	34866485	0	0
DepthKnown_A	430652425	430551645	0	0
RvalidKnown_A	430652425	430551645	0	0
WreadyKnown_A	430652425	430551645	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	34866485	0	0
T1	190937	20846	0	0
T2	290149	23701	0	0
T3	194599	12019	0	0
T4	164741	151645	0	0
T5	741157	470307	0	0
T34	226353	19880	0	0
T67	206813	24226	0	0
T91	165209	13266	0	0
T92	65993	4777	0	0
T93	190774	22115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430652425	29470918	0	0
DepthKnown_A	430652425	430551645	0	0
RvalidKnown_A	430652425	430551645	0	0
WreadyKnown_A	430652425	430551645	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	29470918	0	0
T1	190937	14113	0	0
T2	290149	16508	0	0
T3	194599	8893	0	0
T4	164741	109007	0	0
T5	741157	535803	0	0
T34	226353	14365	0	0
T67	206813	6033	0	0
T91	165209	11570	0	0
T92	65993	3835	0	0
T93	190774	4497	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430652425	25954513	0	0
DepthKnown_A	430652425	430551645	0	0
RvalidKnown_A	430652425	430551645	0	0
WreadyKnown_A	430652425	430551645	0	0
gen_passthru_fifo.paramCheckPass	949	949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	25954513	0	0
T1	190937	13849	0	0
T2	290149	16168	0	0
T3	194599	8650	0	0
T4	164741	106872	0	0
T5	741157	534488	0	0
T34	226353	13976	0	0
T67	206813	5794	0	0
T91	165209	11065	0	0
T92	65993	3721	0	0
T93	190774	4258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	430551645	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	88289	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	88289	0	0
T1	190937	115	0	0
T2	290149	102	0	0
T3	194599	30	0	0
T4	164741	281	0	0
T5	741157	60	0	0
T34	226353	151	0	0
T67	206813	77	0	0
T91	165209	208	0	0
T92	65993	13	0	0
T93	190774	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	91799	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	91799	0	0
T1	190937	115	0	0
T2	290149	102	0	0
T3	194599	30	0	0
T4	164741	281	0	0
T5	741157	60	0	0
T34	226353	151	0	0
T67	206813	77	0	0
T91	165209	208	0	0
T92	65993	13	0	0
T93	190774	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	49918	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	49918	0	0
T1	190937	112	0	0
T2	290149	94	0	0
T3	194599	28	0	0
T4	164741	245	0	0
T5	741157	58	0	0
T34	226353	95	0	0
T67	206813	74	0	0
T91	165209	202	0	0
T92	65993	12	0	0
T93	190774	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	49918	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	49918	0	0
T1	190937	112	0	0
T2	290149	94	0	0
T3	194599	28	0	0
T4	164741	245	0	0
T5	741157	58	0	0
T34	226353	95	0	0
T67	206813	74	0	0
T91	165209	202	0	0
T92	65993	12	0	0
T93	190774	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	38371	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	38371	0	0
T1	190937	3	0	0
T2	290149	8	0	0
T3	194599	2	0	0
T4	164741	36	0	0
T5	741157	2	0	0
T34	226353	56	0	0
T67	206813	3	0	0
T91	165209	6	0	0
T92	65993	1	0	0
T93	190774	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494927836	41881	0	0
DepthKnown_A	494927836	494815172	0	0
RvalidKnown_A	494927836	494815172	0	0
WreadyKnown_A	494927836	494815172	0	0
gen_passthru_fifo.paramCheckPass	2839	2839	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	41881	0	0
T1	190937	3	0	0
T2	290149	8	0	0
T3	194599	2	0	0
T4	164741	36	0	0
T5	741157	2	0	0
T34	226353	56	0	0
T67	206813	3	0	0
T91	165209	6	0	0
T92	65993	1	0	0
T93	190774	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494927836	494815172	0	0
T1	190937	190875	0	0
T2	290149	290029	0	0
T3	194599	194483	0	0
T4	164741	164670	0	0
T5	741157	741146	0	0
T34	226353	226240	0	0
T67	206813	206751	0	0
T91	165209	165093	0	0
T92	65993	65938	0	0
T93	190774	190716	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2839	2839	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0