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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 95.29 93.57 95.62 94.21 97.38 99.55


Total test records in report: 2847
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T301 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1361745839 Apr 18 04:48:49 PM PDT 24 Apr 18 04:59:10 PM PDT 24 4798807300 ps
T302 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1898078529 Apr 18 04:51:34 PM PDT 24 Apr 18 04:57:20 PM PDT 24 2982792490 ps
T303 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2422992414 Apr 18 04:31:21 PM PDT 24 Apr 18 04:36:51 PM PDT 24 3604726044 ps
T304 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.537159095 Apr 18 04:44:32 PM PDT 24 Apr 18 05:23:17 PM PDT 24 12653856450 ps
T305 /workspace/coverage/default/2.chip_sw_example_flash.4047982583 Apr 18 04:33:40 PM PDT 24 Apr 18 04:37:37 PM PDT 24 2867426410 ps
T306 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3338946939 Apr 18 04:30:41 PM PDT 24 Apr 18 04:43:54 PM PDT 24 4585961400 ps
T147 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1498410766 Apr 18 04:24:43 PM PDT 24 Apr 18 05:28:23 PM PDT 24 19292375286 ps
T783 /workspace/coverage/default/45.chip_sw_all_escalation_resets.177258676 Apr 18 04:49:28 PM PDT 24 Apr 18 05:00:48 PM PDT 24 6063009104 ps
T902 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1713372108 Apr 18 04:18:28 PM PDT 24 Apr 18 04:23:20 PM PDT 24 3169528003 ps
T903 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2950787103 Apr 18 04:22:26 PM PDT 24 Apr 18 04:29:25 PM PDT 24 4274363402 ps
T45 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2461619767 Apr 18 04:30:25 PM PDT 24 Apr 18 04:51:58 PM PDT 24 20145620200 ps
T195 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.465319144 Apr 18 04:47:06 PM PDT 24 Apr 18 05:09:09 PM PDT 24 8985951540 ps
T904 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2960885278 Apr 18 04:33:48 PM PDT 24 Apr 18 04:38:46 PM PDT 24 2850974006 ps
T190 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3538599127 Apr 18 04:19:07 PM PDT 24 Apr 18 04:24:01 PM PDT 24 2751037009 ps
T7 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1486395619 Apr 18 04:22:51 PM PDT 24 Apr 18 04:28:02 PM PDT 24 3136458584 ps
T703 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3666505831 Apr 18 04:49:26 PM PDT 24 Apr 18 04:59:02 PM PDT 24 4959958330 ps
T238 /workspace/coverage/default/2.chip_sw_rv_timer_irq.786336575 Apr 18 04:38:41 PM PDT 24 Apr 18 04:42:41 PM PDT 24 2824618676 ps
T231 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3479194507 Apr 18 04:18:59 PM PDT 24 Apr 18 04:30:07 PM PDT 24 6503848232 ps
T718 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3437442863 Apr 18 04:47:07 PM PDT 24 Apr 18 04:55:27 PM PDT 24 3712157654 ps
T171 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.936279259 Apr 18 04:18:45 PM PDT 24 Apr 18 04:21:12 PM PDT 24 3155905155 ps
T713 /workspace/coverage/default/1.chip_sw_otbn_smoketest.926425408 Apr 18 04:33:38 PM PDT 24 Apr 18 05:03:51 PM PDT 24 7969294432 ps
T196 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2655184661 Apr 18 04:44:05 PM PDT 24 Apr 18 04:54:36 PM PDT 24 4268801848 ps
T313 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.679742379 Apr 18 04:17:18 PM PDT 24 Apr 18 04:30:40 PM PDT 24 4856275080 ps
T650 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.32562025 Apr 18 04:24:54 PM PDT 24 Apr 18 04:26:37 PM PDT 24 2456414399 ps
T667 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1019739737 Apr 18 04:18:04 PM PDT 24 Apr 18 04:28:50 PM PDT 24 3859912678 ps
T905 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1900267596 Apr 18 04:22:01 PM PDT 24 Apr 18 04:27:52 PM PDT 24 3158832488 ps
T754 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.214148467 Apr 18 04:46:10 PM PDT 24 Apr 18 04:53:45 PM PDT 24 4022282870 ps
T223 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1231666245 Apr 18 04:35:46 PM PDT 24 Apr 18 06:04:30 PM PDT 24 48137679798 ps
T205 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3474118590 Apr 18 04:29:09 PM PDT 24 Apr 18 04:40:04 PM PDT 24 5108688628 ps
T33 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4116367050 Apr 18 04:20:15 PM PDT 24 Apr 18 04:32:05 PM PDT 24 5083943604 ps
T906 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2393890476 Apr 18 04:43:57 PM PDT 24 Apr 18 04:50:26 PM PDT 24 4214091273 ps
T907 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4288718092 Apr 18 04:39:49 PM PDT 24 Apr 18 04:46:43 PM PDT 24 3362180934 ps
T908 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1497156068 Apr 18 04:25:10 PM PDT 24 Apr 18 04:33:08 PM PDT 24 6648849564 ps
T36 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2182880306 Apr 18 04:34:49 PM PDT 24 Apr 18 04:40:17 PM PDT 24 3269240418 ps
T164 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4177280718 Apr 18 04:50:23 PM PDT 24 Apr 18 05:02:01 PM PDT 24 5984358000 ps
T715 /workspace/coverage/default/84.chip_sw_all_escalation_resets.4067829103 Apr 18 04:52:37 PM PDT 24 Apr 18 05:02:40 PM PDT 24 5089616704 ps
T909 /workspace/coverage/default/1.chip_sw_kmac_entropy.3719580825 Apr 18 04:24:11 PM PDT 24 Apr 18 04:29:15 PM PDT 24 3469351830 ps
T910 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.674315641 Apr 18 04:27:28 PM PDT 24 Apr 18 05:10:59 PM PDT 24 12327954786 ps
T911 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1800080257 Apr 18 04:42:49 PM PDT 24 Apr 18 04:47:52 PM PDT 24 3323639320 ps
T912 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.335632607 Apr 18 04:50:04 PM PDT 24 Apr 18 04:55:12 PM PDT 24 2574287028 ps
T159 /workspace/coverage/default/51.chip_sw_all_escalation_resets.4200632313 Apr 18 04:49:18 PM PDT 24 Apr 18 04:57:23 PM PDT 24 4668577344 ps
T369 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3315387658 Apr 18 04:26:39 PM PDT 24 Apr 18 04:58:59 PM PDT 24 6600661616 ps
T372 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3642873358 Apr 18 04:36:50 PM PDT 24 Apr 18 05:05:24 PM PDT 24 7201131872 ps
T271 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2841773882 Apr 18 04:44:20 PM PDT 24 Apr 18 04:58:51 PM PDT 24 5119573136 ps
T913 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2844606451 Apr 18 04:35:13 PM PDT 24 Apr 18 04:53:10 PM PDT 24 5772313824 ps
T709 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2815837460 Apr 18 04:52:18 PM PDT 24 Apr 18 04:58:41 PM PDT 24 3863234016 ps
T702 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1165414335 Apr 18 04:51:49 PM PDT 24 Apr 18 05:02:41 PM PDT 24 4367853246 ps
T914 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4167432407 Apr 18 04:26:57 PM PDT 24 Apr 18 05:02:42 PM PDT 24 7663015576 ps
T132 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3885243846 Apr 18 04:27:49 PM PDT 24 Apr 18 04:34:39 PM PDT 24 5328158040 ps
T21 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1379943868 Apr 18 04:17:54 PM PDT 24 Apr 18 05:14:39 PM PDT 24 21087581801 ps
T915 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3032421418 Apr 18 04:52:35 PM PDT 24 Apr 18 05:02:34 PM PDT 24 6151899940 ps
T780 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2599850457 Apr 18 04:50:37 PM PDT 24 Apr 18 04:58:53 PM PDT 24 5718804580 ps
T916 /workspace/coverage/default/1.chip_sw_aes_idle.3573651745 Apr 18 04:27:14 PM PDT 24 Apr 18 04:31:26 PM PDT 24 3298151952 ps
T917 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4019746763 Apr 18 04:17:51 PM PDT 24 Apr 18 04:22:20 PM PDT 24 2658376389 ps
T918 /workspace/coverage/default/2.chip_sw_example_concurrency.1451973972 Apr 18 04:35:23 PM PDT 24 Apr 18 04:40:07 PM PDT 24 2981751030 ps
T919 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3626681305 Apr 18 04:33:39 PM PDT 24 Apr 18 04:38:32 PM PDT 24 2944581216 ps
T208 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.683613531 Apr 18 04:40:36 PM PDT 24 Apr 18 04:49:04 PM PDT 24 4954978434 ps
T920 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1787837228 Apr 18 04:48:35 PM PDT 24 Apr 18 04:57:31 PM PDT 24 6034605368 ps
T921 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3014422335 Apr 18 04:18:27 PM PDT 24 Apr 18 05:10:00 PM PDT 24 28032911058 ps
T922 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3396411368 Apr 18 04:39:33 PM PDT 24 Apr 18 04:46:02 PM PDT 24 3764923544 ps
T160 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2838698853 Apr 18 04:20:26 PM PDT 24 Apr 18 04:24:48 PM PDT 24 2472360316 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.813249911 Apr 18 04:34:56 PM PDT 24 Apr 18 04:40:34 PM PDT 24 3271451409 ps
T197 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2110530995 Apr 18 04:43:27 PM PDT 24 Apr 18 04:52:59 PM PDT 24 3674110732 ps
T211 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1854210671 Apr 18 04:18:48 PM PDT 24 Apr 18 04:28:55 PM PDT 24 4392166248 ps
T154 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3320717191 Apr 18 04:50:20 PM PDT 24 Apr 18 04:56:07 PM PDT 24 3755682544 ps
T343 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1495805695 Apr 18 04:52:36 PM PDT 24 Apr 18 05:01:11 PM PDT 24 5013400500 ps
T192 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.204179277 Apr 18 04:35:55 PM PDT 24 Apr 18 04:45:50 PM PDT 24 4006474364 ps
T62 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2770221484 Apr 18 04:23:17 PM PDT 24 Apr 18 04:30:42 PM PDT 24 5907192992 ps
T704 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.482174026 Apr 18 04:47:08 PM PDT 24 Apr 18 04:54:09 PM PDT 24 4009010856 ps
T923 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2339647247 Apr 18 04:46:50 PM PDT 24 Apr 18 05:09:50 PM PDT 24 7995128182 ps
T924 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2659242188 Apr 18 04:17:27 PM PDT 24 Apr 18 04:28:47 PM PDT 24 5007236920 ps
T705 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3112209987 Apr 18 04:50:58 PM PDT 24 Apr 18 04:58:04 PM PDT 24 3962270860 ps
T212 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1258461115 Apr 18 04:20:25 PM PDT 24 Apr 18 04:30:40 PM PDT 24 4555232002 ps
T198 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2434802202 Apr 18 04:18:36 PM PDT 24 Apr 18 04:30:34 PM PDT 24 4071119500 ps
T925 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2875862917 Apr 18 04:24:11 PM PDT 24 Apr 18 04:37:56 PM PDT 24 6923661704 ps
T308 /workspace/coverage/default/0.chip_plic_all_irqs_0.4177159536 Apr 18 04:19:40 PM PDT 24 Apr 18 04:37:56 PM PDT 24 6097056604 ps
T926 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2770920064 Apr 18 04:20:42 PM PDT 24 Apr 18 04:25:14 PM PDT 24 2848948464 ps
T638 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2049434642 Apr 18 04:37:24 PM PDT 24 Apr 18 04:56:15 PM PDT 24 4739860740 ps
T927 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2638507688 Apr 18 04:35:35 PM PDT 24 Apr 18 05:01:01 PM PDT 24 12627585559 ps
T928 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1881907778 Apr 18 04:36:06 PM PDT 24 Apr 18 04:43:33 PM PDT 24 4086265070 ps
T929 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1526386113 Apr 18 04:23:02 PM PDT 24 Apr 18 04:41:13 PM PDT 24 5382359712 ps
T930 /workspace/coverage/default/4.chip_tap_straps_rma.1007515255 Apr 18 04:43:38 PM PDT 24 Apr 18 04:48:45 PM PDT 24 3962768071 ps
T245 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3738714293 Apr 18 04:49:52 PM PDT 24 Apr 18 04:56:02 PM PDT 24 3327308784 ps
T931 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2195418196 Apr 18 04:52:17 PM PDT 24 Apr 18 05:01:45 PM PDT 24 5960350360 ps
T312 /workspace/coverage/default/0.chip_plic_all_irqs_20.870707094 Apr 18 04:18:18 PM PDT 24 Apr 18 04:32:42 PM PDT 24 4928369044 ps
T79 /workspace/coverage/default/0.chip_jtag_csr_rw.3908705965 Apr 18 04:11:08 PM PDT 24 Apr 18 04:57:49 PM PDT 24 19706704962 ps
T696 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.756867417 Apr 18 04:52:17 PM PDT 24 Apr 18 04:58:25 PM PDT 24 3275349400 ps
T932 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.807179483 Apr 18 04:21:31 PM PDT 24 Apr 18 04:40:34 PM PDT 24 6973904488 ps
T933 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3092304387 Apr 18 04:25:03 PM PDT 24 Apr 18 04:34:03 PM PDT 24 6924792108 ps
T46 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3949402183 Apr 18 04:18:00 PM PDT 24 Apr 18 04:23:26 PM PDT 24 3186750920 ps
T83 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107501071 Apr 18 04:48:02 PM PDT 24 Apr 18 04:54:57 PM PDT 24 3228103700 ps
T92 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2741217637 Apr 18 04:25:19 PM PDT 24 Apr 18 04:37:29 PM PDT 24 6978076865 ps
T93 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1891375337 Apr 18 04:27:21 PM PDT 24 Apr 18 04:30:42 PM PDT 24 2840898648 ps
T94 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.29115265 Apr 18 04:36:09 PM PDT 24 Apr 18 04:46:18 PM PDT 24 8968024740 ps
T95 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1691951196 Apr 18 04:28:48 PM PDT 24 Apr 18 04:32:45 PM PDT 24 2752218462 ps
T96 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2571937484 Apr 18 04:26:31 PM PDT 24 Apr 18 04:38:44 PM PDT 24 5886222580 ps
T89 /workspace/coverage/default/13.chip_sw_all_escalation_resets.4130606638 Apr 18 04:45:28 PM PDT 24 Apr 18 04:56:01 PM PDT 24 6224681780 ps
T97 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.378754312 Apr 18 04:30:51 PM PDT 24 Apr 18 04:38:55 PM PDT 24 4414267496 ps
T98 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2581598686 Apr 18 04:43:10 PM PDT 24 Apr 18 04:51:04 PM PDT 24 5981247724 ps
T99 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3710735089 Apr 18 04:26:12 PM PDT 24 Apr 18 05:00:58 PM PDT 24 9835654400 ps
T655 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3164726755 Apr 18 04:45:11 PM PDT 24 Apr 18 04:56:22 PM PDT 24 6013614492 ps
T934 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.703521034 Apr 18 04:28:09 PM PDT 24 Apr 18 04:33:46 PM PDT 24 3055675168 ps
T48 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1000021885 Apr 18 04:39:50 PM PDT 24 Apr 18 04:45:28 PM PDT 24 3991851296 ps
T935 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383398679 Apr 18 04:51:48 PM PDT 24 Apr 18 04:59:42 PM PDT 24 3843360160 ps
T936 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1010922759 Apr 18 04:19:11 PM PDT 24 Apr 18 05:06:02 PM PDT 24 11243314928 ps
T937 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.299467429 Apr 18 04:48:15 PM PDT 24 Apr 18 04:54:31 PM PDT 24 3364606240 ps
T360 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2811661870 Apr 18 04:38:04 PM PDT 24 Apr 18 04:48:09 PM PDT 24 2977589668 ps
T639 /workspace/coverage/default/1.chip_sw_edn_auto_mode.4056812732 Apr 18 04:26:59 PM PDT 24 Apr 18 04:45:16 PM PDT 24 5112189980 ps
T938 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3131018004 Apr 18 04:38:26 PM PDT 24 Apr 18 04:49:34 PM PDT 24 7712365220 ps
T939 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1593214814 Apr 18 04:26:05 PM PDT 24 Apr 18 05:27:21 PM PDT 24 15146108555 ps
T940 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.220186977 Apr 18 04:23:20 PM PDT 24 Apr 18 05:18:14 PM PDT 24 34284609648 ps
T52 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.518143241 Apr 18 04:33:05 PM PDT 24 Apr 18 04:39:18 PM PDT 24 4091444492 ps
T701 /workspace/coverage/default/39.chip_sw_all_escalation_resets.799597995 Apr 18 04:48:55 PM PDT 24 Apr 18 04:59:01 PM PDT 24 5780596584 ps
T210 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2116355555 Apr 18 04:26:49 PM PDT 24 Apr 18 04:35:09 PM PDT 24 5411123724 ps
T700 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2809691014 Apr 18 04:51:59 PM PDT 24 Apr 18 04:57:33 PM PDT 24 3383462016 ps
T941 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1715020637 Apr 18 04:50:59 PM PDT 24 Apr 18 04:57:20 PM PDT 24 4102677816 ps
T942 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4053621503 Apr 18 04:38:30 PM PDT 24 Apr 18 04:46:26 PM PDT 24 4168435996 ps
T771 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2194427507 Apr 18 04:49:35 PM PDT 24 Apr 18 04:58:45 PM PDT 24 5471744360 ps
T943 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3538586920 Apr 18 04:31:48 PM PDT 24 Apr 18 04:40:58 PM PDT 24 4153831640 ps
T944 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1175409310 Apr 18 04:37:55 PM PDT 24 Apr 18 05:17:07 PM PDT 24 10928980656 ps
T148 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2212984752 Apr 18 04:33:20 PM PDT 24 Apr 18 07:26:15 PM PDT 24 59439576972 ps
T50 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1897981318 Apr 18 04:35:03 PM PDT 24 Apr 18 04:42:25 PM PDT 24 3960980464 ps
T945 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.827837750 Apr 18 04:25:06 PM PDT 24 Apr 18 05:06:28 PM PDT 24 8968105636 ps
T946 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2320448768 Apr 18 04:25:45 PM PDT 24 Apr 18 04:41:57 PM PDT 24 7182839128 ps
T947 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3261150424 Apr 18 04:16:50 PM PDT 24 Apr 18 04:28:08 PM PDT 24 4263920400 ps
T948 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1679710792 Apr 18 04:19:01 PM PDT 24 Apr 18 04:39:18 PM PDT 24 8019408906 ps
T374 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.328225855 Apr 18 04:28:42 PM PDT 24 Apr 18 05:41:23 PM PDT 24 18312661694 ps
T949 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1981664014 Apr 18 04:26:02 PM PDT 24 Apr 18 05:14:32 PM PDT 24 12029144340 ps
T950 /workspace/coverage/default/1.rom_keymgr_functest.2952288235 Apr 18 04:32:22 PM PDT 24 Apr 18 04:43:39 PM PDT 24 3909542078 ps
T951 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3056114594 Apr 18 04:18:56 PM PDT 24 Apr 18 04:45:49 PM PDT 24 12219293502 ps
T717 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2513857325 Apr 18 04:48:36 PM PDT 24 Apr 18 04:54:08 PM PDT 24 3541938600 ps
T236 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3681795929 Apr 18 04:27:48 PM PDT 24 Apr 18 04:31:58 PM PDT 24 2659385200 ps
T787 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1262641464 Apr 18 04:49:35 PM PDT 24 Apr 18 05:03:19 PM PDT 24 5576031856 ps
T179 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2192398045 Apr 18 04:41:08 PM PDT 24 Apr 18 04:52:54 PM PDT 24 9838965390 ps
T84 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3584867931 Apr 18 04:18:35 PM PDT 24 Apr 18 04:46:08 PM PDT 24 12216942920 ps
T952 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3121072091 Apr 18 04:39:53 PM PDT 24 Apr 18 04:50:46 PM PDT 24 3974836472 ps
T953 /workspace/coverage/default/46.chip_sw_all_escalation_resets.793231456 Apr 18 04:49:06 PM PDT 24 Apr 18 04:59:55 PM PDT 24 4915791402 ps
T954 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2726871506 Apr 18 04:24:34 PM PDT 24 Apr 18 04:38:00 PM PDT 24 7296498040 ps
T710 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348061756 Apr 18 04:48:38 PM PDT 24 Apr 18 04:56:18 PM PDT 24 3532847176 ps
T955 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.494829965 Apr 18 04:32:43 PM PDT 24 Apr 18 04:40:44 PM PDT 24 3428067288 ps
T956 /workspace/coverage/default/2.chip_tap_straps_testunlock0.786683358 Apr 18 04:39:10 PM PDT 24 Apr 18 04:51:16 PM PDT 24 7111847366 ps
T318 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3763336772 Apr 18 04:23:20 PM PDT 24 Apr 18 04:36:37 PM PDT 24 4847878158 ps
T957 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2198078811 Apr 18 04:40:21 PM PDT 24 Apr 18 04:46:09 PM PDT 24 3119595800 ps
T184 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.62566861 Apr 18 04:27:47 PM PDT 24 Apr 18 04:36:43 PM PDT 24 7305210556 ps
T642 /workspace/coverage/default/0.chip_sw_edn_kat.4108207583 Apr 18 04:17:46 PM PDT 24 Apr 18 04:27:25 PM PDT 24 3756352984 ps
T958 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2874439944 Apr 18 04:33:45 PM PDT 24 Apr 18 07:54:02 PM PDT 24 64021339345 ps
T719 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1402141905 Apr 18 04:47:59 PM PDT 24 Apr 18 04:56:12 PM PDT 24 4253210730 ps
T756 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3053710420 Apr 18 04:50:25 PM PDT 24 Apr 18 05:00:50 PM PDT 24 5972644600 ps
T959 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.962625717 Apr 18 04:35:17 PM PDT 24 Apr 18 04:41:43 PM PDT 24 3374892004 ps
T651 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2715337288 Apr 18 04:35:30 PM PDT 24 Apr 18 04:37:06 PM PDT 24 2842282437 ps
T706 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3812229719 Apr 18 04:49:19 PM PDT 24 Apr 18 04:55:33 PM PDT 24 2957584576 ps
T652 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2308021970 Apr 18 04:24:54 PM PDT 24 Apr 18 04:26:57 PM PDT 24 2579148895 ps
T59 /workspace/coverage/default/1.chip_sw_alert_test.2864455694 Apr 18 04:26:18 PM PDT 24 Apr 18 04:31:05 PM PDT 24 2999482400 ps
T960 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1300279093 Apr 18 04:48:48 PM PDT 24 Apr 18 05:07:26 PM PDT 24 13077179913 ps
T232 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1287319675 Apr 18 04:25:42 PM PDT 24 Apr 18 04:41:27 PM PDT 24 6047512326 ps
T961 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2566539963 Apr 18 04:19:03 PM PDT 24 Apr 18 04:39:11 PM PDT 24 9733801876 ps
T193 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.981429171 Apr 18 04:24:21 PM PDT 24 Apr 18 04:56:31 PM PDT 24 24485583010 ps
T962 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1665384268 Apr 18 04:46:48 PM PDT 24 Apr 18 05:19:25 PM PDT 24 12855785558 ps
T963 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.396384551 Apr 18 04:17:37 PM PDT 24 Apr 18 04:47:58 PM PDT 24 7654028676 ps
T653 /workspace/coverage/default/1.rom_volatile_raw_unlock.3160675881 Apr 18 04:33:10 PM PDT 24 Apr 18 04:34:58 PM PDT 24 2573048956 ps
T707 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2559983673 Apr 18 04:45:25 PM PDT 24 Apr 18 04:51:11 PM PDT 24 3424787840 ps
T964 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1069302169 Apr 18 04:22:49 PM PDT 24 Apr 18 04:27:34 PM PDT 24 2644891580 ps
T741 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221528636 Apr 18 04:44:18 PM PDT 24 Apr 18 04:51:20 PM PDT 24 3738159458 ps
T965 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1918371287 Apr 18 04:33:56 PM PDT 24 Apr 18 04:43:24 PM PDT 24 5986076664 ps
T966 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3062453419 Apr 18 04:18:51 PM PDT 24 Apr 18 04:23:31 PM PDT 24 2724675320 ps
T788 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.140098721 Apr 18 04:50:36 PM PDT 24 Apr 18 04:57:48 PM PDT 24 3455330344 ps
T967 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2200805373 Apr 18 04:27:31 PM PDT 24 Apr 18 05:40:15 PM PDT 24 18162331600 ps
T224 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1630601871 Apr 18 04:19:40 PM PDT 24 Apr 18 04:49:21 PM PDT 24 23115760223 ps
T968 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3252042011 Apr 18 04:40:35 PM PDT 24 Apr 18 04:52:39 PM PDT 24 8650650850 ps
T969 /workspace/coverage/default/1.chip_tap_straps_prod.2673236709 Apr 18 04:29:59 PM PDT 24 Apr 18 04:32:59 PM PDT 24 3286383109 ps
T970 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3158187558 Apr 18 04:25:12 PM PDT 24 Apr 18 04:41:19 PM PDT 24 5961035264 ps
T189 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.537936473 Apr 18 04:18:47 PM PDT 24 Apr 18 04:28:01 PM PDT 24 4286601986 ps
T971 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1176053956 Apr 18 04:20:41 PM PDT 24 Apr 18 04:32:21 PM PDT 24 8792180950 ps
T656 /workspace/coverage/default/0.chip_sw_power_idle_load.3993038675 Apr 18 04:21:48 PM PDT 24 Apr 18 04:33:01 PM PDT 24 4234507832 ps
T972 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2255645103 Apr 18 04:23:57 PM PDT 24 Apr 18 04:33:27 PM PDT 24 5199994184 ps
T53 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.365152053 Apr 18 04:43:27 PM PDT 24 Apr 18 04:50:55 PM PDT 24 7187182932 ps
T775 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3750170174 Apr 18 04:51:03 PM PDT 24 Apr 18 05:03:30 PM PDT 24 6402128886 ps
T973 /workspace/coverage/default/28.chip_sw_all_escalation_resets.399605890 Apr 18 04:48:08 PM PDT 24 Apr 18 04:59:54 PM PDT 24 4613275464 ps
T199 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2835494552 Apr 18 04:48:53 PM PDT 24 Apr 18 05:02:16 PM PDT 24 4774731510 ps
T770 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2411752452 Apr 18 04:48:16 PM PDT 24 Apr 18 04:57:19 PM PDT 24 4225728748 ps
T310 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3813633424 Apr 18 04:25:12 PM PDT 24 Apr 18 04:36:59 PM PDT 24 4518711388 ps
T974 /workspace/coverage/default/0.chip_sw_aes_masking_off.2216643465 Apr 18 04:21:23 PM PDT 24 Apr 18 04:26:26 PM PDT 24 3148609333 ps
T690 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2409846002 Apr 18 04:18:05 PM PDT 24 Apr 18 04:51:03 PM PDT 24 22335886840 ps
T975 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2087918295 Apr 18 04:46:53 PM PDT 24 Apr 18 05:26:19 PM PDT 24 10539318762 ps
T209 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2805112115 Apr 18 04:30:26 PM PDT 24 Apr 18 04:41:25 PM PDT 24 5210992722 ps
T648 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1277925893 Apr 18 04:22:47 PM PDT 24 Apr 18 04:33:33 PM PDT 24 4944735345 ps
T976 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1651112394 Apr 18 04:52:02 PM PDT 24 Apr 18 05:00:44 PM PDT 24 5067579408 ps
T298 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3043184362 Apr 18 04:48:51 PM PDT 24 Apr 18 04:56:15 PM PDT 24 3395450154 ps
T977 /workspace/coverage/default/1.chip_sw_csrng_smoketest.3007699014 Apr 18 04:32:34 PM PDT 24 Apr 18 04:35:43 PM PDT 24 2535769476 ps
T978 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1897437947 Apr 18 04:21:02 PM PDT 24 Apr 18 04:27:25 PM PDT 24 4527544362 ps
T654 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.283018215 Apr 18 04:18:43 PM PDT 24 Apr 18 04:21:06 PM PDT 24 2832712908 ps
T979 /workspace/coverage/default/2.chip_sw_kmac_entropy.1732616743 Apr 18 04:35:35 PM PDT 24 Apr 18 04:40:12 PM PDT 24 3361526566 ps
T430 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1230565125 Apr 18 04:17:44 PM PDT 24 Apr 18 04:21:59 PM PDT 24 3344877284 ps
T352 /workspace/coverage/default/36.chip_sw_all_escalation_resets.4177485435 Apr 18 04:49:02 PM PDT 24 Apr 18 05:00:07 PM PDT 24 6244339240 ps
T307 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1776341944 Apr 18 04:24:05 PM PDT 24 Apr 18 04:46:58 PM PDT 24 10538078360 ps
T272 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3973730169 Apr 18 04:26:21 PM PDT 24 Apr 18 04:35:48 PM PDT 24 3368407992 ps
T980 /workspace/coverage/default/1.chip_sw_example_rom.2748983077 Apr 18 04:23:09 PM PDT 24 Apr 18 04:25:24 PM PDT 24 2239961716 ps
T353 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1268980490 Apr 18 04:16:52 PM PDT 24 Apr 18 04:26:14 PM PDT 24 5760523926 ps
T392 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1388993525 Apr 18 04:44:11 PM PDT 24 Apr 18 04:52:23 PM PDT 24 6239501254 ps
T731 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2050069550 Apr 18 04:49:26 PM PDT 24 Apr 18 04:59:22 PM PDT 24 5203683624 ps
T728 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3292179125 Apr 18 04:52:03 PM PDT 24 Apr 18 05:02:59 PM PDT 24 6359092392 ps
T781 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4005266590 Apr 18 04:51:13 PM PDT 24 Apr 18 04:57:16 PM PDT 24 3455161496 ps
T354 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1909090863 Apr 18 04:19:37 PM PDT 24 Apr 18 04:23:58 PM PDT 24 2873391109 ps
T319 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2396992199 Apr 18 04:35:44 PM PDT 24 Apr 18 04:49:34 PM PDT 24 5035312738 ps
T981 /workspace/coverage/default/2.chip_sw_edn_kat.201481522 Apr 18 04:38:22 PM PDT 24 Apr 18 04:49:46 PM PDT 24 3607862380 ps
T153 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3289902667 Apr 18 04:37:40 PM PDT 24 Apr 18 04:44:05 PM PDT 24 4085342447 ps
T982 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3259965768 Apr 18 04:45:10 PM PDT 24 Apr 18 04:54:40 PM PDT 24 3468466696 ps
T983 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1680379956 Apr 18 04:24:45 PM PDT 24 Apr 18 04:36:17 PM PDT 24 4556209980 ps
T90 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784314735 Apr 18 04:54:46 PM PDT 24 Apr 18 05:00:28 PM PDT 24 3141948696 ps
T984 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4067936173 Apr 18 04:25:02 PM PDT 24 Apr 18 04:43:01 PM PDT 24 5592437912 ps
T341 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3223715504 Apr 18 04:17:58 PM PDT 24 Apr 18 04:27:09 PM PDT 24 3570852114 ps
T985 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.399697669 Apr 18 04:19:48 PM PDT 24 Apr 18 04:23:57 PM PDT 24 3289819629 ps
T986 /workspace/coverage/default/0.chip_sw_aes_enc.3424230579 Apr 18 04:19:30 PM PDT 24 Apr 18 04:24:08 PM PDT 24 2730257672 ps
T987 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1662324037 Apr 18 04:35:36 PM PDT 24 Apr 18 04:43:56 PM PDT 24 7052900352 ps
T988 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.842042693 Apr 18 04:18:02 PM PDT 24 Apr 18 04:29:49 PM PDT 24 6862570774 ps
T329 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3073568852 Apr 18 04:43:17 PM PDT 24 Apr 18 04:54:08 PM PDT 24 4429168136 ps
T989 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2832396127 Apr 18 04:43:37 PM PDT 24 Apr 18 04:54:46 PM PDT 24 4116528670 ps
T990 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3895538168 Apr 18 04:17:02 PM PDT 24 Apr 18 04:53:29 PM PDT 24 21214526818 ps
T991 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3203617621 Apr 18 04:32:17 PM PDT 24 Apr 18 04:38:26 PM PDT 24 3191605496 ps
T992 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2695119383 Apr 18 04:28:17 PM PDT 24 Apr 18 05:06:55 PM PDT 24 9204182812 ps
T993 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.29098429 Apr 18 04:35:41 PM PDT 24 Apr 18 04:39:00 PM PDT 24 2615791700 ps
T744 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2365390390 Apr 18 04:49:30 PM PDT 24 Apr 18 04:58:19 PM PDT 24 4131356960 ps
T994 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1446322205 Apr 18 04:47:08 PM PDT 24 Apr 18 04:55:10 PM PDT 24 4382350910 ps
T161 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2481966600 Apr 18 04:24:09 PM PDT 24 Apr 18 04:25:42 PM PDT 24 1933832101 ps
T776 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1691672297 Apr 18 04:48:56 PM PDT 24 Apr 18 04:55:07 PM PDT 24 3072106984 ps
T740 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465604377 Apr 18 04:51:01 PM PDT 24 Apr 18 04:56:30 PM PDT 24 3322742408 ps
T672 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2766276996 Apr 18 04:26:01 PM PDT 24 Apr 18 04:31:41 PM PDT 24 2665481334 ps
T222 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1483751180 Apr 18 04:19:27 PM PDT 24 Apr 18 05:49:27 PM PDT 24 50578063210 ps
T778 /workspace/coverage/default/94.chip_sw_all_escalation_resets.442653409 Apr 18 04:53:24 PM PDT 24 Apr 18 05:06:09 PM PDT 24 5113021714 ps
T682 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3243849007 Apr 18 04:24:26 PM PDT 24 Apr 18 04:47:46 PM PDT 24 8718085752 ps
T995 /workspace/coverage/default/1.chip_sw_aes_enc.2228997287 Apr 18 04:26:01 PM PDT 24 Apr 18 04:30:58 PM PDT 24 2831256184 ps
T996 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2144313368 Apr 18 04:36:38 PM PDT 24 Apr 18 05:29:35 PM PDT 24 15140311345 ps
T997 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1338749615 Apr 18 04:41:22 PM PDT 24 Apr 18 04:44:56 PM PDT 24 2702743599 ps
T998 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1949286316 Apr 18 04:45:48 PM PDT 24 Apr 18 05:16:41 PM PDT 24 13306825232 ps
T683 /workspace/coverage/default/1.chip_sw_power_sleep_load.3399505695 Apr 18 04:31:30 PM PDT 24 Apr 18 04:41:23 PM PDT 24 9039466006 ps
T216 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2392230518 Apr 18 04:19:50 PM PDT 24 Apr 18 04:29:14 PM PDT 24 5111065988 ps
T999 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1894115906 Apr 18 04:28:06 PM PDT 24 Apr 18 05:22:11 PM PDT 24 14042414180 ps
T1000 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2608472616 Apr 18 04:19:24 PM PDT 24 Apr 18 04:31:42 PM PDT 24 5477036880 ps
T789 /workspace/coverage/default/98.chip_sw_all_escalation_resets.629227431 Apr 18 04:53:19 PM PDT 24 Apr 18 05:03:49 PM PDT 24 5635536950 ps
T1001 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.688331753 Apr 18 04:33:21 PM PDT 24 Apr 18 04:37:10 PM PDT 24 3283793168 ps
T1002 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1510424657 Apr 18 04:24:15 PM PDT 24 Apr 18 04:33:41 PM PDT 24 4742178280 ps
T1003 /workspace/coverage/default/2.rom_keymgr_functest.1384648381 Apr 18 04:44:01 PM PDT 24 Apr 18 04:52:56 PM PDT 24 5325475222 ps
T649 /workspace/coverage/default/3.chip_tap_straps_dev.3031622109 Apr 18 04:51:32 PM PDT 24 Apr 18 05:07:59 PM PDT 24 11247463914 ps
T247 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3855823463 Apr 18 04:50:47 PM PDT 24 Apr 18 04:58:43 PM PDT 24 4456952748 ps
T91 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3527026325 Apr 18 04:44:08 PM PDT 24 Apr 18 04:53:06 PM PDT 24 4645012380 ps
T1004 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3932109370 Apr 18 04:40:22 PM PDT 24 Apr 18 04:50:49 PM PDT 24 3602165630 ps
T1005 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1595975287 Apr 18 04:24:24 PM PDT 24 Apr 18 04:50:44 PM PDT 24 14480439440 ps
T1006 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2892195178 Apr 18 04:32:30 PM PDT 24 Apr 18 04:52:41 PM PDT 24 7291998871 ps
T1007 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2042871083 Apr 18 04:40:12 PM PDT 24 Apr 18 04:49:38 PM PDT 24 6487212600 ps
T1008 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2451032439 Apr 18 04:17:15 PM PDT 24 Apr 18 04:24:29 PM PDT 24 5193511528 ps
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