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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 95.29 93.57 95.62 94.21 97.38 99.55


Total test records in report: 2847
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T1135 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3096515311 Apr 18 04:34:57 PM PDT 24 Apr 18 04:46:24 PM PDT 24 4126403816 ps
T1136 /workspace/coverage/default/0.chip_sival_flash_info_access.4037657730 Apr 18 04:16:38 PM PDT 24 Apr 18 04:21:57 PM PDT 24 3264310216 ps
T1137 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1265493063 Apr 18 04:26:08 PM PDT 24 Apr 18 04:35:57 PM PDT 24 3860344824 ps
T1138 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1249140900 Apr 18 04:24:41 PM PDT 24 Apr 18 04:48:44 PM PDT 24 9323532850 ps
T1139 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098776079 Apr 18 04:46:18 PM PDT 24 Apr 18 04:52:52 PM PDT 24 4079424514 ps
T1140 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3534317806 Apr 18 04:28:21 PM PDT 24 Apr 18 04:57:55 PM PDT 24 8653276736 ps
T1141 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2042419222 Apr 18 04:41:09 PM PDT 24 Apr 18 04:59:14 PM PDT 24 6041952296 ps
T1142 /workspace/coverage/default/1.chip_sw_uart_smoketest.1963536930 Apr 18 04:34:48 PM PDT 24 Apr 18 04:40:12 PM PDT 24 2769902708 ps
T1143 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3181558924 Apr 18 04:20:39 PM PDT 24 Apr 18 04:30:31 PM PDT 24 4864829125 ps
T1144 /workspace/coverage/default/2.chip_sw_uart_tx_rx.4181775926 Apr 18 04:35:02 PM PDT 24 Apr 18 04:49:31 PM PDT 24 4402598620 ps
T291 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.833634471 Apr 18 04:19:52 PM PDT 24 Apr 18 04:36:03 PM PDT 24 8869248085 ps
T785 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3909491629 Apr 18 04:53:24 PM PDT 24 Apr 18 05:02:01 PM PDT 24 5185509936 ps
T758 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361979981 Apr 18 04:53:03 PM PDT 24 Apr 18 04:57:59 PM PDT 24 3443520214 ps
T1145 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1103659027 Apr 18 04:18:09 PM PDT 24 Apr 18 04:33:18 PM PDT 24 7921315426 ps
T1146 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3635687222 Apr 18 04:27:37 PM PDT 24 Apr 18 05:26:47 PM PDT 24 13175888417 ps
T1147 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3533854240 Apr 18 04:26:49 PM PDT 24 Apr 18 04:32:02 PM PDT 24 2739465696 ps
T1148 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1252463094 Apr 18 04:32:33 PM PDT 24 Apr 18 04:35:20 PM PDT 24 2918162230 ps
T1149 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2278823921 Apr 18 04:35:44 PM PDT 24 Apr 18 04:58:39 PM PDT 24 8195798840 ps
T218 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2226676933 Apr 18 04:39:49 PM PDT 24 Apr 18 05:34:06 PM PDT 24 14553940720 ps
T733 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2207590560 Apr 18 04:53:28 PM PDT 24 Apr 18 05:03:11 PM PDT 24 4267056452 ps
T227 /workspace/coverage/default/2.chip_sw_flash_init.3062331577 Apr 18 04:34:13 PM PDT 24 Apr 18 05:25:18 PM PDT 24 18875974001 ps
T1150 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2614228094 Apr 18 04:24:36 PM PDT 24 Apr 18 04:37:06 PM PDT 24 6029512517 ps
T1151 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1912831906 Apr 18 04:21:02 PM PDT 24 Apr 18 04:40:47 PM PDT 24 5563211992 ps
T1152 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1354201953 Apr 18 04:35:22 PM PDT 24 Apr 18 04:38:46 PM PDT 24 2578299892 ps
T1153 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2140029694 Apr 18 04:42:52 PM PDT 24 Apr 18 05:13:47 PM PDT 24 9958756384 ps
T1154 /workspace/coverage/default/0.chip_sw_power_sleep_load.2245904951 Apr 18 04:19:17 PM PDT 24 Apr 18 04:29:44 PM PDT 24 10728133272 ps
T1155 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2039350779 Apr 18 04:27:53 PM PDT 24 Apr 18 04:35:05 PM PDT 24 4828455320 ps
T1156 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3446616226 Apr 18 04:23:03 PM PDT 24 Apr 18 05:03:23 PM PDT 24 13434537632 ps
T228 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3581577119 Apr 18 04:24:01 PM PDT 24 Apr 18 05:52:48 PM PDT 24 47771617112 ps
T762 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2378322147 Apr 18 04:48:26 PM PDT 24 Apr 18 04:59:36 PM PDT 24 5707249458 ps
T1157 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.69256344 Apr 18 04:25:12 PM PDT 24 Apr 18 04:32:11 PM PDT 24 3493865446 ps
T1158 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2506108642 Apr 18 04:29:07 PM PDT 24 Apr 18 04:37:21 PM PDT 24 4161545730 ps
T51 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2643269502 Apr 18 04:23:34 PM PDT 24 Apr 18 04:30:11 PM PDT 24 4525012506 ps
T183 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1581425823 Apr 18 04:22:39 PM PDT 24 Apr 18 05:46:11 PM PDT 24 43603885562 ps
T691 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3713539646 Apr 18 04:35:22 PM PDT 24 Apr 18 04:56:04 PM PDT 24 22742683234 ps
T233 /workspace/coverage/default/0.chip_sw_alert_test.1226627098 Apr 18 04:18:22 PM PDT 24 Apr 18 04:24:15 PM PDT 24 3213200526 ps
T1159 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2262935602 Apr 18 04:38:53 PM PDT 24 Apr 18 04:49:38 PM PDT 24 4490518028 ps
T165 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2679234984 Apr 18 04:53:41 PM PDT 24 Apr 18 05:01:59 PM PDT 24 4829164628 ps
T137 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.451309735 Apr 18 04:45:01 PM PDT 24 Apr 18 05:03:16 PM PDT 24 6184341290 ps
T1160 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2622318114 Apr 18 04:43:56 PM PDT 24 Apr 18 04:53:07 PM PDT 24 3374966590 ps
T1161 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4098243873 Apr 18 04:18:11 PM PDT 24 Apr 18 04:24:05 PM PDT 24 3209473860 ps
T432 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.882217390 Apr 18 04:39:50 PM PDT 24 Apr 18 04:47:54 PM PDT 24 9562381789 ps
T1162 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.967782530 Apr 18 04:25:11 PM PDT 24 Apr 18 04:28:20 PM PDT 24 2903777660 ps
T1163 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2525535303 Apr 18 04:22:58 PM PDT 24 Apr 18 04:34:56 PM PDT 24 4250586588 ps
T1164 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3703205773 Apr 18 04:39:25 PM PDT 24 Apr 18 04:46:49 PM PDT 24 3654271780 ps
T1165 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1477065345 Apr 18 04:44:09 PM PDT 24 Apr 18 04:49:29 PM PDT 24 2783929828 ps
T1166 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.261577564 Apr 18 04:24:09 PM PDT 24 Apr 18 04:43:19 PM PDT 24 7698654052 ps
T1167 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4101582624 Apr 18 04:37:24 PM PDT 24 Apr 18 04:41:13 PM PDT 24 2659371783 ps
T637 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3494426277 Apr 18 04:31:26 PM PDT 24 Apr 18 05:29:01 PM PDT 24 24985249386 ps
T1168 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.625650811 Apr 18 04:17:51 PM PDT 24 Apr 18 04:27:09 PM PDT 24 4824633441 ps
T1169 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3539602439 Apr 18 04:21:30 PM PDT 24 Apr 18 04:26:28 PM PDT 24 3306364652 ps
T1170 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2018414050 Apr 18 04:44:48 PM PDT 24 Apr 18 04:49:41 PM PDT 24 2682703540 ps
T1171 /workspace/coverage/default/1.chip_sw_example_flash.370656849 Apr 18 04:25:39 PM PDT 24 Apr 18 04:29:42 PM PDT 24 2405881360 ps
T1172 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3616777629 Apr 18 04:22:16 PM PDT 24 Apr 18 04:35:14 PM PDT 24 4777574726 ps
T1173 /workspace/coverage/default/0.chip_tap_straps_rma.2033342595 Apr 18 04:18:52 PM PDT 24 Apr 18 04:23:52 PM PDT 24 3057809363 ps
T1174 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1698361422 Apr 18 04:25:21 PM PDT 24 Apr 18 04:29:33 PM PDT 24 2798429778 ps
T759 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2128433709 Apr 18 04:51:12 PM PDT 24 Apr 18 04:58:17 PM PDT 24 5531060568 ps
T1175 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1788782479 Apr 18 04:36:07 PM PDT 24 Apr 18 04:41:02 PM PDT 24 4212155730 ps
T1176 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.812343489 Apr 18 04:16:26 PM PDT 24 Apr 18 04:26:02 PM PDT 24 4277431500 ps
T747 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221807818 Apr 18 04:50:06 PM PDT 24 Apr 18 04:56:38 PM PDT 24 4454566536 ps
T738 /workspace/coverage/default/47.chip_sw_all_escalation_resets.2824210892 Apr 18 04:48:47 PM PDT 24 Apr 18 04:57:37 PM PDT 24 5465895520 ps
T1177 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1399850537 Apr 18 04:42:20 PM PDT 24 Apr 18 04:49:45 PM PDT 24 2920696224 ps
T1178 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1078716855 Apr 18 04:29:02 PM PDT 24 Apr 18 04:38:30 PM PDT 24 4119742176 ps
T1179 /workspace/coverage/default/2.chip_sw_aes_masking_off.867951695 Apr 18 04:39:14 PM PDT 24 Apr 18 04:44:10 PM PDT 24 2855597125 ps
T1180 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3917644851 Apr 18 04:36:15 PM PDT 24 Apr 18 04:38:28 PM PDT 24 2875992830 ps
T765 /workspace/coverage/default/21.chip_sw_all_escalation_resets.4161534136 Apr 18 04:49:09 PM PDT 24 Apr 18 05:03:48 PM PDT 24 4923604520 ps
T688 /workspace/coverage/default/1.chip_sw_pattgen_ios.279370070 Apr 18 04:23:11 PM PDT 24 Apr 18 04:28:23 PM PDT 24 3490210104 ps
T1181 /workspace/coverage/default/2.chip_sw_kmac_idle.268449439 Apr 18 04:38:55 PM PDT 24 Apr 18 04:44:30 PM PDT 24 3171981172 ps
T1182 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1444003997 Apr 18 04:18:22 PM PDT 24 Apr 18 04:22:12 PM PDT 24 2820154812 ps
T1183 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.992238816 Apr 18 04:52:25 PM PDT 24 Apr 18 05:02:45 PM PDT 24 5251713760 ps
T1184 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.4349864 Apr 18 04:43:44 PM PDT 24 Apr 18 04:56:32 PM PDT 24 4514461612 ps
T1185 /workspace/coverage/default/3.chip_tap_straps_rma.1233533886 Apr 18 04:43:04 PM PDT 24 Apr 18 04:48:29 PM PDT 24 4173479204 ps
T1186 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2249325695 Apr 18 04:24:41 PM PDT 24 Apr 18 04:32:49 PM PDT 24 4215893250 ps
T1187 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3855593207 Apr 18 04:46:01 PM PDT 24 Apr 18 05:36:23 PM PDT 24 15052136286 ps
T1188 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3329356962 Apr 18 04:23:03 PM PDT 24 Apr 18 05:54:48 PM PDT 24 49894290616 ps
T1189 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2122651681 Apr 18 04:17:20 PM PDT 24 Apr 18 07:52:07 PM PDT 24 76911313400 ps
T1190 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2015832482 Apr 18 04:34:48 PM PDT 24 Apr 18 04:58:11 PM PDT 24 6342832420 ps
T338 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4145875004 Apr 18 04:29:48 PM PDT 24 Apr 18 04:40:31 PM PDT 24 5388658238 ps
T1191 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3555536754 Apr 18 04:51:37 PM PDT 24 Apr 18 04:59:55 PM PDT 24 4524440520 ps
T1192 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3796172997 Apr 18 04:27:30 PM PDT 24 Apr 18 05:19:24 PM PDT 24 14513454755 ps
T259 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2109838057 Apr 18 04:17:33 PM PDT 24 Apr 18 04:27:58 PM PDT 24 5551153938 ps
T750 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2125587638 Apr 18 04:47:58 PM PDT 24 Apr 18 04:56:39 PM PDT 24 5383504808 ps
T1193 /workspace/coverage/default/0.chip_sw_hmac_enc.4041370101 Apr 18 04:20:48 PM PDT 24 Apr 18 04:26:00 PM PDT 24 2614713004 ps
T370 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3615311461 Apr 18 04:16:49 PM PDT 24 Apr 18 04:28:05 PM PDT 24 4887613936 ps
T739 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.760373147 Apr 18 04:45:53 PM PDT 24 Apr 18 04:52:29 PM PDT 24 3362375320 ps
T720 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379315468 Apr 18 04:50:55 PM PDT 24 Apr 18 04:57:26 PM PDT 24 4189506080 ps
T1194 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.741638718 Apr 18 04:39:54 PM PDT 24 Apr 18 04:51:23 PM PDT 24 5063178089 ps
T1195 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2218060781 Apr 18 04:17:49 PM PDT 24 Apr 18 04:35:27 PM PDT 24 11101984512 ps
T757 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203424052 Apr 18 04:46:47 PM PDT 24 Apr 18 04:52:09 PM PDT 24 3061424400 ps
T1196 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2934396023 Apr 18 04:49:58 PM PDT 24 Apr 18 04:56:22 PM PDT 24 3307237620 ps
T1197 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3681098893 Apr 18 04:19:26 PM PDT 24 Apr 18 04:28:49 PM PDT 24 5017511144 ps
T1198 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1445389475 Apr 18 04:18:22 PM PDT 24 Apr 18 04:26:29 PM PDT 24 5410202320 ps
T1199 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2831103020 Apr 18 04:28:10 PM PDT 24 Apr 18 04:35:59 PM PDT 24 5157930348 ps
T393 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2987541410 Apr 18 04:22:16 PM PDT 24 Apr 18 04:29:09 PM PDT 24 3181115249 ps
T1200 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4035020269 Apr 18 04:29:45 PM PDT 24 Apr 18 04:38:11 PM PDT 24 4555029212 ps
T243 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3588323078 Apr 18 04:41:17 PM PDT 24 Apr 18 04:52:00 PM PDT 24 4403048624 ps
T1201 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.308553675 Apr 18 04:38:34 PM PDT 24 Apr 18 05:37:09 PM PDT 24 18835243316 ps
T1202 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2708560221 Apr 18 04:39:51 PM PDT 24 Apr 18 04:49:00 PM PDT 24 3757113232 ps
T1203 /workspace/coverage/default/2.chip_sw_uart_smoketest.487453169 Apr 18 04:43:11 PM PDT 24 Apr 18 04:47:24 PM PDT 24 2838755378 ps
T1204 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3325045217 Apr 18 04:21:59 PM PDT 24 Apr 18 04:26:45 PM PDT 24 2395938467 ps
T1205 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2103121864 Apr 18 04:40:56 PM PDT 24 Apr 18 04:50:05 PM PDT 24 5479500493 ps
T1206 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3298617956 Apr 18 04:25:58 PM PDT 24 Apr 18 04:32:19 PM PDT 24 3944770200 ps
T1207 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.569543570 Apr 18 04:21:59 PM PDT 24 Apr 18 07:29:12 PM PDT 24 66236285877 ps
T1208 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1735551193 Apr 18 04:31:56 PM PDT 24 Apr 18 04:38:39 PM PDT 24 3537844197 ps
T1209 /workspace/coverage/default/0.chip_sw_flash_init.3257380550 Apr 18 04:18:31 PM PDT 24 Apr 18 04:53:46 PM PDT 24 19632363844 ps
T1210 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.4244004627 Apr 18 04:45:20 PM PDT 24 Apr 18 05:09:37 PM PDT 24 8150701190 ps
T1211 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3721739049 Apr 18 04:18:47 PM PDT 24 Apr 18 04:24:38 PM PDT 24 3654114866 ps
T1212 /workspace/coverage/default/0.chip_sw_usbdev_dpi.740705795 Apr 18 04:18:18 PM PDT 24 Apr 18 05:09:15 PM PDT 24 12186264870 ps
T1213 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1271283277 Apr 18 04:34:00 PM PDT 24 Apr 18 04:40:30 PM PDT 24 3417712982 ps
T1214 /workspace/coverage/default/1.chip_sw_flash_init.1428375320 Apr 18 04:23:27 PM PDT 24 Apr 18 04:51:36 PM PDT 24 23948057075 ps
T1215 /workspace/coverage/default/2.chip_sw_aes_smoketest.1726110921 Apr 18 04:41:48 PM PDT 24 Apr 18 04:47:03 PM PDT 24 2828976250 ps
T1216 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.985330520 Apr 18 04:18:32 PM PDT 24 Apr 18 04:30:50 PM PDT 24 5120054142 ps
T1217 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.201728619 Apr 18 04:36:24 PM PDT 24 Apr 18 05:29:15 PM PDT 24 17507914760 ps
T745 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2475984606 Apr 18 04:47:40 PM PDT 24 Apr 18 04:57:51 PM PDT 24 5835731072 ps
T1218 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1952515094 Apr 18 04:29:12 PM PDT 24 Apr 18 04:44:16 PM PDT 24 12406925639 ps
T687 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.771017986 Apr 18 04:19:33 PM PDT 24 Apr 18 04:32:58 PM PDT 24 4673972040 ps
T1219 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3837884865 Apr 18 04:34:20 PM PDT 24 Apr 18 04:45:50 PM PDT 24 4618359340 ps
T1220 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1150490223 Apr 18 04:23:49 PM PDT 24 Apr 18 04:29:40 PM PDT 24 4838121248 ps
T1221 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4158844284 Apr 18 04:35:29 PM PDT 24 Apr 18 04:45:35 PM PDT 24 3920985580 ps
T1222 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1289292089 Apr 18 04:25:33 PM PDT 24 Apr 18 04:31:04 PM PDT 24 3037992624 ps
T1223 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1197473299 Apr 18 04:21:01 PM PDT 24 Apr 18 05:22:54 PM PDT 24 19248450944 ps
T1224 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1535805299 Apr 18 04:27:58 PM PDT 24 Apr 18 05:57:57 PM PDT 24 19228596180 ps
T769 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962503054 Apr 18 04:46:19 PM PDT 24 Apr 18 04:54:36 PM PDT 24 3580933222 ps
T1225 /workspace/coverage/default/75.chip_sw_all_escalation_resets.384154977 Apr 18 04:52:48 PM PDT 24 Apr 18 05:02:09 PM PDT 24 5224954696 ps
T748 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1573428281 Apr 18 04:54:10 PM PDT 24 Apr 18 04:59:01 PM PDT 24 4092349520 ps
T1226 /workspace/coverage/default/0.chip_sw_aes_entropy.2681885957 Apr 18 04:17:55 PM PDT 24 Apr 18 04:21:55 PM PDT 24 3072135360 ps
T1227 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2581016252 Apr 18 04:33:23 PM PDT 24 Apr 18 04:39:13 PM PDT 24 4649407656 ps
T415 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3282614356 Apr 18 04:17:59 PM PDT 24 Apr 18 04:44:04 PM PDT 24 23680174422 ps
T1228 /workspace/coverage/default/0.chip_sw_coremark.1125556352 Apr 18 04:17:46 PM PDT 24 Apr 18 07:08:24 PM PDT 24 50968906612 ps
T1229 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2793266011 Apr 18 04:18:27 PM PDT 24 Apr 18 04:43:23 PM PDT 24 8743874626 ps
T1230 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1110314876 Apr 18 04:28:44 PM PDT 24 Apr 18 04:39:00 PM PDT 24 9193010405 ps
T1231 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1181150903 Apr 18 04:39:53 PM PDT 24 Apr 18 04:58:41 PM PDT 24 8051965820 ps
T300 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1662795738 Apr 18 04:48:56 PM PDT 24 Apr 18 04:55:41 PM PDT 24 3715524610 ps
T1232 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.869515149 Apr 18 04:43:44 PM PDT 24 Apr 18 05:21:32 PM PDT 24 13102879354 ps
T1233 /workspace/coverage/default/2.rom_e2e_asm_init_dev.274944049 Apr 18 04:46:57 PM PDT 24 Apr 18 05:38:38 PM PDT 24 15653795010 ps
T1234 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2042000806 Apr 18 04:51:54 PM PDT 24 Apr 18 04:59:48 PM PDT 24 4012767706 ps
T737 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2435119361 Apr 18 04:49:03 PM PDT 24 Apr 18 04:56:16 PM PDT 24 3737359334 ps
T743 /workspace/coverage/default/58.chip_sw_all_escalation_resets.152111830 Apr 18 04:51:53 PM PDT 24 Apr 18 05:03:09 PM PDT 24 5186845548 ps
T1235 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2989348779 Apr 18 04:38:24 PM PDT 24 Apr 18 04:51:12 PM PDT 24 7230454088 ps
T363 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3222693043 Apr 18 04:46:26 PM PDT 24 Apr 18 04:56:36 PM PDT 24 4065480480 ps
T1236 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3136701528 Apr 18 04:18:11 PM PDT 24 Apr 18 05:50:01 PM PDT 24 49449965831 ps
T1237 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1454289365 Apr 18 04:38:59 PM PDT 24 Apr 18 04:43:48 PM PDT 24 2888075674 ps
T347 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.855684659 Apr 18 04:40:14 PM PDT 24 Apr 18 04:46:15 PM PDT 24 2885152356 ps
T1238 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.30239389 Apr 18 04:23:03 PM PDT 24 Apr 18 04:36:17 PM PDT 24 6066647516 ps
T56 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3563078619 Apr 18 04:40:04 PM PDT 24 Apr 18 05:08:29 PM PDT 24 19797021670 ps
T1239 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3097831887 Apr 18 04:29:31 PM PDT 24 Apr 18 04:40:59 PM PDT 24 5986424120 ps
T1240 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1724090321 Apr 18 04:18:54 PM PDT 24 Apr 18 04:27:52 PM PDT 24 6559853256 ps
T1241 /workspace/coverage/default/2.rom_volatile_raw_unlock.1360958508 Apr 18 04:43:08 PM PDT 24 Apr 18 04:45:16 PM PDT 24 2389411429 ps
T282 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3034506015 Apr 18 04:30:01 PM PDT 24 Apr 18 04:33:51 PM PDT 24 2735545357 ps
T1242 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1082019400 Apr 18 04:44:31 PM PDT 24 Apr 18 04:58:04 PM PDT 24 4381016810 ps
T1243 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3222611653 Apr 18 04:18:48 PM PDT 24 Apr 18 04:28:41 PM PDT 24 3508384570 ps
T1244 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2192668758 Apr 18 04:38:10 PM PDT 24 Apr 18 05:08:53 PM PDT 24 8336557996 ps
T1245 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.552716767 Apr 18 04:44:14 PM PDT 24 Apr 18 04:50:33 PM PDT 24 3559056312 ps
T772 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3258649045 Apr 18 04:51:07 PM PDT 24 Apr 18 04:58:30 PM PDT 24 4114564744 ps
T1246 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.327379401 Apr 18 04:34:19 PM PDT 24 Apr 18 04:58:46 PM PDT 24 8743515512 ps
T1247 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2717379660 Apr 18 04:23:40 PM PDT 24 Apr 18 04:41:37 PM PDT 24 5491219413 ps
T1248 /workspace/coverage/default/2.chip_tap_straps_dev.2261708075 Apr 18 04:39:33 PM PDT 24 Apr 18 04:42:02 PM PDT 24 2706189003 ps
T1249 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3696134748 Apr 18 04:16:58 PM PDT 24 Apr 18 04:28:44 PM PDT 24 7624385532 ps
T1250 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2417025052 Apr 18 04:45:39 PM PDT 24 Apr 18 05:05:00 PM PDT 24 13259791367 ps
T1251 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3261322971 Apr 18 04:40:03 PM PDT 24 Apr 18 04:52:00 PM PDT 24 4971981456 ps
T1252 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4008550109 Apr 18 04:19:33 PM PDT 24 Apr 18 04:25:04 PM PDT 24 3702035540 ps
T1253 /workspace/coverage/default/1.chip_sw_edn_kat.3859610261 Apr 18 04:27:25 PM PDT 24 Apr 18 04:40:04 PM PDT 24 3497615018 ps
T1254 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3568302556 Apr 18 04:35:34 PM PDT 24 Apr 18 04:41:03 PM PDT 24 2858628237 ps
T727 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617671493 Apr 18 04:53:14 PM PDT 24 Apr 18 04:59:31 PM PDT 24 3575245204 ps
T1255 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2769556373 Apr 18 04:25:17 PM PDT 24 Apr 18 04:36:47 PM PDT 24 4606167366 ps
T1256 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2411999684 Apr 18 04:52:33 PM PDT 24 Apr 18 04:58:40 PM PDT 24 3718819130 ps
T333 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2084077841 Apr 18 04:17:01 PM PDT 24 Apr 18 04:36:32 PM PDT 24 5886589500 ps
T283 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1494782032 Apr 18 04:30:19 PM PDT 24 Apr 18 04:35:01 PM PDT 24 2811716426 ps
T1257 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2086872171 Apr 18 04:25:17 PM PDT 24 Apr 18 05:23:22 PM PDT 24 14390157241 ps
T1258 /workspace/coverage/default/0.chip_sw_example_rom.1705428940 Apr 18 04:16:38 PM PDT 24 Apr 18 04:18:44 PM PDT 24 2719828062 ps
T1259 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3175119873 Apr 18 04:18:41 PM PDT 24 Apr 18 04:27:20 PM PDT 24 5917034884 ps
T1260 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1948031986 Apr 18 04:43:45 PM PDT 24 Apr 18 04:53:10 PM PDT 24 4436342738 ps
T1261 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3054622560 Apr 18 04:27:52 PM PDT 24 Apr 18 04:38:18 PM PDT 24 5133671736 ps
T1262 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1065399348 Apr 18 04:37:36 PM PDT 24 Apr 18 04:41:25 PM PDT 24 2347856220 ps
T371 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2662067948 Apr 18 04:23:39 PM PDT 24 Apr 18 04:36:15 PM PDT 24 5078041920 ps
T1263 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3147388610 Apr 18 04:19:27 PM PDT 24 Apr 18 04:32:35 PM PDT 24 5971983832 ps
T1264 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3020478343 Apr 18 04:43:45 PM PDT 24 Apr 18 04:47:20 PM PDT 24 2399035908 ps
T761 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3705554270 Apr 18 04:48:54 PM PDT 24 Apr 18 04:55:21 PM PDT 24 3068717544 ps
T725 /workspace/coverage/default/78.chip_sw_all_escalation_resets.909251037 Apr 18 04:52:02 PM PDT 24 Apr 18 04:59:01 PM PDT 24 4635658472 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.750750385 Apr 18 04:21:28 PM PDT 24 Apr 18 04:29:37 PM PDT 24 3006911348 ps
T763 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262783212 Apr 18 04:48:48 PM PDT 24 Apr 18 04:55:22 PM PDT 24 3794284870 ps
T1265 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3279872809 Apr 18 04:43:33 PM PDT 24 Apr 18 04:48:43 PM PDT 24 6683403800 ps
T320 /workspace/coverage/default/2.chip_plic_all_irqs_20.1420546821 Apr 18 04:41:31 PM PDT 24 Apr 18 04:52:05 PM PDT 24 4481516254 ps
T1266 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2220623678 Apr 18 04:24:07 PM PDT 24 Apr 18 04:41:14 PM PDT 24 6008143464 ps
T1267 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4067896746 Apr 18 04:19:27 PM PDT 24 Apr 18 04:37:58 PM PDT 24 5649466519 ps
T1268 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2860950749 Apr 18 04:46:19 PM PDT 24 Apr 18 05:08:21 PM PDT 24 8973066108 ps
T1269 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2596373254 Apr 18 04:29:46 PM PDT 24 Apr 18 04:37:29 PM PDT 24 5481020182 ps
T1270 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.349776670 Apr 18 04:44:14 PM PDT 24 Apr 18 04:52:50 PM PDT 24 5045733593 ps
T1271 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3336449435 Apr 18 04:32:54 PM PDT 24 Apr 18 04:57:47 PM PDT 24 8379747211 ps
T1272 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2134195054 Apr 18 04:20:56 PM PDT 24 Apr 18 04:43:29 PM PDT 24 6445983268 ps
T134 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3680792468 Apr 18 04:17:44 PM PDT 24 Apr 18 04:25:47 PM PDT 24 5456957022 ps
T49 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3923204708 Apr 18 04:23:15 PM PDT 24 Apr 18 04:29:25 PM PDT 24 3269928860 ps
T1273 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2758408073 Apr 18 04:43:50 PM PDT 24 Apr 18 04:46:58 PM PDT 24 2446565400 ps
T1274 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.309312519 Apr 18 04:26:01 PM PDT 24 Apr 18 05:40:13 PM PDT 24 19249040980 ps
T377 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2158955589 Apr 18 04:19:27 PM PDT 24 Apr 18 04:21:45 PM PDT 24 2392985464 ps
T782 /workspace/coverage/default/48.chip_sw_all_escalation_resets.324529602 Apr 18 04:51:14 PM PDT 24 Apr 18 05:03:00 PM PDT 24 5149100958 ps
T1275 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1500060876 Apr 18 04:47:18 PM PDT 24 Apr 18 04:55:13 PM PDT 24 4614472232 ps
T1276 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2018441783 Apr 18 04:20:37 PM PDT 24 Apr 18 04:34:52 PM PDT 24 8095849334 ps
T73 /workspace/coverage/cover_reg_top/49.xbar_same_source.1160080075 Apr 18 04:00:34 PM PDT 24 Apr 18 04:01:06 PM PDT 24 967412510 ps
T74 /workspace/coverage/cover_reg_top/31.xbar_access_same_device.4177903557 Apr 18 03:57:01 PM PDT 24 Apr 18 03:57:37 PM PDT 24 892350231 ps
T75 /workspace/coverage/cover_reg_top/40.xbar_random.2926081938 Apr 18 03:58:48 PM PDT 24 Apr 18 03:59:04 PM PDT 24 350065862 ps
T80 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3457221307 Apr 18 03:57:04 PM PDT 24 Apr 18 03:57:42 PM PDT 24 445966667 ps
T129 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1389121636 Apr 18 04:08:44 PM PDT 24 Apr 18 04:09:25 PM PDT 24 1092967495 ps
T420 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1347316821 Apr 18 04:08:16 PM PDT 24 Apr 18 04:19:16 PM PDT 24 34719506261 ps
T522 /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2831708282 Apr 18 03:48:26 PM PDT 24 Apr 18 03:48:33 PM PDT 24 48798170 ps
T446 /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3300284702 Apr 18 04:09:17 PM PDT 24 Apr 18 04:09:27 PM PDT 24 68655465 ps
T506 /workspace/coverage/cover_reg_top/17.xbar_random.3634492342 Apr 18 03:53:15 PM PDT 24 Apr 18 03:53:43 PM PDT 24 304425377 ps
T527 /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3950846335 Apr 18 04:05:41 PM PDT 24 Apr 18 04:07:05 PM PDT 24 5385857947 ps
T519 /workspace/coverage/cover_reg_top/27.xbar_stress_all.771131788 Apr 18 03:56:13 PM PDT 24 Apr 18 03:57:10 PM PDT 24 1284383399 ps
T532 /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2351380174 Apr 18 04:03:52 PM PDT 24 Apr 18 04:03:58 PM PDT 24 37974476 ps
T534 /workspace/coverage/cover_reg_top/18.xbar_smoke.3827812563 Apr 18 03:53:24 PM PDT 24 Apr 18 03:53:33 PM PDT 24 147747624 ps
T447 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1232795569 Apr 18 04:02:27 PM PDT 24 Apr 18 04:12:43 PM PDT 24 15317208658 ps
T517 /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3932087907 Apr 18 03:57:24 PM PDT 24 Apr 18 03:57:45 PM PDT 24 384214562 ps
T496 /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.403176344 Apr 18 04:02:41 PM PDT 24 Apr 18 04:11:42 PM PDT 24 33270616650 ps
T530 /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1598196238 Apr 18 03:57:29 PM PDT 24 Apr 18 03:57:36 PM PDT 24 50819740 ps
T533 /workspace/coverage/cover_reg_top/2.xbar_smoke.827758968 Apr 18 03:47:43 PM PDT 24 Apr 18 03:47:49 PM PDT 24 48622969 ps
T531 /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4030784592 Apr 18 04:02:30 PM PDT 24 Apr 18 04:03:40 PM PDT 24 4369962915 ps
T463 /workspace/coverage/cover_reg_top/55.xbar_random.3619442657 Apr 18 04:01:34 PM PDT 24 Apr 18 04:02:23 PM PDT 24 518707678 ps
T491 /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3657434570 Apr 18 03:55:13 PM PDT 24 Apr 18 03:55:59 PM PDT 24 331277820 ps
T716 /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1336512056 Apr 18 03:57:06 PM PDT 24 Apr 18 03:57:53 PM PDT 24 2482738876 ps
T528 /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3727962817 Apr 18 03:59:23 PM PDT 24 Apr 18 04:00:28 PM PDT 24 6312082363 ps
T476 /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.4075638825 Apr 18 04:01:22 PM PDT 24 Apr 18 04:07:32 PM PDT 24 21392628695 ps
T518 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3457028718 Apr 18 04:01:02 PM PDT 24 Apr 18 04:03:55 PM PDT 24 2232833985 ps
T525 /workspace/coverage/cover_reg_top/24.xbar_same_source.377875560 Apr 18 03:55:14 PM PDT 24 Apr 18 03:55:36 PM PDT 24 283547823 ps
T520 /workspace/coverage/cover_reg_top/68.xbar_random.2536810963 Apr 18 04:03:53 PM PDT 24 Apr 18 04:04:06 PM PDT 24 321126416 ps
T529 /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3044431896 Apr 18 04:05:29 PM PDT 24 Apr 18 04:08:14 PM PDT 24 9655947446 ps
T521 /workspace/coverage/cover_reg_top/26.xbar_error_random.2620041637 Apr 18 03:55:52 PM PDT 24 Apr 18 03:56:34 PM PDT 24 1150100867 ps
T686 /workspace/coverage/cover_reg_top/67.xbar_smoke.1230502058 Apr 18 04:03:42 PM PDT 24 Apr 18 04:03:49 PM PDT 24 53579072 ps
T421 /workspace/coverage/cover_reg_top/60.xbar_same_source.4274161368 Apr 18 04:02:37 PM PDT 24 Apr 18 04:02:58 PM PDT 24 257483466 ps
T492 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2655483933 Apr 18 03:48:06 PM PDT 24 Apr 18 03:48:40 PM PDT 24 764758032 ps
T526 /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1769215954 Apr 18 03:51:48 PM PDT 24 Apr 18 03:52:30 PM PDT 24 448879626 ps
T416 /workspace/coverage/cover_reg_top/81.xbar_stress_all.2975941778 Apr 18 04:06:10 PM PDT 24 Apr 18 04:10:46 PM PDT 24 3126844263 ps
T523 /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.896428731 Apr 18 04:09:18 PM PDT 24 Apr 18 04:14:51 PM PDT 24 19194125489 ps
T524 /workspace/coverage/cover_reg_top/11.chip_tl_errors.1750357722 Apr 18 03:50:30 PM PDT 24 Apr 18 03:56:04 PM PDT 24 3930036970 ps
T508 /workspace/coverage/cover_reg_top/33.xbar_smoke.3983581706 Apr 18 03:57:12 PM PDT 24 Apr 18 03:57:19 PM PDT 24 121763157 ps
T800 /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.1653291796 Apr 18 04:09:08 PM PDT 24 Apr 18 04:10:50 PM PDT 24 5697917772 ps
T579 /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.220064862 Apr 18 03:59:30 PM PDT 24 Apr 18 04:08:44 PM PDT 24 48054869886 ps
T577 /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3206865613 Apr 18 03:56:01 PM PDT 24 Apr 18 03:56:07 PM PDT 24 42503681 ps
T419 /workspace/coverage/cover_reg_top/54.xbar_stress_all.1576993893 Apr 18 04:01:29 PM PDT 24 Apr 18 04:09:37 PM PDT 24 13275432606 ps
T411 /workspace/coverage/cover_reg_top/69.xbar_stress_all.124682262 Apr 18 04:04:04 PM PDT 24 Apr 18 04:14:21 PM PDT 24 15538978832 ps
T571 /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.192926241 Apr 18 03:58:41 PM PDT 24 Apr 18 04:03:06 PM PDT 24 15426006354 ps
T586 /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3801111121 Apr 18 04:00:08 PM PDT 24 Apr 18 04:01:21 PM PDT 24 4190406151 ps
T418 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3088737695 Apr 18 04:06:11 PM PDT 24 Apr 18 04:11:55 PM PDT 24 2404131269 ps
T574 /workspace/coverage/cover_reg_top/48.xbar_random.2902283798 Apr 18 04:00:22 PM PDT 24 Apr 18 04:00:43 PM PDT 24 465353400 ps
T815 /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1629261151 Apr 18 04:07:01 PM PDT 24 Apr 18 04:07:35 PM PDT 24 867833070 ps
T1277 /workspace/coverage/cover_reg_top/73.xbar_smoke.1689953978 Apr 18 04:04:46 PM PDT 24 Apr 18 04:04:56 PM PDT 24 233199623 ps
T72 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1899472096 Apr 18 03:47:34 PM PDT 24 Apr 18 03:53:28 PM PDT 24 6500608700 ps
T685 /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2547771783 Apr 18 03:58:12 PM PDT 24 Apr 18 04:00:05 PM PDT 24 10638486055 ps
T588 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.286611027 Apr 18 03:53:24 PM PDT 24 Apr 18 03:57:27 PM PDT 24 388836058 ps
T812 /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2819110802 Apr 18 04:03:56 PM PDT 24 Apr 18 04:09:41 PM PDT 24 19833700712 ps
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