Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 95.29 93.57 95.62 94.21 97.38 99.55


Total test records in report: 2847
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html
T1009 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2589153349 Apr 18 04:39:13 PM PDT 24 Apr 18 04:46:12 PM PDT 24 4288111360 ps
T1010 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.978683281 Apr 18 04:24:51 PM PDT 24 Apr 18 05:02:31 PM PDT 24 21778531119 ps
T182 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1395069905 Apr 18 04:33:31 PM PDT 24 Apr 18 05:45:08 PM PDT 24 43237423364 ps
T1011 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1744778166 Apr 18 04:18:28 PM PDT 24 Apr 18 04:36:20 PM PDT 24 7170294979 ps
T657 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.207636350 Apr 18 04:26:52 PM PDT 24 Apr 18 04:43:51 PM PDT 24 4738558166 ps
T57 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3200035131 Apr 18 04:26:17 PM PDT 24 Apr 18 04:33:28 PM PDT 24 4733740528 ps
T406 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2722102226 Apr 18 04:46:00 PM PDT 24 Apr 18 04:50:34 PM PDT 24 2743221848 ps
T299 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441416813 Apr 18 04:52:30 PM PDT 24 Apr 18 04:59:54 PM PDT 24 3337375852 ps
T407 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3915381751 Apr 18 04:36:47 PM PDT 24 Apr 18 05:32:22 PM PDT 24 15691907882 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.648673012 Apr 18 04:20:03 PM PDT 24 Apr 18 04:25:00 PM PDT 24 2730262060 ps
T408 /workspace/coverage/default/0.chip_sw_aes_smoketest.2955776259 Apr 18 04:25:53 PM PDT 24 Apr 18 04:31:35 PM PDT 24 3227605720 ps
T409 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1776542588 Apr 18 04:25:47 PM PDT 24 Apr 18 04:28:52 PM PDT 24 2791906152 ps
T410 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4164990396 Apr 18 04:39:47 PM PDT 24 Apr 18 04:50:08 PM PDT 24 4299603124 ps
T242 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.520105191 Apr 18 04:30:53 PM PDT 24 Apr 18 04:40:07 PM PDT 24 5460199948 ps
T317 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1442283835 Apr 18 04:34:38 PM PDT 24 Apr 18 04:46:43 PM PDT 24 5149705070 ps
T345 /workspace/coverage/default/0.chip_sw_aon_timer_irq.67976684 Apr 18 04:19:07 PM PDT 24 Apr 18 04:27:47 PM PDT 24 4334042000 ps
T361 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2620118289 Apr 18 04:52:30 PM PDT 24 Apr 18 04:57:34 PM PDT 24 3341729160 ps
T1012 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3349849599 Apr 18 04:18:27 PM PDT 24 Apr 18 04:34:51 PM PDT 24 5500479990 ps
T1013 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2521530754 Apr 18 04:20:29 PM PDT 24 Apr 18 04:28:33 PM PDT 24 7054711504 ps
T1014 /workspace/coverage/default/43.chip_sw_all_escalation_resets.1366257887 Apr 18 04:49:00 PM PDT 24 Apr 18 05:00:55 PM PDT 24 4448813210 ps
T34 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3645571677 Apr 18 04:37:35 PM PDT 24 Apr 18 04:46:36 PM PDT 24 5449063810 ps
T1015 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2304597193 Apr 18 04:17:43 PM PDT 24 Apr 18 04:23:29 PM PDT 24 3567397848 ps
T273 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.587637232 Apr 18 04:29:30 PM PDT 24 Apr 18 04:39:22 PM PDT 24 4434551128 ps
T226 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3640378622 Apr 18 04:41:03 PM PDT 24 Apr 18 05:11:42 PM PDT 24 19881344336 ps
T1016 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3810776204 Apr 18 04:36:52 PM PDT 24 Apr 18 04:46:52 PM PDT 24 7086745610 ps
T1017 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2314248952 Apr 18 04:25:20 PM PDT 24 Apr 18 04:35:34 PM PDT 24 4345369472 ps
T1018 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2928774003 Apr 18 04:46:27 PM PDT 24 Apr 18 04:55:04 PM PDT 24 4095033560 ps
T681 /workspace/coverage/default/2.chip_sw_power_sleep_load.1011529657 Apr 18 04:41:27 PM PDT 24 Apr 18 04:47:14 PM PDT 24 4163996352 ps
T1019 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3636655180 Apr 18 04:36:02 PM PDT 24 Apr 18 04:53:08 PM PDT 24 5491466840 ps
T698 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1000011836 Apr 18 04:50:55 PM PDT 24 Apr 18 05:01:51 PM PDT 24 4979140234 ps
T1020 /workspace/coverage/default/2.chip_sw_power_idle_load.3876530665 Apr 18 04:40:54 PM PDT 24 Apr 18 04:52:50 PM PDT 24 4463409918 ps
T150 /workspace/coverage/default/2.chip_plic_all_irqs_10.4244535019 Apr 18 04:40:48 PM PDT 24 Apr 18 04:51:38 PM PDT 24 4092559284 ps
T1021 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.93530798 Apr 18 04:27:52 PM PDT 24 Apr 18 05:43:38 PM PDT 24 14621415974 ps
T1022 /workspace/coverage/default/2.chip_sw_aes_enc.132846711 Apr 18 04:37:34 PM PDT 24 Apr 18 04:41:00 PM PDT 24 2668201396 ps
T1023 /workspace/coverage/default/2.chip_sw_aes_entropy.3798357406 Apr 18 04:38:17 PM PDT 24 Apr 18 04:42:26 PM PDT 24 2616650640 ps
T311 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.191140363 Apr 18 04:34:30 PM PDT 24 Apr 18 04:47:23 PM PDT 24 4254657488 ps
T323 /workspace/coverage/default/0.chip_sw_pattgen_ios.660396843 Apr 18 04:16:20 PM PDT 24 Apr 18 04:20:03 PM PDT 24 3067417396 ps
T1024 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1182597153 Apr 18 04:24:58 PM PDT 24 Apr 18 04:53:28 PM PDT 24 11277991224 ps
T1025 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241950488 Apr 18 04:51:01 PM PDT 24 Apr 18 04:58:42 PM PDT 24 4147377032 ps
T724 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.280284966 Apr 18 04:54:31 PM PDT 24 Apr 18 04:59:19 PM PDT 24 3375901188 ps
T699 /workspace/coverage/default/16.chip_sw_all_escalation_resets.954885040 Apr 18 04:46:25 PM PDT 24 Apr 18 04:55:31 PM PDT 24 6171712712 ps
T1026 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.973288316 Apr 18 04:21:22 PM PDT 24 Apr 18 04:30:59 PM PDT 24 6221829304 ps
T1027 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1527698807 Apr 18 04:29:07 PM PDT 24 Apr 18 04:45:13 PM PDT 24 6623129588 ps
T1028 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3202457509 Apr 18 04:46:05 PM PDT 24 Apr 18 05:59:36 PM PDT 24 15471740008 ps
T1029 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.4011199194 Apr 18 04:17:48 PM PDT 24 Apr 18 04:37:24 PM PDT 24 6421146766 ps
T315 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1607334709 Apr 18 04:38:05 PM PDT 24 Apr 18 05:05:22 PM PDT 24 7759774082 ps
T673 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2402729728 Apr 18 04:17:41 PM PDT 24 Apr 18 04:20:54 PM PDT 24 2721102058 ps
T1030 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.114161929 Apr 18 04:22:31 PM PDT 24 Apr 18 04:33:08 PM PDT 24 5117675250 ps
T1031 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2993763821 Apr 18 04:23:13 PM PDT 24 Apr 18 04:48:47 PM PDT 24 8176436160 ps
T316 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1604961597 Apr 18 04:27:50 PM PDT 24 Apr 18 04:49:52 PM PDT 24 5855813288 ps
T434 /workspace/coverage/default/1.chip_jtag_mem_access.1031466080 Apr 18 04:22:30 PM PDT 24 Apr 18 04:50:54 PM PDT 24 13535139222 ps
T436 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3406796250 Apr 18 04:21:20 PM PDT 24 Apr 18 04:28:36 PM PDT 24 3385440374 ps
T1032 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.809865545 Apr 18 04:36:07 PM PDT 24 Apr 18 04:50:30 PM PDT 24 7846811684 ps
T1033 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2645759471 Apr 18 04:22:25 PM PDT 24 Apr 18 04:30:18 PM PDT 24 3474783888 ps
T777 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854826140 Apr 18 04:52:55 PM PDT 24 Apr 18 05:00:35 PM PDT 24 3812238736 ps
T1034 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.381950332 Apr 18 04:27:18 PM PDT 24 Apr 18 04:34:05 PM PDT 24 4135814232 ps
T54 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1340123845 Apr 18 04:23:05 PM PDT 24 Apr 18 04:45:49 PM PDT 24 16125361700 ps
T695 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102241272 Apr 18 04:49:58 PM PDT 24 Apr 18 04:58:51 PM PDT 24 4341877760 ps
T1035 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2532501408 Apr 18 04:24:59 PM PDT 24 Apr 18 04:34:08 PM PDT 24 17476903660 ps
T1036 /workspace/coverage/default/1.chip_sw_example_concurrency.3447841634 Apr 18 04:22:13 PM PDT 24 Apr 18 04:28:04 PM PDT 24 3374292690 ps
T640 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3210535654 Apr 18 04:21:10 PM PDT 24 Apr 18 04:29:45 PM PDT 24 3051749978 ps
T1037 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2918404013 Apr 18 04:46:50 PM PDT 24 Apr 18 04:55:19 PM PDT 24 6385942353 ps
T735 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.496196461 Apr 18 04:50:17 PM PDT 24 Apr 18 04:56:51 PM PDT 24 4021903752 ps
T1038 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1034252127 Apr 18 04:24:58 PM PDT 24 Apr 18 04:44:22 PM PDT 24 6968758172 ps
T1039 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.552968110 Apr 18 04:22:33 PM PDT 24 Apr 18 04:35:51 PM PDT 24 4814876148 ps
T1040 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2299797933 Apr 18 04:17:18 PM PDT 24 Apr 18 04:23:04 PM PDT 24 4588912648 ps
T1041 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1327075733 Apr 18 04:27:33 PM PDT 24 Apr 18 04:48:00 PM PDT 24 6171838328 ps
T1042 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.920987775 Apr 18 04:35:08 PM PDT 24 Apr 18 04:47:49 PM PDT 24 6554688304 ps
T1043 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.563355287 Apr 18 04:20:52 PM PDT 24 Apr 18 04:24:41 PM PDT 24 2550745206 ps
T1044 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3822839711 Apr 18 04:22:00 PM PDT 24 Apr 18 07:39:01 PM PDT 24 65164595635 ps
T1045 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.354273016 Apr 18 04:30:09 PM PDT 24 Apr 18 04:36:15 PM PDT 24 5727116174 ps
T217 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2701919991 Apr 18 04:22:42 PM PDT 24 Apr 18 05:13:40 PM PDT 24 12403035040 ps
T1046 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3861872646 Apr 18 04:45:01 PM PDT 24 Apr 18 04:54:33 PM PDT 24 6448918038 ps
T248 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3768528646 Apr 18 04:35:11 PM PDT 24 Apr 18 04:44:00 PM PDT 24 4609101808 ps
T1047 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2031332010 Apr 18 04:29:11 PM PDT 24 Apr 18 05:11:43 PM PDT 24 29596188922 ps
T1048 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3559990451 Apr 18 04:26:40 PM PDT 24 Apr 18 05:15:22 PM PDT 24 12109166456 ps
T1049 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3249808812 Apr 18 04:19:44 PM PDT 24 Apr 18 04:27:28 PM PDT 24 4912055846 ps
T1050 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.96265663 Apr 18 04:38:21 PM PDT 24 Apr 18 07:53:05 PM PDT 24 256329630770 ps
T766 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1510370935 Apr 18 04:51:42 PM PDT 24 Apr 18 04:59:40 PM PDT 24 5677851254 ps
T1051 /workspace/coverage/default/1.chip_sw_rv_timer_irq.765363299 Apr 18 04:25:53 PM PDT 24 Apr 18 04:30:32 PM PDT 24 3059634720 ps
T1052 /workspace/coverage/default/2.chip_tap_straps_prod.1062806999 Apr 18 04:40:06 PM PDT 24 Apr 18 04:43:07 PM PDT 24 2855931478 ps
T1053 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1503140598 Apr 18 04:35:50 PM PDT 24 Apr 18 04:44:00 PM PDT 24 5780081032 ps
T1054 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3525418642 Apr 18 04:44:28 PM PDT 24 Apr 18 04:53:46 PM PDT 24 3977872440 ps
T729 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2480417408 Apr 18 04:52:11 PM PDT 24 Apr 18 04:58:17 PM PDT 24 3667230980 ps
T1055 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3040235668 Apr 18 04:46:34 PM PDT 24 Apr 18 04:51:58 PM PDT 24 5696403700 ps
T635 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3179169305 Apr 18 04:42:28 PM PDT 24 Apr 18 05:41:48 PM PDT 24 24055604112 ps
T1056 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.963118833 Apr 18 04:22:41 PM PDT 24 Apr 18 04:27:17 PM PDT 24 2551835424 ps
T1057 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1599098457 Apr 18 04:38:49 PM PDT 24 Apr 18 04:48:39 PM PDT 24 4139328460 ps
T234 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188948393 Apr 18 04:48:38 PM PDT 24 Apr 18 04:55:36 PM PDT 24 4189737966 ps
T277 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4133656846 Apr 18 04:49:15 PM PDT 24 Apr 18 04:57:33 PM PDT 24 3600300540 ps
T278 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2478054186 Apr 18 04:33:14 PM PDT 24 Apr 18 04:39:29 PM PDT 24 3265740624 ps
T279 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3124160668 Apr 18 04:51:35 PM PDT 24 Apr 18 05:00:45 PM PDT 24 6152163568 ps
T280 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1068994862 Apr 18 04:20:41 PM PDT 24 Apr 18 04:27:01 PM PDT 24 2611069432 ps
T133 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1195289865 Apr 18 04:39:48 PM PDT 24 Apr 18 04:50:25 PM PDT 24 5689094338 ps
T257 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3611782034 Apr 18 04:34:24 PM PDT 24 Apr 18 04:49:09 PM PDT 24 4781359736 ps
T260 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4182671684 Apr 18 04:35:24 PM PDT 24 Apr 18 04:44:28 PM PDT 24 3466950230 ps
T261 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3923734359 Apr 18 04:48:25 PM PDT 24 Apr 18 05:00:53 PM PDT 24 4472445176 ps
T262 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1066981715 Apr 18 04:45:33 PM PDT 24 Apr 18 04:55:43 PM PDT 24 5020834174 ps
T263 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1452896643 Apr 18 04:35:28 PM PDT 24 Apr 18 05:06:02 PM PDT 24 14087154260 ps
T264 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.421214205 Apr 18 04:27:37 PM PDT 24 Apr 18 04:36:07 PM PDT 24 4101509360 ps
T265 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3805224762 Apr 18 04:53:04 PM PDT 24 Apr 18 05:01:25 PM PDT 24 5260018780 ps
T266 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3729084475 Apr 18 04:36:39 PM PDT 24 Apr 18 05:03:16 PM PDT 24 12943762766 ps
T267 /workspace/coverage/default/80.chip_sw_all_escalation_resets.2345735637 Apr 18 04:51:55 PM PDT 24 Apr 18 04:59:43 PM PDT 24 5468615448 ps
T268 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1313469959 Apr 18 04:21:08 PM PDT 24 Apr 18 04:30:35 PM PDT 24 3908821824 ps
T180 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1369962778 Apr 18 04:40:47 PM PDT 24 Apr 18 04:44:21 PM PDT 24 2922545604 ps
T378 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1334557210 Apr 18 04:16:33 PM PDT 24 Apr 18 04:20:26 PM PDT 24 3026546514 ps
T379 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1291548582 Apr 18 04:30:27 PM PDT 24 Apr 18 04:39:52 PM PDT 24 5673022348 ps
T380 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.303953469 Apr 18 04:20:40 PM PDT 24 Apr 18 04:26:26 PM PDT 24 3369370375 ps
T381 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3018654990 Apr 18 04:19:28 PM PDT 24 Apr 18 04:21:16 PM PDT 24 2102136210 ps
T382 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1941917066 Apr 18 04:30:57 PM PDT 24 Apr 18 04:41:16 PM PDT 24 5216820100 ps
T383 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1094810658 Apr 18 04:26:26 PM PDT 24 Apr 18 05:25:28 PM PDT 24 14894916844 ps
T384 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1271845154 Apr 18 04:17:27 PM PDT 24 Apr 18 04:19:57 PM PDT 24 3641070246 ps
T385 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3420442465 Apr 18 04:27:12 PM PDT 24 Apr 18 05:20:51 PM PDT 24 12419867836 ps
T331 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.249767992 Apr 18 04:24:54 PM PDT 24 Apr 18 04:37:24 PM PDT 24 4991267228 ps
T636 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1346797375 Apr 18 04:21:40 PM PDT 24 Apr 18 05:26:57 PM PDT 24 24506435491 ps
T225 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1774680032 Apr 18 04:23:16 PM PDT 24 Apr 18 04:29:48 PM PDT 24 4233660645 ps
T732 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1738183550 Apr 18 04:54:06 PM PDT 24 Apr 18 05:02:27 PM PDT 24 4436627990 ps
T1058 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.858103941 Apr 18 04:45:03 PM PDT 24 Apr 18 04:55:24 PM PDT 24 4535457556 ps
T181 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1809608555 Apr 18 04:22:58 PM PDT 24 Apr 18 04:26:30 PM PDT 24 2469213212 ps
T1059 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3438644839 Apr 18 04:21:18 PM PDT 24 Apr 18 04:32:54 PM PDT 24 4714164312 ps
T736 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1304108017 Apr 18 04:50:26 PM PDT 24 Apr 18 05:00:56 PM PDT 24 5613052130 ps
T1060 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1837980361 Apr 18 04:41:12 PM PDT 24 Apr 18 05:01:42 PM PDT 24 10301028066 ps
T362 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2391261026 Apr 18 04:49:14 PM PDT 24 Apr 18 05:01:40 PM PDT 24 5569392690 ps
T1061 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1732078976 Apr 18 04:45:17 PM PDT 24 Apr 18 04:55:51 PM PDT 24 6214834767 ps
T375 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3939100099 Apr 18 04:25:58 PM PDT 24 Apr 18 05:33:22 PM PDT 24 18154238388 ps
T1062 /workspace/coverage/default/0.chip_sw_example_concurrency.791334243 Apr 18 04:16:34 PM PDT 24 Apr 18 04:19:24 PM PDT 24 2092770304 ps
T1063 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.589227953 Apr 18 04:16:03 PM PDT 24 Apr 18 04:24:13 PM PDT 24 6809529160 ps
T746 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898007201 Apr 18 04:49:31 PM PDT 24 Apr 18 04:56:22 PM PDT 24 4094176824 ps
T1064 /workspace/coverage/default/42.chip_sw_all_escalation_resets.559091514 Apr 18 04:49:32 PM PDT 24 Apr 18 04:57:42 PM PDT 24 3774952196 ps
T435 /workspace/coverage/default/2.chip_jtag_mem_access.2855526277 Apr 18 04:32:36 PM PDT 24 Apr 18 04:54:13 PM PDT 24 13357974460 ps
T749 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289772213 Apr 18 04:50:18 PM PDT 24 Apr 18 04:57:01 PM PDT 24 3478900396 ps
T1065 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1869759258 Apr 18 04:45:35 PM PDT 24 Apr 18 05:00:44 PM PDT 24 11079619124 ps
T376 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.801385284 Apr 18 04:31:41 PM PDT 24 Apr 18 04:36:45 PM PDT 24 2546126492 ps
T1066 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.892562648 Apr 18 04:20:21 PM PDT 24 Apr 18 04:22:09 PM PDT 24 2513566494 ps
T1067 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1907323811 Apr 18 04:30:46 PM PDT 24 Apr 18 04:37:07 PM PDT 24 2886419540 ps
T1068 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.294107614 Apr 18 04:18:09 PM PDT 24 Apr 18 04:42:43 PM PDT 24 15937381207 ps
T111 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3928813898 Apr 18 04:21:17 PM PDT 24 Apr 18 04:57:55 PM PDT 24 17679906754 ps
T786 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3609026243 Apr 18 04:47:54 PM PDT 24 Apr 18 04:54:55 PM PDT 24 3846253696 ps
T1069 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.538765256 Apr 18 04:37:46 PM PDT 24 Apr 18 04:44:34 PM PDT 24 19025135970 ps
T324 /workspace/coverage/default/2.chip_sw_pattgen_ios.3754739447 Apr 18 04:34:11 PM PDT 24 Apr 18 04:38:56 PM PDT 24 2978244992 ps
T1070 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1795859766 Apr 18 04:36:09 PM PDT 24 Apr 18 04:57:50 PM PDT 24 11054705317 ps
T70 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1657420964 Apr 18 04:18:39 PM PDT 24 Apr 18 04:22:34 PM PDT 24 2939799648 ps
T314 /workspace/coverage/default/1.chip_plic_all_irqs_0.4158690164 Apr 18 04:29:33 PM PDT 24 Apr 18 04:50:12 PM PDT 24 5601230520 ps
T734 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3843080580 Apr 18 04:45:36 PM PDT 24 Apr 18 04:58:30 PM PDT 24 6378562600 ps
T1071 /workspace/coverage/default/0.chip_tap_straps_testunlock0.174703550 Apr 18 04:20:12 PM PDT 24 Apr 18 04:28:34 PM PDT 24 5580628561 ps
T1072 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2477844980 Apr 18 04:21:43 PM PDT 24 Apr 18 04:31:43 PM PDT 24 4536537000 ps
T1073 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4169823535 Apr 18 04:28:32 PM PDT 24 Apr 18 04:36:40 PM PDT 24 4284577120 ps
T768 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2269165065 Apr 18 04:49:40 PM PDT 24 Apr 18 04:56:11 PM PDT 24 4292306234 ps
T1074 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1133957392 Apr 18 04:25:02 PM PDT 24 Apr 18 04:36:11 PM PDT 24 4888374734 ps
T1075 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4159787245 Apr 18 04:21:24 PM PDT 24 Apr 18 04:54:04 PM PDT 24 9397203728 ps
T1076 /workspace/coverage/default/1.chip_sw_kmac_idle.3256784267 Apr 18 04:28:23 PM PDT 24 Apr 18 04:32:56 PM PDT 24 2577051240 ps
T1077 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.4045941297 Apr 18 04:20:28 PM PDT 24 Apr 18 04:36:25 PM PDT 24 5951568008 ps
T213 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1022539035 Apr 18 04:19:14 PM PDT 24 Apr 18 04:30:03 PM PDT 24 5992039592 ps
T1078 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2397378917 Apr 18 04:19:24 PM PDT 24 Apr 18 04:25:54 PM PDT 24 3374765436 ps
T431 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2019313159 Apr 18 04:21:46 PM PDT 24 Apr 18 04:32:13 PM PDT 24 9741207789 ps
T281 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3253165835 Apr 18 04:40:51 PM PDT 24 Apr 18 04:44:55 PM PDT 24 2667216770 ps
T1079 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.271012501 Apr 18 04:40:16 PM PDT 24 Apr 18 04:45:16 PM PDT 24 3067956031 ps
T1080 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3868758033 Apr 18 04:24:19 PM PDT 24 Apr 18 04:31:08 PM PDT 24 5298977020 ps
T779 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.816317343 Apr 18 04:47:11 PM PDT 24 Apr 18 04:53:31 PM PDT 24 3939754260 ps
T1081 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1953032857 Apr 18 04:16:31 PM PDT 24 Apr 18 04:20:15 PM PDT 24 3742532693 ps
T332 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3256097020 Apr 18 04:35:43 PM PDT 24 Apr 18 04:45:34 PM PDT 24 3692172414 ps
T1082 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2870913278 Apr 18 04:20:50 PM PDT 24 Apr 18 04:31:42 PM PDT 24 4278544968 ps
T100 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2521721661 Apr 18 04:24:13 PM PDT 24 Apr 18 04:30:35 PM PDT 24 6908648318 ps
T755 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2364748151 Apr 18 04:50:37 PM PDT 24 Apr 18 05:00:32 PM PDT 24 5509687918 ps
T714 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4193345918 Apr 18 04:37:29 PM PDT 24 Apr 18 04:56:53 PM PDT 24 11786249260 ps
T1083 /workspace/coverage/default/1.chip_sw_example_manufacturer.513114614 Apr 18 04:25:30 PM PDT 24 Apr 18 04:28:38 PM PDT 24 2666131488 ps
T37 /workspace/coverage/default/0.chip_sw_spi_device_tpm.814671000 Apr 18 04:19:13 PM PDT 24 Apr 18 04:24:52 PM PDT 24 3039064470 ps
T1084 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1293523844 Apr 18 04:18:56 PM PDT 24 Apr 18 04:31:50 PM PDT 24 4594181452 ps
T258 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3852851637 Apr 18 04:47:18 PM PDT 24 Apr 18 04:57:57 PM PDT 24 5870366072 ps
T151 /workspace/coverage/default/0.chip_plic_all_irqs_10.3510632819 Apr 18 04:20:22 PM PDT 24 Apr 18 04:30:49 PM PDT 24 3941145848 ps
T1085 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3692071223 Apr 18 04:20:47 PM PDT 24 Apr 18 05:22:07 PM PDT 24 18067559248 ps
T1086 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1452885620 Apr 18 04:18:32 PM PDT 24 Apr 18 05:05:40 PM PDT 24 20843526804 ps
T330 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2368667433 Apr 18 04:35:11 PM PDT 24 Apr 18 04:46:21 PM PDT 24 4363401088 ps
T1087 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.880504635 Apr 18 04:25:59 PM PDT 24 Apr 18 04:30:51 PM PDT 24 2086290868 ps
T1088 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1316998997 Apr 18 04:37:14 PM PDT 24 Apr 18 04:47:15 PM PDT 24 5065574050 ps
T1089 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2691416794 Apr 18 04:50:23 PM PDT 24 Apr 18 04:58:40 PM PDT 24 4741193774 ps
T1090 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.538328779 Apr 18 04:46:19 PM PDT 24 Apr 18 04:53:53 PM PDT 24 6517881877 ps
T1091 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3145698509 Apr 18 04:38:40 PM PDT 24 Apr 18 04:42:28 PM PDT 24 2500765360 ps
T1092 /workspace/coverage/default/4.chip_tap_straps_prod.1960896001 Apr 18 04:44:05 PM PDT 24 Apr 18 04:47:04 PM PDT 24 2494893539 ps
T1093 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.527870543 Apr 18 04:24:05 PM PDT 24 Apr 18 05:17:54 PM PDT 24 15252129175 ps
T1094 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1554408146 Apr 18 04:38:05 PM PDT 24 Apr 18 04:43:41 PM PDT 24 3498913876 ps
T1095 /workspace/coverage/default/1.chip_sw_aes_masking_off.2927992104 Apr 18 04:25:23 PM PDT 24 Apr 18 04:30:09 PM PDT 24 2418329845 ps
T1096 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.905990879 Apr 18 04:24:42 PM PDT 24 Apr 18 05:04:03 PM PDT 24 26028572514 ps
T60 /workspace/coverage/default/1.chip_jtag_csr_rw.1978351628 Apr 18 04:22:27 PM PDT 24 Apr 18 04:40:10 PM PDT 24 9850001028 ps
T752 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.843721907 Apr 18 04:53:34 PM PDT 24 Apr 18 04:59:09 PM PDT 24 4129096848 ps
T24 /workspace/coverage/default/2.chip_sw_gpio.1716894914 Apr 18 04:34:55 PM PDT 24 Apr 18 04:42:05 PM PDT 24 3624277734 ps
T697 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2797268410 Apr 18 04:22:20 PM PDT 24 Apr 18 04:31:17 PM PDT 24 5337069432 ps
T1097 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3347918214 Apr 18 04:38:19 PM PDT 24 Apr 18 04:41:32 PM PDT 24 1846503226 ps
T764 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2346848945 Apr 18 04:54:18 PM PDT 24 Apr 18 05:03:04 PM PDT 24 5472341688 ps
T144 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1195147081 Apr 18 04:17:47 PM PDT 24 Apr 18 04:27:50 PM PDT 24 3911332200 ps
T722 /workspace/coverage/default/77.chip_sw_all_escalation_resets.353706669 Apr 18 04:52:18 PM PDT 24 Apr 18 05:01:27 PM PDT 24 5817819248 ps
T773 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3688471963 Apr 18 04:50:02 PM PDT 24 Apr 18 04:59:27 PM PDT 24 5680747220 ps
T730 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2035177448 Apr 18 04:46:09 PM PDT 24 Apr 18 04:54:27 PM PDT 24 4021306690 ps
T1098 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1908805082 Apr 18 04:19:02 PM PDT 24 Apr 18 04:40:30 PM PDT 24 6710609788 ps
T767 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416538192 Apr 18 04:49:34 PM PDT 24 Apr 18 04:55:02 PM PDT 24 3780299162 ps
T1099 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.43973910 Apr 18 04:32:52 PM PDT 24 Apr 18 04:36:36 PM PDT 24 3013411750 ps
T1100 /workspace/coverage/default/0.rom_keymgr_functest.1949794262 Apr 18 04:21:46 PM PDT 24 Apr 18 04:30:55 PM PDT 24 3809521484 ps
T784 /workspace/coverage/default/92.chip_sw_all_escalation_resets.585950371 Apr 18 04:53:28 PM PDT 24 Apr 18 05:02:54 PM PDT 24 4429493240 ps
T162 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.452012755 Apr 18 04:35:13 PM PDT 24 Apr 18 04:39:28 PM PDT 24 2500188893 ps
T214 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.917968612 Apr 18 04:41:01 PM PDT 24 Apr 18 04:49:18 PM PDT 24 5173137900 ps
T61 /workspace/coverage/default/2.chip_sw_alert_test.2525563721 Apr 18 04:39:23 PM PDT 24 Apr 18 04:47:03 PM PDT 24 3351109884 ps
T1101 /workspace/coverage/default/2.chip_sival_flash_info_access.4051252166 Apr 18 04:34:39 PM PDT 24 Apr 18 04:39:30 PM PDT 24 2621245716 ps
T394 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3554075216 Apr 18 04:31:00 PM PDT 24 Apr 18 04:37:43 PM PDT 24 7610098136 ps
T1102 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3611483895 Apr 18 04:39:55 PM PDT 24 Apr 18 04:47:33 PM PDT 24 4026569764 ps
T753 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3744757303 Apr 18 04:45:15 PM PDT 24 Apr 18 04:52:02 PM PDT 24 3500923628 ps
T1103 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.395403140 Apr 18 04:21:12 PM PDT 24 Apr 18 04:34:09 PM PDT 24 6336198490 ps
T1104 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.514007694 Apr 18 04:34:53 PM PDT 24 Apr 18 04:53:54 PM PDT 24 6031229471 ps
T1105 /workspace/coverage/default/1.rom_e2e_asm_init_dev.198666849 Apr 18 04:35:48 PM PDT 24 Apr 18 05:30:38 PM PDT 24 15141453678 ps
T723 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3568609823 Apr 18 04:49:41 PM PDT 24 Apr 18 04:56:33 PM PDT 24 4173299692 ps
T1106 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.308498523 Apr 18 04:38:59 PM PDT 24 Apr 18 04:46:03 PM PDT 24 4903834912 ps
T1107 /workspace/coverage/default/0.chip_sw_example_manufacturer.1052494462 Apr 18 04:17:38 PM PDT 24 Apr 18 04:20:32 PM PDT 24 2300220244 ps
T1108 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3754827308 Apr 18 04:26:37 PM PDT 24 Apr 18 05:28:31 PM PDT 24 18026330237 ps
T1109 /workspace/coverage/default/61.chip_sw_all_escalation_resets.937074363 Apr 18 04:50:41 PM PDT 24 Apr 18 05:02:21 PM PDT 24 5401441308 ps
T1110 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3671261531 Apr 18 04:18:54 PM PDT 24 Apr 18 04:21:49 PM PDT 24 2097732770 ps
T201 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1941440861 Apr 18 04:34:41 PM PDT 24 Apr 18 04:44:17 PM PDT 24 4304343060 ps
T1111 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1448924360 Apr 18 04:35:39 PM PDT 24 Apr 18 04:45:13 PM PDT 24 4219681408 ps
T1112 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1465169403 Apr 18 04:35:34 PM PDT 24 Apr 18 04:59:29 PM PDT 24 8683097486 ps
T1113 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1675017070 Apr 18 04:35:04 PM PDT 24 Apr 18 04:41:56 PM PDT 24 4027212396 ps
T1114 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2071093469 Apr 18 04:46:43 PM PDT 24 Apr 18 05:41:58 PM PDT 24 14965998642 ps
T1115 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2028742913 Apr 18 04:41:11 PM PDT 24 Apr 18 04:58:02 PM PDT 24 7139120484 ps
T1116 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1624231934 Apr 18 04:38:44 PM PDT 24 Apr 18 04:50:40 PM PDT 24 8244435248 ps
T1117 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1416586157 Apr 18 04:51:35 PM PDT 24 Apr 18 05:00:20 PM PDT 24 4668541352 ps
T25 /workspace/coverage/default/0.chip_sw_gpio.1135728867 Apr 18 04:16:46 PM PDT 24 Apr 18 04:25:18 PM PDT 24 3929012498 ps
T1118 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.556597029 Apr 18 04:38:45 PM PDT 24 Apr 18 06:14:40 PM PDT 24 23717064700 ps
T760 /workspace/coverage/default/20.chip_sw_all_escalation_resets.453760987 Apr 18 04:46:31 PM PDT 24 Apr 18 04:57:52 PM PDT 24 5204198570 ps
T1119 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2500979936 Apr 18 04:22:56 PM PDT 24 Apr 18 04:29:55 PM PDT 24 3028853666 ps
T1120 /workspace/coverage/default/1.chip_sw_aes_entropy.629113153 Apr 18 04:28:27 PM PDT 24 Apr 18 04:33:13 PM PDT 24 3094394656 ps
T274 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2978215606 Apr 18 04:36:11 PM PDT 24 Apr 18 04:43:56 PM PDT 24 3509020956 ps
T1121 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2125463550 Apr 18 04:20:48 PM PDT 24 Apr 18 04:31:31 PM PDT 24 4650345623 ps
T1122 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1295517206 Apr 18 04:34:56 PM PDT 24 Apr 18 04:51:30 PM PDT 24 11371481891 ps
T1123 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1610981018 Apr 18 04:33:42 PM PDT 24 Apr 18 04:53:20 PM PDT 24 8359862046 ps
T1124 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3911921275 Apr 18 04:46:12 PM PDT 24 Apr 18 04:57:47 PM PDT 24 4412891881 ps
T742 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3670449526 Apr 18 04:46:52 PM PDT 24 Apr 18 04:52:18 PM PDT 24 3057943602 ps
T1125 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2194066733 Apr 18 04:21:27 PM PDT 24 Apr 18 05:04:21 PM PDT 24 13186629880 ps
T1126 /workspace/coverage/default/1.chip_sw_power_idle_load.1413530640 Apr 18 04:30:38 PM PDT 24 Apr 18 04:40:38 PM PDT 24 4351471200 ps
T1127 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.666307106 Apr 18 04:20:27 PM PDT 24 Apr 18 04:24:35 PM PDT 24 2630526133 ps
T1128 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2418811700 Apr 18 04:17:54 PM PDT 24 Apr 18 04:26:16 PM PDT 24 4762305864 ps
T1129 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1306805931 Apr 18 04:41:57 PM PDT 24 Apr 18 04:52:53 PM PDT 24 4674124616 ps
T1130 /workspace/coverage/default/0.chip_sw_example_flash.4188474720 Apr 18 04:16:58 PM PDT 24 Apr 18 04:21:21 PM PDT 24 3211575950 ps
T346 /workspace/coverage/default/1.chip_sival_flash_info_access.739538498 Apr 18 04:22:50 PM PDT 24 Apr 18 04:27:14 PM PDT 24 2880987948 ps
T641 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3245681095 Apr 18 04:26:46 PM PDT 24 Apr 18 04:36:01 PM PDT 24 2797871720 ps
T1131 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2927949118 Apr 18 04:30:25 PM PDT 24 Apr 18 04:43:40 PM PDT 24 4257543840 ps
T55 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2105861037 Apr 18 04:30:36 PM PDT 24 Apr 18 04:54:02 PM PDT 24 19078092864 ps
T31 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.770501376 Apr 18 04:22:15 PM PDT 24 Apr 18 04:28:42 PM PDT 24 2431315734 ps
T1132 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1724837269 Apr 18 04:37:38 PM PDT 24 Apr 18 04:42:11 PM PDT 24 2730127080 ps
T774 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2987583499 Apr 18 04:50:29 PM PDT 24 Apr 18 05:01:50 PM PDT 24 5388984568 ps
T38 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3005650926 Apr 18 04:24:22 PM PDT 24 Apr 18 04:30:21 PM PDT 24 3796457480 ps
T1133 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3779854894 Apr 18 04:36:46 PM PDT 24 Apr 18 04:41:06 PM PDT 24 3099259116 ps
T1134 /workspace/coverage/default/2.chip_sw_example_rom.1876882920 Apr 18 04:33:16 PM PDT 24 Apr 18 04:35:31 PM PDT 24 2749804808 ps
T726 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1693692217 Apr 18 04:47:48 PM PDT 24 Apr 18 04:53:45 PM PDT 24 3566660536 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%