Unified Coverage Report :: Module :: adc_ctrl

Module : adc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon	90.74			90.74

---

Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : adc_ctrl

	Total	Covered	Percent
Totals	37	29	78.38
Total Bits	324	294	90.74
Total Bits 0->1	162	147	90.74
Total Bits 1->0	162	147	90.74

Ports	37	29	78.38
Port Bits	324	294	90.74
Port Bits 0->1	162	147	90.74
Port Bits 1->0	162	147	90.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T126	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T126	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	INPUT
tl_o.a_ready	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T47,T48	Yes	T117,T50,T47	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T60	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T50,T80,*T51	Yes	T117,T50,T60	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T60	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T80,*T117,*T126	Yes	T80,T117,T50	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T50,T80,T51	Yes	T117,T50,T60	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T126,*T47	Yes	T117,T50,T126	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T203,T60	Yes	T82,T203,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T203,T85	Yes	T82,T203,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T203,T85	Yes	T82,T203,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T203,T60	Yes	T82,T203,T60	OUTPUT
adc_o.pd	Yes	Yes	T117,T126,T47	Yes	T117,T126,T47	OUTPUT
adc_o.channel_sel[1:0]	Yes	Yes	T117,T126,T47	Yes	T117,T126,T47	OUTPUT
adc_i.data_valid	Yes	Yes	T117,T126,T47	Yes	T117,T126,T47	INPUT
adc_i.data[9:0]	Yes	Yes	T117,T47,T48	Yes	T117,T47,T48	INPUT
intr_match_pending_o	Yes	Yes	T117,T343,T191	Yes	T117,T343,T191	OUTPUT
wkup_req_o	Yes	Yes	T47,T48,T53	Yes	T117,T47,T48	OUTPUT

*Tests covering at least one bit in the range