Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	133102073	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	9050	9050	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133102073	0	0
T1	6756744	682568	0	0
T2	6756112	682558	0	0
T3	1450010	40095	0	0
T4	655360	8	0	0
T29	2354130	64675	0	0
T36	1426470	48640	0	0
T46	1935710	57908	0	0
T59	1524450	59481	0	0
T64	2342430	82052	0	0
T65	720350	20337	0	0
T82	1165400	27311	0	0
T181	175396	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8445930	8439460	0	0
T2	8445140	8438770	0	0
T3	1450010	1448960	0	0
T29	2354130	2353070	0	0
T36	1426470	1425920	0	0
T46	1935710	1935160	0	0
T59	1524450	1523830	0	0
T64	2342430	2341260	0	0
T65	720350	719730	0	0
T82	1165400	1164820	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8445930	8439460	0	0
T2	8445140	8438770	0	0
T3	1450010	1448960	0	0
T29	2354130	2353070	0	0
T36	1426470	1425920	0	0
T46	1935710	1935160	0	0
T59	1524450	1523830	0	0
T64	2342430	2341260	0	0
T65	720350	719730	0	0
T82	1165400	1164820	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8445930	8439460	0	0
T2	8445140	8438770	0	0
T3	1450010	1448960	0	0
T29	2354130	2353070	0	0
T36	1426470	1425920	0	0
T46	1935710	1935160	0	0
T59	1524450	1523830	0	0
T64	2342430	2341260	0	0
T65	720350	719730	0	0
T82	1165400	1164820	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	9050	9050	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T29	10	10	0	0
T36	10	10	0	0
T46	10	10	0	0
T59	10	10	0	0
T64	10	10	0	0
T65	10	10	0	0
T82	10	10	0	0