Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	39427167	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	39427167	0	0
T1	844593	402693	0	0
T2	844514	402689	0	0
T3	145001	14490	0	0
T29	235413	21695	0	0
T36	142647	14848	0	0
T46	193571	25055	0	0
T59	152445	24744	0	0
T64	234243	30764	0	0
T65	72035	7937	0	0
T82	116540	8883	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	30072998	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	30072998	0	0
T1	844593	206216	0	0
T2	844514	206211	0	0
T3	145001	10283	0	0
T29	235413	17422	0	0
T36	142647	10836	0	0
T46	193571	22347	0	0
T59	152445	17370	0	0
T64	234243	21026	0	0
T65	72035	5503	0	0
T82	116540	6700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	32412956	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	32412956	0	0
T1	844593	38209	0	0
T2	844514	38209	0	0
T3	145001	7739	0	0
T29	235413	12840	0	0
T36	142647	11438	0	0
T46	193571	5198	0	0
T59	152445	8771	0	0
T64	234243	15024	0	0
T65	72035	3494	0	0
T82	116540	5935	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	30944464	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	30944464	0	0
T1	844593	35058	0	0
T2	844514	35057	0	0
T3	145001	7475	0	0
T29	235413	12598	0	0
T36	142647	11142	0	0
T46	193571	4996	0	0
T59	152445	8492	0	0
T64	234243	14634	0	0
T65	72035	3351	0	0
T82	116540	5741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	61122	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	61122	0	0
T1	844593	98	0	0
T2	844514	98	0	0
T3	145001	27	0	0
T29	235413	30	0	0
T36	142647	94	0	0
T46	193571	78	0	0
T59	152445	26	0	0
T64	234243	151	0	0
T65	72035	13	0	0
T82	116540	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	61122	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	61122	0	0
T1	844593	98	0	0
T2	844514	98	0	0
T3	145001	27	0	0
T29	235413	30	0	0
T36	142647	94	0	0
T46	193571	78	0	0
T59	152445	26	0	0
T64	234243	151	0	0
T65	72035	13	0	0
T82	116540	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	49523	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	49523	0	0
T1	844593	98	0	0
T2	844514	98	0	0
T3	145001	25	0	0
T29	235413	28	0	0
T36	142647	93	0	0
T46	193571	77	0	0
T59	152445	23	0	0
T64	234243	95	0	0
T65	72035	12	0	0
T82	116540	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	49523	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	49523	0	0
T1	844593	98	0	0
T2	844514	98	0	0
T3	145001	25	0	0
T29	235413	28	0	0
T36	142647	93	0	0
T46	193571	77	0	0
T59	152445	23	0	0
T64	234243	95	0	0
T65	72035	12	0	0
T82	116540	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	11599	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	11599	0	0
T3	145001	2	0	0
T4	327680	4	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	3	0	0
T64	234243	56	0	0
T65	72035	1	0	0
T82	116540	1	0	0
T181	87698	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410811267	11599	0	0
DepthKnown_A	410811267	410714371	0	0
RvalidKnown_A	410811267	410714371	0	0
WreadyKnown_A	410811267	410714371	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	11599	0	0
T3	145001	2	0	0
T4	327680	4	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	3	0	0
T64	234243	56	0	0
T65	72035	1	0	0
T82	116540	1	0	0
T181	87698	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	410714371	0	0
T1	844593	843946	0	0
T2	844514	843877	0	0
T3	145001	144896	0	0
T29	235413	235307	0	0
T36	142647	142592	0	0
T46	193571	193516	0	0
T59	152445	152383	0	0
T64	234243	234126	0	0
T65	72035	71973	0	0
T82	116540	116482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T36	1	1	0	0
T46	1	1	0	0
T59	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T82	1	1	0	0