Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30			94.30

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main	94.34			94.34
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	94.71			94.71

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.34			94.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.34			94.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.71			94.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.71			94.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	64	46	71.88
Total Bits	1158	1092	94.30
Total Bits 0->1	579	546	94.30
Total Bits 1->0	579	546	94.30

Ports	64	46	71.88
Port Bits	1158	1092	94.30
Port Bits 0->1	579	546	94.30
Port Bits 1->0	579	546	94.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[17:5]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_o.a_ready	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T186,T121,T122	Yes	T186,T121,T122	OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T39,T186,T121	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T80,*T146,*T186	Yes	T80,T146,T186	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T39,T186,T121	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T186,*T121,*T122	Yes	T187,T186,T121	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T187,T60	Yes	T82,T187,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T187,T60	Yes	T82,T187,T60	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T64,T66,T67	Yes	T64,T66,T67	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_o.req	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T59	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.ack	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	60	41	68.33
Total Bits	1130	1066	94.34
Total Bits 0->1	565	533	94.34
Total Bits 1->0	565	533	94.34

Ports	60	41	68.33
Port Bits	1130	1066	94.34
Port Bits 0->1	565	533	94.34
Port Bits 1->0	565	533	94.34

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[5]	No	No		No		INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[0]	No	No		No		INPUT
ram_tl_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
regs_tl_i.a_user.cmd_intg[0]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T187,T186,T121	Yes	T187,T186,T121	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[4:2]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[17:5]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[1:0]	Yes	Yes	*T80,*T146,*T186	Yes	T80,T146,T186	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T187,T186,T121	Yes	T187,T186,T121	INPUT
regs_tl_i.a_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
regs_tl_o.a_ready	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T186,T80,T188	Yes	T186,T80,T188	OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T39,T186,T121	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T80,*T146,*T186	Yes	T80,T146,T186	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T39,T186,T121	Yes	T39,T187,T186	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T186,*T121,*T122	Yes	T187,T186,T121	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T187,T60	Yes	T82,T187,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T85,T389	Yes	T82,T85,T389	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T85,T389	Yes	T82,T85,T389	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T187,T60	Yes	T82,T187,T60	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T64,T66,T67	Yes	T64,T66,T67	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_o.req	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T59	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.ack	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	58	42	72.41
Total Bits	1096	1038	94.71
Total Bits 0->1	548	519	94.71
Total Bits 1->0	548	519	94.71

Ports	58	42	72.41
Port Bits	1096	1038	94.71
Port Bits 0->1	548	519	94.71
Port Bits 1->0	548	519	94.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
ram_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[11:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T29	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[1:0]	Yes	Yes	*T79,*T81,*T335	Yes	T79,T81,T335	OUTPUT
ram_tl_o.d_source[5:2]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T65,T59	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[19:5]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
regs_tl_o.a_ready	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T121,*T122,*T80	Yes	T121,T122,T80	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T39,T80,T334	Yes	T39,T121,T122	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T80,*T146,*T121	Yes	T80,T146,T121	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T39,T80,T334	Yes	T39,T121,T122	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T121,*T122,*T80	Yes	T121,T122,T80	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T64,T66,T67	Yes	T64,T66,T67	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T121,T122,T229	Yes	T121,T122,T229	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T59	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sram_otp_key_i.ack	Yes	Yes	T121,T122,T229	Yes	T121,T122,T229	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range