Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart1	89.47			89.47
tb.dut.top_earlgrey.u_uart2	89.47			89.47
tb.dut.top_earlgrey.u_uart3	89.54			89.54
tb.dut.top_earlgrey.u_uart0	90.07			90.07

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T328,T141,T71	Yes	T328,T141,T71	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T328,T141,T71	Yes	T328,T141,T71	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T328,T141,T71	Yes	T328,T141,T71	INPUT
tl_o.a_ready	Yes	Yes	T328,T141,T142	Yes	T328,T141,T142	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T328,T141,T142	Yes	T328,T141,T142	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T328,T141,T142	Yes	T328,T141,T142	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T39,T109,T80	Yes	T328,T141,T142	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T328,T141,T142	Yes	T328,T141,T142	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T80,*T146,*T328	Yes	T80,T146,T328	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T39,T109,T80	Yes	T328,T141,T142	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T328,*T141,*T142	Yes	T328,T141,T142	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T328,T141,T142	Yes	T328,T141,T142	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T154,T338	Yes	T82,T154,T338	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T154,T338	Yes	T82,T154,T338	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T141,T124,T39	Yes	T141,T124,T39	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T141,T142,T124	Yes	T141,T142,T124	OUTPUT
intr_rx_watermark_o	Yes	Yes	T141,T142,T124	Yes	T141,T142,T124	OUTPUT
intr_tx_empty_o	Yes	Yes	T141,T142,T124	Yes	T141,T142,T124	OUTPUT
intr_rx_overflow_o	Yes	Yes	T141,T142,T124	Yes	T141,T142,T124	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_break_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_timeout_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_o.a_ready	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T124,T125,T98	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T124,*T125,*T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T124,T125,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T124,*T125,*T98	Yes	T124,T125,T98	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T154,T60	Yes	T82,T154,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T154,T60	Yes	T82,T154,T60	OUTPUT
cio_rx_i	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
cio_tx_o	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
intr_rx_watermark_o	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
intr_tx_empty_o	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
intr_rx_overflow_o	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_break_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_timeout_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	39	31	79.49
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_o.a_ready	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T141,T142,T169	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T141,*T142,*T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T141,T142,T169	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T141,*T142,*T169	Yes	T141,T142,T169	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T148	Yes	T82,T60,T148	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T85,T190	Yes	T82,T85,T190	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T85,T190	Yes	T82,T85,T190	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T148	Yes	T82,T60,T148	OUTPUT
cio_rx_i	Yes	Yes	T141,T142,T339	Yes	T141,T142,T339	INPUT
cio_tx_o	Yes	Yes	T141,T142,T339	Yes	T141,T142,T339	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
intr_rx_watermark_o	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
intr_tx_empty_o	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
intr_rx_overflow_o	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_break_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_timeout_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	39	31	79.49
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_o.a_ready	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T11,T12,T316	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T11,*T12,*T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T11,T12,T316	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T316	Yes	T11,T12,T316	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T338,T60	Yes	T82,T338,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T85,T190	Yes	T82,T85,T190	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T85,T190	Yes	T82,T85,T190	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T338,T60	Yes	T82,T338,T60	OUTPUT
cio_rx_i	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
cio_tx_o	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
intr_rx_watermark_o	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
intr_tx_empty_o	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
intr_rx_overflow_o	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_break_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_timeout_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	INPUT
tl_o.a_ready	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T39,T109,T80	Yes	T328,T39,T271	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T80,*T146,*T328	Yes	T80,T146,T328	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T39,T109,T80	Yes	T328,T39,T271	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T328,*T39,*T271	Yes	T328,T39,T271	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T340	Yes	T82,T60,T340	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T340	Yes	T82,T60,T340	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T39,T271,T99	Yes	T39,T271,T99	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T271,T99,T169	Yes	T271,T99,T169	OUTPUT
intr_rx_watermark_o	Yes	Yes	T271,T99,T169	Yes	T271,T99,T169	OUTPUT
intr_tx_empty_o	Yes	Yes	T271,T99,T169	Yes	T271,T99,T169	OUTPUT
intr_rx_overflow_o	Yes	Yes	T271,T99,T169	Yes	T271,T99,T169	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_break_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_timeout_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T169,T196,T197	Yes	T169,T196,T197	OUTPUT

*Tests covering at least one bit in the range