Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.54			81.54

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	81.54			81.54

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.54			81.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.54			81.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	301	54.73
Total Bits	6824	5564	81.54
Total Bits 0->1	3412	2782	81.54
Total Bits 1->0	3412	2782	81.54

Ports	550	301	54.73
Port Bits	6824	5564	81.54
Port Bits 0->1	3412	2782	81.54
Port Bits 1->0	3412	2782	81.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T64,T154,T155	Yes	T64,T154,T155	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T64,*T154,*T155	Yes	T64,T154,T155	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T146,T156,T157	Yes	T146,T156,T157	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T146,T26,T27	Yes	T146,T26,T27	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T64,T66,T154	Yes	T64,T66,T154	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T3,*T29,*T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T69,*T72,*T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T69,T72,T158	Yes	T69,T72,T158	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[1:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[2]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[6:3]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[7]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[9:8]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[11:10]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[13:12]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[14]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[22:15]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[23]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[29:24]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_data[30]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[31]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T52	Yes	T52	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[1:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[3:2]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_user.data_intg[4]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:5]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T52	Yes	T52	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T78,*T159,*T160	Yes	T78,T159,T160	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T3,T65,T59	Yes	T3,T29,T64	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T78,T159,T160	Yes	T78,T159,T160	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T78,*T159,*T80	Yes	T78,T159,T80	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T78,*T159,*T80	Yes	T78,T159,T80	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T3,T65,T59	Yes	T3,T29,T64	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T78,*T159,*T160	Yes	T78,T159,T160	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T29,T64	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T78,T159,T80	Yes	T78,T159,T80	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T1,T2,T39	Yes	T1,T2,T39	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T52,T61	Yes	T60,T52,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T161,*T162,*T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T52,T61	Yes	T60,T52,T61	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0]	Yes	Yes	*T52,*T161,*T162	Yes	T52,T161,T162	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T161,T162,T163	Yes	T161,T162,T163	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T161,T162,T164	Yes	T161,T162,T164	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T52,*T60,*T61	Yes	T60,T52,T61	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T163,T164,T165	Yes	T161,T162,T60	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T161,T162,T164	Yes	T161,T162,T60	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1:0]	Yes	Yes	*T52,*T161,*T162	Yes	T52,T161,T162	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T163,T164,T165	Yes	T161,T162,T60	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T163,*T164,*T165	Yes	T161,T162,T163	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T161,T162,T60	Yes	T161,T162,T60	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T64,T66,T154	Yes	T64,T66,T154	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T60,T80,T148	Yes	T60,T80,T148	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T60,*T109,*T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T60,*T109,*T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T60,T80,T148	Yes	T60,T80,T148	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[1:0]	Yes	Yes	*T80,*T146,*T109	Yes	T80,T146,T109	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T10,*T150	Yes	T10,T150	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T109,T80,T166	Yes	T109,T80,T166	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T80,T167,T168	Yes	T80,T167,T168	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T109,T80,T148	Yes	T60,T109,T80	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T109,T80,*T148	Yes	T60,T109,T80	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T80,T167,T168	Yes	T80,T167,T168	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T109	Yes	T80,T146,T109	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T109,T80,T148	Yes	T60,T109,T80	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T109,*T80,*T166	Yes	T109,T80,T166	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T80,T167	Yes	T60,T80,T167	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T60,*T109,*T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T60,T80,T167	Yes	T60,T80,T167	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[1:0]	Yes	Yes	*T80,*T146,*T109	Yes	T80,T146,T109	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T109,T80,T166	Yes	T109,T80,T166	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T80,T167,T168	Yes	T80,T167,T168	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T109,T80,T166	Yes	T60,T109,T80	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T109,T80,T166	Yes	T60,T109,T80	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T80,T167,T168	Yes	T80,T167,T168	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T109	Yes	T80,T146,T109	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T109,T80,T166	Yes	T60,T109,T80	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T109,*T80,*T166	Yes	T109,T80,T166	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T60,T109,T80	Yes	T60,T109,T80	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[0]	No	No		No		OUTPUT
tl_usbdev_o.a_source[1]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T14,T15,T169	Yes	T14,T15,T169	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T169	Yes	T14,T15,T169	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	T14,T15,T169	Yes	T14,T15,T169	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T14,T16,T20	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[0]	No	No		No		INPUT
tl_usbdev_i.d_source[1]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T14,T16,T20	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__prim_i.a_ready	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T170,T39,T60	Yes	T170,T39,T60	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T170,T39,T60	Yes	T170,T39,T60	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T29,*T170,*T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T170,T39,T60	Yes	T170,T39,T60	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[0]	No	No		No		OUTPUT
tl_hmac_o.a_source[1]	Yes	Yes	*T29,*T170,*T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T170,*T171,*T172	Yes	T170,T171,T172	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T29,T170,T39	Yes	T29,T170,T39	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T170,T39,T173	Yes	T170,T39,T173	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T170,T39,T173	Yes	T170,T39,T173	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	T170,T39,*T173	Yes	T170,T39,T173	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T170,T39,T60	Yes	T170,T39,T42	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[0]	No	No		No		INPUT
tl_hmac_i.d_source[1]	Yes	Yes	*T170,*T39,*T174	Yes	T170,T39,T174	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T170,T39,T173	Yes	T170,T39,T173	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T170,*T39,*T60	Yes	T170,T39,T42	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T170,T39,T173	Yes	T170,T39,T173	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T175,T176,T97	Yes	T175,T176,T97	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T29,*T175,*T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T175,T176,T97	Yes	T175,T176,T97	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[1:0]	Yes	Yes	*T52,*T29,*T175	Yes	T52,T29,T175	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T175,*T176,*T97	Yes	T175,T176,T97	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T29,T175,T173	Yes	T29,T175,T173	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T29,T175,T174	Yes	T29,T175,T174	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T29,T175,T174	Yes	T29,T175,T174	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T29,T175,*T174	Yes	T29,T175,T174	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T175,T177,T178	Yes	T175,T176,T179	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[1:0]	Yes	Yes	*T52,*T29,*T175	Yes	T52,T29,T175	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T29,T175,T174	Yes	T29,T175,T174	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T175,*T177,*T178	Yes	T175,T176,T179	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T29,T175,T174	Yes	T29,T175,T174	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T65,T180,T178	Yes	T65,T180,T178	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T65,*T180,*T178	Yes	T65,T180,T178	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T65,*T29,*T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T65,T180,T178	Yes	T65,T180,T178	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[1:0]	Yes	Yes	*T80,*T65,*T180	Yes	T80,T65,T180	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T65,T180,T178	Yes	T65,T180,T178	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T29,T155,T173	Yes	T65,T29,T155	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[1:0]	Yes	Yes	*T80,*T65,*T180	Yes	T80,T65,T180	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T29,T155,T173	Yes	T65,T29,T155	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T65,*T29,*T155	Yes	T65,T29,T155	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T65,T29,T155	Yes	T65,T29,T155	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[0]	No	No		No		INPUT
tl_entropy_src_i.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T181,T127,T128	Yes	T181,T127,T128	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[1:0]	Yes	Yes	*T80,*T181,*T127	Yes	T80,T181,T127	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T181,T127,T128	Yes	T181,T127,T128	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T181,T127,T128	Yes	T181,T127,T128	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[1:0]	Yes	Yes	*T80,*T181,*T127	Yes	T80,T181,T127	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T181,*T127,*T128	Yes	T181,T127,T128	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[0]	No	No		No		OUTPUT
tl_edn0_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_edn0_i.d_user.data_intg[1]	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[0]	No	No		No		INPUT
tl_edn0_i.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[0]	No	No		No		OUTPUT
tl_edn1_o.a_source[1]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[5:4]	Yes	Yes	T182,*T183,*T184	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[0]	No	No		No		INPUT
tl_edn1_i.d_source[1]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	Yes	Yes	T182,T183,T184	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T36,T64,T66	Yes	T36,T64,T66	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T59,*T36,*T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[1:0]	Yes	Yes	*T80,*T146,*T59	Yes	T80,T146,T59	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T36,T64,T66	Yes	T36,T64,T66	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T64,T66,T117	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T59	Yes	T80,T146,T59	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T64,T66,T117	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T59,*T36,*T64	Yes	T59,T36,T64	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T59,T36,T64	Yes	T59,T36,T64	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T29,*T127,*T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T79,*T81,*T52	Yes	T79,T81,T52	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	*T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T79,*T81,*T52	Yes	T79,T81,T52	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T29,T127,T128	Yes	T29,T127,T128	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T71,*T177,*T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T71,*T177,*T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[0]	No	No		No		OUTPUT
tl_keymgr_o.a_source[1]	Yes	Yes	*T71,*T177,*T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T71,T179,T185	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[0]	No	No		No		INPUT
tl_keymgr_i.d_source[1]	Yes	Yes	*T71,*T177,*T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T71,T179,T185	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T71,*T177,*T178	Yes	T71,T177,T178	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T52	Yes	T52	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T59,T64,T66	Yes	T59,T64,T66	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T59,T64,T66	Yes	T59,T64,T66	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T65,T59	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T187,T186,T121	Yes	T187,T186,T121	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T39,*T187,*T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0]	Yes	Yes	*T80,*T146,*T186	Yes	T80,T146,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T187,T186,T121	Yes	T187,T186,T121	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T186,T80,T188	Yes	T186,T80,T188	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T39,T186,T121	Yes	T39,T187,T186	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T39,T186,T121	Yes	T39,T186,T121	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T186	Yes	T80,T146,T186	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T39,T186,T121	Yes	T39,T187,T186	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T186,*T121,*T122	Yes	T187,T186,T121	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T39,T187,T186	Yes	T39,T187,T186	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range