Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T141,T142,T13 |
| 0 | 1 | Covered | T141,T142,T13 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T141,T142,T13 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T141,T142,T13 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T141,T142,T13 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T141,T142,T13 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T141,T142,T13 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T141,T142,T13 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T79,T80 |
| 0 | 1 | Covered | T13,T22,T23 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T22,T23 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T22,T23 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T36,T236,T13 |
| 0 | 1 | Covered | T36,T236,T13 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T236,T13,T237 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T236,T13,T237 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T236,T13,T237 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T236,T13,T237 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T36,T37,T38 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T236,T13,T237 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T36,T37,T38 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T236,T13,T237 |
| 0 | 1 | Covered | T236,T13,T237 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T236,T13,T237 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T236,T13,T237 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T236,T13,T237 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T236,T13,T237 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T236,T13,T237 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T79,T80,T7 |
| 0 | 1 | Covered | T5,T6,T8 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T9 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T7 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T30,T32 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T30,T32 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T79,T80,T5 |
| 0 | 1 | Covered | T5,T6,T8 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T8,T30,T32 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T7,T30,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T7,T30,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T30,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T7,T30,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T9,T30 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T30,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T9,T30 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T79,T80,T5 |
| 0 | 1 | Covered | T5,T6,T7 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T28,T31 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T17,T18,T269 |
| 0 | 1 | Covered | T17,T18,T269 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T30,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T30,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T30,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T30,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T30,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T9,T30 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T30,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T9,T30 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T124,T125,T98 |
| 0 | 1 | Covered | T124,T125,T98 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T30,T32 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T30,T32 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T124,T125,T98 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T30,T32 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T30,T32 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T17,T18 |
| 0 | 1 | Covered | T13,T17,T18 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T22,T23 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T30,T32 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T22,T23 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T30,T32 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T18,T47 |
| 0 | 1 | Covered | T13,T18,T47 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T28,T31 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T18,T22 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T18,T22 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T17,T18 |
| 0 | 1 | Covered | T13,T17,T269 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T22,T23 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T22,T23 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T22,T23 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T22,T23 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T17,T18 |
| 0 | 1 | Covered | T13,T17,T18 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T28,T31 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T28,T31 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T18,T22 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T28,T31 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T28,T31 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T18,T22 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T126,T106 |
| 0 | 1 | Covered | T13,T126,T106 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T126,T106 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T126,T106 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T126,T106 |
| 0 | 1 | Covered | T13,T126,T106 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T126,T106 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T126,T106 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T126,T106 |
| 0 | 1 | Covered | T13,T126,T106 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T126,T106 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T126,T106 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T39,T77,T42 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T7 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T39,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T39,T42,T43 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T77,T5,T113 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T7,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T7,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T7,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T7,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T39,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T7,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T39,T42,T43 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T77,T5,T113 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T28,T31 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T39,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T39,T42,T43 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T271,T99,T272 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T39,T271,T99 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T71,T68,T73 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T7,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T7,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T7,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T7,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T7,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T7,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T46,T4,T44 |
| 0 | 1 | Covered | T46,T4,T44 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T28,T31 |
| 1 | 1 | Covered | T6,T7,T26 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T6,T7,T26 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T7,T26 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T6,T7,T26 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T7,T26 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T14,T15,T17 |
| 0 | 1 | Covered | T14,T15,T17 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T18,T19,T6 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T18,T19,T6 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T18,T19,T6 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T6 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T18,T19,T6 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T6 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T46,T4,T44 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T7,T26,T27 |
| 1 | 1 | Covered | T26,T28,T31 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T5,T6,T7 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T17,T18 |
| 0 | 1 | Covered | T13,T17,T18 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T18,T22 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T18,T22 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T18,T22 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T18,T22 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T126,T106 |
| 0 | 1 | Covered | T13,T126,T106 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T126,T106 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T126,T106 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 74 |
1 |
1 |
| 76 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 91 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 30 | 30 | 100.00 |
| Logical | 30 | 30 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION (ie_i ? inout_io : 1'bz)
--1-
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 76
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T126,T106 |
| 0 | 1 | Covered | T13,T126,T106 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 80
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 81
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 81
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T28 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
LINE 81
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 88
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
LINE 88
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T13,T126,T106 |
| 1 | 1 | Covered | T26,T27,T28 |
LINE 89
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T126,T106 |
LINE 89
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T27,T28 |
| 1 | 1 | Covered | T13,T126,T106 |
LINE 91
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T28 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
74 |
1 |
1 |
100.00 |
| TERNARY |
88 |
2 |
2 |
100.00 |
| TERNARY |
89 |
2 |
2 |
100.00 |
| TERNARY |
91 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 (ie_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T126,T106 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T28 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
905 |
905 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
905 |
905 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T36 |
1 |
1 |
0 |
0 |
| T46 |
1 |
1 |
0 |
0 |
| T59 |
1 |
1 |
0 |
0 |
| T64 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T82 |
1 |
1 |
0 |
0 |