Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77			89.77

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	89.77			89.77

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77			89.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77			89.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	370	65.84
Total Bits	7060	6338	89.77
Total Bits 0->1	3530	3169	89.77
Total Bits 1->0	3530	3169	89.77

Ports	562	370	65.84
Port Bits	7060	6338	89.77
Port Bits 0->1	3530	3169	89.77
Port Bits 1->0	3530	3169	89.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_main_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_main_i.a_opcode[1]	No	No		No		INPUT
tl_main_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T64,T66,T154	Yes	T64,T66,T154	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	No	No		No		OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_uart0_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T328,T71,T39	Yes	T328,T71,T39	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_error	No	No		No		INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_user.rsp_intg[1:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart0_i.d_user.rsp_intg[5:4]	Yes	Yes	T39,T109,T80	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_sink	No	No		No		INPUT
tl_uart0_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T328	Yes	T80,T146,T328	INPUT
tl_uart0_i.d_source[5:2]	No	No		No		INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[0]	No	No		No		INPUT
tl_uart0_i.d_size[1]	Yes	Yes	T39,T109,T80	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T328,*T39,*T271	Yes	T328,T39,T271	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T328,T39,T271	Yes	T328,T39,T271	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_uart1_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_error	No	No		No		INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_user.rsp_intg[1:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_sink	No	No		No		INPUT
tl_uart1_i.d_source[0]	No	No		No		INPUT
tl_uart1_i.d_source[1]	Yes	Yes	*T124,*T125,*T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_source[5:2]	No	No		No		INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[0]	No	No		No		INPUT
tl_uart1_i.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T124,*T125,*T98	Yes	T124,T125,T98	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T124,T125,T98	Yes	T124,T125,T98	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_uart2_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_error	No	No		No		INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_user.rsp_intg[1:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_sink	No	No		No		INPUT
tl_uart2_i.d_source[0]	No	No		No		INPUT
tl_uart2_i.d_source[1]	Yes	Yes	*T141,*T142,*T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_source[5:2]	No	No		No		INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[0]	No	No		No		INPUT
tl_uart2_i.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T141,*T142,*T169	Yes	T141,T142,T169	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T141,T142,T169	Yes	T141,T142,T169	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart3_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_uart3_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart3_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_error	No	No		No		INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_user.rsp_intg[1:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart3_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,*T329,*T330	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_sink	No	No		No		INPUT
tl_uart3_i.d_source[0]	No	No		No		INPUT
tl_uart3_i.d_source[1]	Yes	Yes	*T11,*T12,*T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_source[5:2]	No	No		No		INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[0]	No	No		No		INPUT
tl_uart3_i.d_size[1]	Yes	Yes	T148,T329,T330	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T11,*T12,*T316	Yes	T11,T12,T316	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T11,T12,T316	Yes	T11,T12,T316	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T236,T237,T167	Yes	T236,T237,T167	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T236,T237,T167	Yes	T236,T237,T167	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_i2c0_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T236,T237,T60	Yes	T236,T237,T60	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T236,T237,T60	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_error	No	No		No		INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T236,T237,T191	Yes	T236,T237,T191	INPUT
tl_i2c0_i.d_user.rsp_intg[1:0]	Yes	Yes	T236,T237,T148	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,T167,T168	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T236,T237,T148	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_sink	No	No		No		INPUT
tl_i2c0_i.d_source[0]	No	No		No		INPUT
tl_i2c0_i.d_source[1]	Yes	Yes	*T236,*T237,*T148	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_source[5:2]	No	No		No		INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[0]	No	No		No		INPUT
tl_i2c0_i.d_size[1]	Yes	Yes	T148,T167,T168	Yes	T236,T237,T60	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T236,*T237,*T167	Yes	T236,T237,T167	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T236,T237,T60	Yes	T236,T237,T60	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T238,T241,T167	Yes	T238,T241,T167	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T238,T241,T167	Yes	T238,T241,T167	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_i2c1_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T60,T238,T148	Yes	T60,T238,T148	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T60,T238,T148	Yes	T60,T238,T148	INPUT
tl_i2c1_i.d_error	No	No		No		INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T238,T241,T167	Yes	T238,T241,T167	INPUT
tl_i2c1_i.d_user.rsp_intg[1:0]	Yes	Yes	T238,T148,T241	Yes	T60,T238,T148	INPUT
tl_i2c1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,T167,T168	Yes	T60,T238,T148	INPUT
tl_i2c1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T238,T148,T241	Yes	T60,T238,T148	INPUT
tl_i2c1_i.d_sink	No	No		No		INPUT
tl_i2c1_i.d_source[0]	No	No		No		INPUT
tl_i2c1_i.d_source[1]	Yes	Yes	*T238,*T241,*T167	Yes	T60,T238,T241	INPUT
tl_i2c1_i.d_source[5:2]	No	No		No		INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[0]	No	No		No		INPUT
tl_i2c1_i.d_size[1]	Yes	Yes	T148,T167,T168	Yes	T60,T238,T148	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T238,*T241,*T167	Yes	T238,T241,T167	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T60,T238,T148	Yes	T60,T238,T148	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T167,T168,T191	Yes	T167,T168,T191	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T167,T168,T191	Yes	T167,T168,T191	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_i2c2_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T60,T148,T167	Yes	T60,T148,T167	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T60,T148,T167	Yes	T60,T148,T167	INPUT
tl_i2c2_i.d_error	No	No		No		INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T191,T247,T248	Yes	T191,T247,T248	INPUT
tl_i2c2_i.d_user.rsp_intg[1:0]	Yes	Yes	T148,T167,T168	Yes	T60,T148,T167	INPUT
tl_i2c2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T148,T167,T168	Yes	T60,T148,T167	INPUT
tl_i2c2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T148,T167,T168	Yes	T60,T148,T167	INPUT
tl_i2c2_i.d_sink	No	No		No		INPUT
tl_i2c2_i.d_source[0]	No	No		No		INPUT
tl_i2c2_i.d_source[1]	Yes	Yes	*T167,*T168,*T191	Yes	T60,T167,T168	INPUT
tl_i2c2_i.d_source[5:2]	No	No		No		INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[0]	No	No		No		INPUT
tl_i2c2_i.d_size[1]	Yes	Yes	T148,T167,T168	Yes	T60,T148,T167	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T167,*T168,*T191	Yes	T167,T168,T191	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T60,T148,T167	Yes	T60,T148,T167	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T331,T151,T152	Yes	T331,T151,T152	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pattgen_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T331,T151,T152	Yes	T331,T151,T152	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_pattgen_o.a_opcode[1]	No	No		No		OUTPUT
tl_pattgen_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T60,T331,T151	Yes	T60,T331,T151	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T60,T331,T151	Yes	T60,T331,T151	INPUT
tl_pattgen_i.d_error	No	No		No		INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T331,T151,T152	Yes	T331,T151,T152	INPUT
tl_pattgen_i.d_user.rsp_intg[1:0]	Yes	Yes	T331,T151,T152	Yes	T60,T331,T151	INPUT
tl_pattgen_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pattgen_i.d_user.rsp_intg[5:4]	Yes	Yes	T52,*T331,*T151	Yes	T60,T331,T151	INPUT
tl_pattgen_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T331,T151,T152	Yes	T60,T331,T151	INPUT
tl_pattgen_i.d_sink	No	No		No		INPUT
tl_pattgen_i.d_source[1:0]	Yes	Yes	*T52,*T331,*T151	Yes	T52,T331,T151	INPUT
tl_pattgen_i.d_source[5:2]	No	No		No		INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[0]	No	No		No		INPUT
tl_pattgen_i.d_size[1]	Yes	Yes	T52	Yes	T60,T331,T151	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T331,*T151,*T152	Yes	T331,T151,T152	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T60,T331,T151	Yes	T60,T331,T151	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T126,T106,T143	Yes	T126,T106,T143	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T126,T106,T143	Yes	T126,T106,T143	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_pwm_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T60,T126,T106	Yes	T60,T126,T106	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T60,T126,T106	Yes	T60,T126,T106	INPUT
tl_pwm_aon_i.d_error	No	No		No		INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T126,T106,T143	Yes	T126,T106,T143	INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T126,T106,T143	Yes	T60,T126,T106	INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwm_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T52,*T126,*T106	Yes	T60,T126,T106	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T126,T106,T143	Yes	T60,T126,T106	INPUT
tl_pwm_aon_i.d_sink	No	No		No		INPUT
tl_pwm_aon_i.d_source[1:0]	Yes	Yes	*T52,*T126,*T106	Yes	T52,T60,T126	INPUT
tl_pwm_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[0]	No	No		No		INPUT
tl_pwm_aon_i.d_size[1]	Yes	Yes	T52	Yes	T60,T126,T106	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T126,*T106,*T143	Yes	T126,T106,T143	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T60,T126,T106	Yes	T60,T126,T106	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_gpio_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_gpio_o.a_opcode[1]	No	No		No		OUTPUT
tl_gpio_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_gpio_i.d_error	No	No		No		INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T13,T22,T23	Yes	T13,T22,T23	INPUT
tl_gpio_i.d_user.rsp_intg[1:0]	Yes	Yes	T13,T126,T22	Yes	T13,T60,T126	INPUT
tl_gpio_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_gpio_i.d_user.rsp_intg[5:4]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_gpio_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T13,T126,T22	Yes	T13,T60,T126	INPUT
tl_gpio_i.d_sink	No	No		No		INPUT
tl_gpio_i.d_source[0]	No	No		No		INPUT
tl_gpio_i.d_source[1]	Yes	Yes	*T3,*T29,*T64	Yes	T3,T65,T59	INPUT
tl_gpio_i.d_source[5:2]	No	No		No		INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[0]	No	No		No		INPUT
tl_gpio_i.d_size[1]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T3,*T29,*T64	Yes	T3,T65,T59	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T36,T77,T80	Yes	T36,T77,T80	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_device_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T36,T77,T80	Yes	T36,T77,T80	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_spi_device_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_device_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T36,T60,T77	Yes	T36,T60,T77	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T36,T60,T77	Yes	T36,T60,T77	INPUT
tl_spi_device_i.d_error	No	No		No		INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T36,T77,T80	Yes	T36,T77,T80	INPUT
tl_spi_device_i.d_user.rsp_intg[1:0]	Yes	Yes	T36,T77,T80	Yes	T36,T77,T80	INPUT
tl_spi_device_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_device_i.d_user.rsp_intg[5:4]	Yes	Yes	T36,T77,T80	Yes	T36,T60,T77	INPUT
tl_spi_device_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T36,T60,T77	Yes	T36,T77,T80	INPUT
tl_spi_device_i.d_sink	No	No		No		INPUT
tl_spi_device_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T36	Yes	T80,T146,T36	INPUT
tl_spi_device_i.d_source[5:2]	No	No		No		INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[0]	No	No		No		INPUT
tl_spi_device_i.d_size[1]	Yes	Yes	T36,T77,T80	Yes	T36,T60,T77	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T36,*T60,*T77	Yes	T36,T77,T80	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T36,T60,T77	Yes	T36,T60,T77	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T283,T288,T126	Yes	T283,T288,T126	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_timer_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T283,T288,T126	Yes	T283,T288,T126	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_rv_timer_o.a_opcode[1]	No	No		No		OUTPUT
tl_rv_timer_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T283,T288,T60	Yes	T283,T288,T60	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T283,T288,T60	Yes	T283,T288,T60	INPUT
tl_rv_timer_i.d_error	No	No		No		INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T283,T288,T80	Yes	T283,T288,T80	INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0]	Yes	Yes	T283,T288,T126	Yes	T283,T288,T60	INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4]	Yes	Yes	T126,T80,T325	Yes	T283,T288,T60	INPUT
tl_rv_timer_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T283,T288,T126	Yes	T283,T288,T60	INPUT
tl_rv_timer_i.d_sink	No	No		No		INPUT
tl_rv_timer_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T283	Yes	T80,T146,T283	INPUT
tl_rv_timer_i.d_source[5:2]	No	No		No		INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[0]	No	No		No		INPUT
tl_rv_timer_i.d_size[1]	Yes	Yes	T126,T80,T325	Yes	T283,T288,T60	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T283,*T288,*T126	Yes	T283,T288,T126	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T283,T288,T60	Yes	T283,T288,T60	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_pwrmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_error	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T308,*T39,*T332	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_sink	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[1:0]	Yes	Yes	*T52,*T3,*T59	Yes	T52,T3,T59	INPUT
tl_pwrmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_size[1]	Yes	Yes	T308,T39,T332	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T59,*T29	Yes	T3,T59,T29	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_rstmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_error	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T29,T64,T4	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T29,T64	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_sink	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[1:0]	Yes	Yes	*T52,*T3,*T29	Yes	T52,T3,T65	INPUT
tl_rstmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_size[1]	Yes	Yes	T29,T64,T4	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T65,T59	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T29,T46,T11	Yes	T29,T46,T11	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T65,T29,T46	Yes	T65,T29,T46	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_clkmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T46,T11,T333	Yes	T46,T11,T333	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[1:0]	Yes	Yes	*T80,*T1,*T2	Yes	T80,T1,T2	INPUT
tl_clkmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_size[1]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T29,*T46,*T11	Yes	T29,T46,T11	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_pinmux_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	No	No		No		INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	No	No		No		INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_otp_ctrl__core_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[1:0]	Yes	Yes	*T77,*T209,*T52	Yes	T77,T209,T52	INPUT
tl_otp_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T210,*T211,*T212	Yes	T210,T211,T212	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T52	Yes	T52	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T3,T65,T59	Yes	T3,T65,T59	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T3,T65,T59	Yes	T3,T29,T64	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2:0]	Yes	Yes	*T52,*T3,*T65	Yes	T52,T3,T29	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	*T52,*T3,*T29	Yes	T52,T3,T65	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T3,T65,T59	Yes	T3,T29,T64	INPUT
tl_otp_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[0]	Yes	Yes	*T52	Yes	T52	INPUT
tl_otp_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_size[1]	Yes	Yes	T52	Yes	T52	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T29,T64	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T52	Yes	T52	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_lc_ctrl_o.a_opcode[1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_error	No	No		No		INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T44,T45	Yes	T4,T44,T45	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T44,T45	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T4,T44,T45	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_sink	No	No		No		INPUT
tl_lc_ctrl_i.d_source[1:0]	Yes	Yes	*T78,*T159,*T160	Yes	T78,T159,T160	INPUT
tl_lc_ctrl_i.d_source[5:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[0]	No	No		No		INPUT
tl_lc_ctrl_i.d_size[1]	Yes	Yes	T4,T44,T45	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T4,*T44,*T45	Yes	T4,T44,T212	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T4,T44,T212	Yes	T4,T44,T212	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T114,T139,T137	Yes	T114,T139,T137	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T114,T139,T137	Yes	T114,T139,T137	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T1	Yes	T80,T146,T1	INPUT
tl_sensor_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_size[1]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_alert_handler_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_alert_handler_o.a_opcode[1]	No	No		No		OUTPUT
tl_alert_handler_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_error	No	No		No		INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0]	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4]	Yes	Yes	T64,T66,T67	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T59,T64,T66	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_sink	No	No		No		INPUT
tl_alert_handler_i.d_source[1:0]	Yes	Yes	*T80,*T59,*T82	Yes	T80,T59,T82	INPUT
tl_alert_handler_i.d_source[5:2]	No	No		No		INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[0]	No	No		No		INPUT
tl_alert_handler_i.d_size[1]	Yes	Yes	T64,T66,T67	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T59,*T82,*T64	Yes	T59,T82,T64	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T59,T82,T64	Yes	T59,T82,T64	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T121,*T122,*T80	Yes	T121,T122,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T39,T80,T334	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T121	Yes	T80,T146,T121	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1]	Yes	Yes	T39,T80,T334	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T121,*T122,*T80	Yes	T121,T122,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T29	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0]	Yes	Yes	*T79,*T81,*T335	Yes	T79,T81,T335	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T3,*T65,*T59	Yes	T3,T65,T59	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_aon_timer_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_error	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T29,T64,T66	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_sink	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[1:0]	Yes	Yes	*T80,*T3,*T59	Yes	T80,T3,T59	INPUT
tl_aon_timer_aon_i.d_source[5:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_size[1]	Yes	Yes	T29,T64,T66	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T3,*T59,*T29	Yes	T3,T59,T29	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T3,T59,T29	Yes	T3,T59,T29	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T80,*T146,*T308	Yes	T80,T146,T308	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_size[1]	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T308,*T286,*T17	Yes	T308,T286,T17	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T308,T286,T17	Yes	T308,T286,T17	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T126	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T126	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	INPUT
tl_adc_ctrl_aon_i.d_error	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T117,T47,T48	Yes	T117,T50,T47	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T60	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T50,T80,*T51	Yes	T117,T50,T60	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T117,T50,T126	Yes	T117,T50,T60	INPUT
tl_adc_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T80,*T117,*T126	Yes	T80,T117,T50	INPUT
tl_adc_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_size[1]	Yes	Yes	T50,T80,T51	Yes	T117,T50,T60	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T117,*T126,*T47	Yes	T117,T50,T126	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T117,T50,T60	Yes	T117,T50,T60	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_ast_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_ast_o.a_opcode[1]	No	No		No		OUTPUT
tl_ast_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	No	No		No		INPUT
tl_ast_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	No	No		No		INPUT
tl_ast_i.d_source[0]	No	No		No		INPUT
tl_ast_i.d_source[5:1]	Yes	Yes	T79,T80,*T81	Yes	T79,T80,T81	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[0]	No	No		No		INPUT
tl_ast_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	No	No		No		INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range