Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	821622534	3102	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	821622534	3102	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	821622534	3102	0	0
T1	844593	10	0	0
T2	844514	10	0	0
T3	145001	2	0	0
T17	109679	0	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	2	0	0
T64	234243	4	0	0
T65	72035	1	0	0
T82	116540	1	0	0
T162	93723	0	0	0
T176	152897	0	0	0
T198	239160	0	0	0
T203	521164	0	0	0
T230	82636	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T280	0	4	0	0
T300	612842	0	0	0
T301	91590	0	0	0
T314	0	4	0	0
T315	0	9	0	0
T316	209454	0	0	0
T317	228858	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	821622534	3102	0	0
T1	844593	10	0	0
T2	844514	10	0	0
T3	145001	2	0	0
T17	109679	0	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	2	0	0
T64	234243	4	0	0
T65	72035	1	0	0
T82	116540	1	0	0
T162	93723	0	0	0
T176	152897	0	0	0
T198	239160	0	0	0
T203	521164	0	0	0
T230	82636	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T280	0	4	0	0
T300	612842	0	0	0
T301	91590	0	0	0
T314	0	4	0	0
T315	0	9	0	0
T316	209454	0	0	0
T317	228858	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	410811267	29	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	410811267	29	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	29	0	0
T17	109679	0	0	0
T162	93723	0	0	0
T176	152897	0	0	0
T198	239160	0	0	0
T203	521164	0	0	0
T230	82636	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T280	0	4	0	0
T300	612842	0	0	0
T301	91590	0	0	0
T314	0	4	0	0
T315	0	9	0	0
T316	209454	0	0	0
T317	228858	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	29	0	0
T17	109679	0	0	0
T162	93723	0	0	0
T176	152897	0	0	0
T198	239160	0	0	0
T203	521164	0	0	0
T230	82636	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T280	0	4	0	0
T300	612842	0	0	0
T301	91590	0	0	0
T314	0	4	0	0
T315	0	9	0	0
T316	209454	0	0	0
T317	228858	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	410811267	3073	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	410811267	3073	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	3073	0	0
T1	844593	10	0	0
T2	844514	10	0	0
T3	145001	2	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	2	0	0
T64	234243	4	0	0
T65	72035	1	0	0
T82	116540	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	410811267	3073	0	0
T1	844593	10	0	0
T2	844514	10	0	0
T3	145001	2	0	0
T29	235413	2	0	0
T36	142647	1	0	0
T46	193571	1	0	0
T59	152445	2	0	0
T64	234243	4	0	0
T65	72035	1	0	0
T82	116540	1	0	0