SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 | ||||
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.32 | 96.47 | 89.29 | 87.66 | 100.00 | 68.18 | u_rv_core_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.15 | 100.00 | 84.62 | 100.00 | 100.00 | u_edn_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 821622534 | 3102 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 821622534 | 3102 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 821622534 | 3102 | 0 | 0 |
T1 | 844593 | 10 | 0 | 0 |
T2 | 844514 | 10 | 0 | 0 |
T3 | 145001 | 2 | 0 | 0 |
T17 | 109679 | 0 | 0 | 0 |
T29 | 235413 | 2 | 0 | 0 |
T36 | 142647 | 1 | 0 | 0 |
T46 | 193571 | 1 | 0 | 0 |
T59 | 152445 | 2 | 0 | 0 |
T64 | 234243 | 4 | 0 | 0 |
T65 | 72035 | 1 | 0 | 0 |
T82 | 116540 | 1 | 0 | 0 |
T162 | 93723 | 0 | 0 | 0 |
T176 | 152897 | 0 | 0 | 0 |
T198 | 239160 | 0 | 0 | 0 |
T203 | 521164 | 0 | 0 | 0 |
T230 | 82636 | 4 | 0 | 0 |
T231 | 0 | 4 | 0 | 0 |
T232 | 0 | 4 | 0 | 0 |
T280 | 0 | 4 | 0 | 0 |
T300 | 612842 | 0 | 0 | 0 |
T301 | 91590 | 0 | 0 | 0 |
T314 | 0 | 4 | 0 | 0 |
T315 | 0 | 9 | 0 | 0 |
T316 | 209454 | 0 | 0 | 0 |
T317 | 228858 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 821622534 | 3102 | 0 | 0 |
T1 | 844593 | 10 | 0 | 0 |
T2 | 844514 | 10 | 0 | 0 |
T3 | 145001 | 2 | 0 | 0 |
T17 | 109679 | 0 | 0 | 0 |
T29 | 235413 | 2 | 0 | 0 |
T36 | 142647 | 1 | 0 | 0 |
T46 | 193571 | 1 | 0 | 0 |
T59 | 152445 | 2 | 0 | 0 |
T64 | 234243 | 4 | 0 | 0 |
T65 | 72035 | 1 | 0 | 0 |
T82 | 116540 | 1 | 0 | 0 |
T162 | 93723 | 0 | 0 | 0 |
T176 | 152897 | 0 | 0 | 0 |
T198 | 239160 | 0 | 0 | 0 |
T203 | 521164 | 0 | 0 | 0 |
T230 | 82636 | 4 | 0 | 0 |
T231 | 0 | 4 | 0 | 0 |
T232 | 0 | 4 | 0 | 0 |
T280 | 0 | 4 | 0 | 0 |
T300 | 612842 | 0 | 0 | 0 |
T301 | 91590 | 0 | 0 | 0 |
T314 | 0 | 4 | 0 | 0 |
T315 | 0 | 9 | 0 | 0 |
T316 | 209454 | 0 | 0 | 0 |
T317 | 228858 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 410811267 | 29 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 410811267 | 29 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410811267 | 29 | 0 | 0 |
T17 | 109679 | 0 | 0 | 0 |
T162 | 93723 | 0 | 0 | 0 |
T176 | 152897 | 0 | 0 | 0 |
T198 | 239160 | 0 | 0 | 0 |
T203 | 521164 | 0 | 0 | 0 |
T230 | 82636 | 4 | 0 | 0 |
T231 | 0 | 4 | 0 | 0 |
T232 | 0 | 4 | 0 | 0 |
T280 | 0 | 4 | 0 | 0 |
T300 | 612842 | 0 | 0 | 0 |
T301 | 91590 | 0 | 0 | 0 |
T314 | 0 | 4 | 0 | 0 |
T315 | 0 | 9 | 0 | 0 |
T316 | 209454 | 0 | 0 | 0 |
T317 | 228858 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410811267 | 29 | 0 | 0 |
T17 | 109679 | 0 | 0 | 0 |
T162 | 93723 | 0 | 0 | 0 |
T176 | 152897 | 0 | 0 | 0 |
T198 | 239160 | 0 | 0 | 0 |
T203 | 521164 | 0 | 0 | 0 |
T230 | 82636 | 4 | 0 | 0 |
T231 | 0 | 4 | 0 | 0 |
T232 | 0 | 4 | 0 | 0 |
T280 | 0 | 4 | 0 | 0 |
T300 | 612842 | 0 | 0 | 0 |
T301 | 91590 | 0 | 0 | 0 |
T314 | 0 | 4 | 0 | 0 |
T315 | 0 | 9 | 0 | 0 |
T316 | 209454 | 0 | 0 | 0 |
T317 | 228858 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 410811267 | 3073 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 410811267 | 3073 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410811267 | 3073 | 0 | 0 |
T1 | 844593 | 10 | 0 | 0 |
T2 | 844514 | 10 | 0 | 0 |
T3 | 145001 | 2 | 0 | 0 |
T29 | 235413 | 2 | 0 | 0 |
T36 | 142647 | 1 | 0 | 0 |
T46 | 193571 | 1 | 0 | 0 |
T59 | 152445 | 2 | 0 | 0 |
T64 | 234243 | 4 | 0 | 0 |
T65 | 72035 | 1 | 0 | 0 |
T82 | 116540 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410811267 | 3073 | 0 | 0 |
T1 | 844593 | 10 | 0 | 0 |
T2 | 844514 | 10 | 0 | 0 |
T3 | 145001 | 2 | 0 | 0 |
T29 | 235413 | 2 | 0 | 0 |
T36 | 142647 | 1 | 0 | 0 |
T46 | 193571 | 1 | 0 | 0 |
T59 | 152445 | 2 | 0 | 0 |
T64 | 234243 | 4 | 0 | 0 |
T65 | 72035 | 1 | 0 | 0 |
T82 | 116540 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |