Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45			95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn1	92.56			92.56
tb.dut.top_earlgrey.u_edn0	95.19			95.19

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.56			92.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.56			92.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19			95.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19			95.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	63	80.77
Total Bits	1208	1153	95.45
Total Bits 0->1	604	578	95.70
Total Bits 1->0	604	575	95.20

Ports	78	63	80.77
Port Bits	1208	1153	95.45
Port Bits 0->1	604	578	95.70
Port Bits 1->0	604	575	95.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	Yes	Yes	T323,T324,T403	Yes	T323,T324,T403	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T131,T207,T208	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T119,T129,T130	Yes	T119,T129,T131	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T324,T403,T404	Yes	T324,T403,T404	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T323,T324,T403	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T323,T324,T403	Yes	T323,T324,T403	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T3,T82	Yes	T1,T3,T82	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T131,T405,T406	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T407,T408,T409	Yes	T407,T408,T323	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T127,T189,T399	Yes	T127,T128,T119	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T128,T119,T129	Yes	T128,T119,T129	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T190	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T190	Yes	T82,T84,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T82,T203,T410	Yes	T82,T203,T410	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T203,T325	Yes	T82,T203,T325	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T203,T325	Yes	T82,T203,T325	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T82,T203,T410	Yes	T82,T203,T410	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T300,T348,T191	Yes	T300,T348,T191	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	37	74.00
Total Bits	712	659	92.56
Total Bits 0->1	356	330	92.70
Total Bits 1->0	356	329	92.42

Ports	50	37	74.00
Port Bits	712	659	92.56
Port Bits 0->1	356	330	92.70
Port Bits 1->0	356	329	92.42

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_o.a_ready	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T182,*T183,*T184	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T182,T183,T184	Yes	T127,T128,T119	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_i[0].edn_req	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T127,T189,T399	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T128,T119,T129	Yes	T128,T119,T129	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T85	Yes	T82,T84,T190	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T190	Yes	T82,T84,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T82,T60,T411	Yes	T82,T60,T411	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T325,T84	Yes	T82,T325,T84	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T325,T84	Yes	T82,T325,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T84	Yes	T82,T60,T84	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T82,T60,T411	Yes	T82,T60,T411	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T300,T348,T191	Yes	T300,T348,T191	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	61	78.21
Total Bits	1206	1148	95.19
Total Bits 0->1	603	576	95.52
Total Bits 1->0	603	572	94.86

Ports	78	61	78.21
Port Bits	1206	1148	95.19
Port Bits 0->1	603	576	95.52
Port Bits 1->0	603	572	94.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.data_intg[1]	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:2]	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T128,*T119	Yes	T127,T128,T119	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	Yes	Yes	T323,T324,T403	Yes	T323,T324,T403	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T263,T323,T324	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T71,T177,T178	Yes	T71,T177,T178	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T131,T207,T208	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T119,T129,T130	Yes	T119,T129,T131	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T324,T403,T404	Yes	T324,T403,T404	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T323,T324,T403	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T323,T324,T403	Yes	T323,T324,T403	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T3,T82	Yes	T1,T3,T82	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T131,T405,T406	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T407,T408,T409	Yes	T407,T408,T323	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T127,T128,T119	Yes	T127,T128,T119	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T127,T189,T399	Yes	T127,T128,T119	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T128,T119,T129	Yes	T128,T119,T129	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T60,T412	Yes	T82,T60,T412	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T85,T190	Yes	T82,T190,T213	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T190,T213	Yes	T82,T85,T190	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T82,T203,T410	Yes	T82,T203,T410	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T203,T85	Yes	T82,T203,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T203,T85	Yes	T82,T203,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T60,T412	Yes	T82,T60,T412	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T82,T203,T410	Yes	T82,T203,T410	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T300,T348,T191	Yes	T300,T348,T191	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	OUTPUT

*Tests covering at least one bit in the range