Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	87.50			87.50
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	91.67			91.67
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67			91.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67			91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.28	99.64	66.67	90.11		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	98.99	85.52	97.84		81.19	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	INPUT
alert_req_i	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	INPUT
alert_ack_o	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	OUTPUT
alert_state_o	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T104,T106,T107	Yes	T104,T106,T107	INPUT
alert_rx_i.ping_p	Yes	Yes	T104,T106,T107	Yes	T104,T106,T107	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	21	87.50
Total Bits 0->1	12	11	91.67
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	21	87.50
Port Bits 0->1	12	11	91.67
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
alert_req_i	Yes	Yes	T385	Yes	T385	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		Yes	T385	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	INPUT
alert_rx_i.ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_rx_i.ping_p	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	22	91.67
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	22	91.67
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
alert_req_i	No	No		Yes	T242,T243	INPUT
alert_ack_o	Yes	Yes	T242,T243	Yes	T242,T243	OUTPUT
alert_state_o	No	No		Yes	T242,T243	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	INPUT
alert_rx_i.ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_rx_i.ping_p	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
alert_req_i	Yes	Yes	T105,T110,T113	Yes	T105,T109,T110	INPUT
alert_ack_o	Yes	Yes	T105,T109,T110	Yes	T105,T109,T110	OUTPUT
alert_state_o	Yes	Yes	T105,T110,T113	Yes	T105,T109,T110	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T94,T104,T105	Yes	T94,T104,T105	INPUT
alert_rx_i.ping_n	Yes	Yes	T104,T106,T107	Yes	T104,T106,T107	INPUT
alert_rx_i.ping_p	Yes	Yes	T104,T106,T107	Yes	T104,T106,T107	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T94,T104,T105	Yes	T94,T104,T105	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
alert_req_i	Yes	Yes	T374,T375,T376	Yes	T374,T375,T376	INPUT
alert_ack_o	Yes	Yes	T374,T375,T376	Yes	T374,T375,T376	OUTPUT
alert_state_o	Yes	Yes	T374,T375,T376	Yes	T374,T375,T376	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	INPUT
alert_rx_i.ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T241	INPUT
alert_rx_i.ping_p	Yes	Yes	T106,T107,T241	Yes	T106,T107,T175	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T94,T106,T95	Yes	T94,T106,T95	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	INPUT
alert_req_i	Yes	Yes	T46	Yes	T46	INPUT
alert_ack_o	Yes	Yes	T46	Yes	T46	OUTPUT
alert_state_o	Yes	Yes	T46	Yes	T46	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_rx_i.ping_p	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T31,T46,T94	Yes	T31,T46,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
alert_req_i	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	INPUT
alert_ack_o	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	OUTPUT
alert_state_o	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	INPUT
alert_rx_i.ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T241	INPUT
alert_rx_i.ping_p	Yes	Yes	T106,T107,T241	Yes	T106,T107,T175	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T133,T265,T70	Yes	T133,T265,T70	OUTPUT