Module Definition
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Module : rv_plic
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.28 99.64 66.67 90.11 100.00 90.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic 89.28 99.64 66.67 90.11 100.00 90.00



Module Instance : tb.dut.top_earlgrey.u_rv_plic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.28 99.64 66.67 90.11 100.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.52 91.98 81.52 90.16 92.52 96.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 91.67 91.67
gen_target[0].u_target 91.51 88.57 77.45 100.00 100.00
u_gateway 75.00 100.00 25.00 100.00
u_prim_flop_2sync 100.00 100.00 100.00
u_reg 91.49 91.96 84.15 89.83 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_plic
Line No.TotalCoveredPercent
TOTAL56356199.64
CONT_ASSIGN7411100.00
ALWAYS7744100.00
ALWAYS8344100.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1
77 1 1
78 1 1
79 2 2
MISSING_ELSE
83 1 1
84 1 1
85 2 2
MISSING_ELSE
99 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
112 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
209 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
265 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
271 1 1
272 1 1
273 1 1
274 1 1
275 1 1
276 1 1
277 1 1
278 1 1
279 1 1
280 1 1
286 182 182
292 0 1
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
306 1 1
313 181 182
375 1 1


Cond Coverage for Module : rv_plic
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       375
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT94,T95,T96

Toggle Coverage for Module : rv_plic
TotalCoveredPercent
Totals 33 23 69.70
Total Bits 708 638 90.11
Total Bits 0->1 354 319 90.11
Total Bits 1->0 354 319 90.11

Ports 33 23 69.70
Port Bits 708 638 90.11
Port Bits 0->1 354 319 90.11
Port Bits 1->0 354 319 90.11

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[9:2] Yes Yes *T2,T3,T99 Yes T2,T3,T99 INPUT
tl_i.a_address[11:10] No No No INPUT
tl_i.a_address[14:12] Yes Yes *T251,*T252,*T253 Yes T251,T252,T253 INPUT
tl_i.a_address[20:15] No No No INPUT
tl_i.a_address[21] Yes Yes *T2,*T3,*T99 Yes T2,T3,T99 INPUT
tl_i.a_address[25:22] No No No INPUT
tl_i.a_address[27:26] Yes Yes T1,*T94,*T95 Yes T1,T94,T95 INPUT
tl_i.a_address[29:28] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T99 Yes T1,T3,T99 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T3,T99 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T3,T99 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T2,*T3,*T99 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T2,T3,T99 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_src_i[0] Unreachable Unreachable Unreachable INPUT
intr_src_i[181:1] Yes Yes T244,T125,T151 Yes T244,T125,T151 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T94,T106,T95 Yes T94,T106,T95 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T94,T106,T95 Yes T94,T106,T95 OUTPUT
irq_o Yes Yes T2,T3,T99 Yes T2,T3,T99 OUTPUT
irq_id_o[0][0] Yes Yes T2,T3,T99 Yes T2,T3,T99 OUTPUT
irq_id_o[0][1] Yes Yes T99,T244,T143 Yes T99,T244,T143 OUTPUT
irq_id_o[0][2] Yes Yes T2,T3,T65 Yes T2,T3,T65 OUTPUT
irq_id_o[0][3] Yes Yes T3,T99,T133 Yes T3,T99,T133 OUTPUT
irq_id_o[0][4] Yes Yes T2,T3,T99 Yes T2,T3,T99 OUTPUT
irq_id_o[0][5] Yes Yes T3,T99,T108 Yes T3,T99,T108 OUTPUT
irq_id_o[0][6] Yes Yes T3,T99,T108 Yes T3,T99,T108 OUTPUT
irq_id_o[0][7] Yes Yes T2,T65,T66 Yes T2,T65,T66 OUTPUT
msip_o Yes Yes T1,T254,T255 Yes T1,T254,T255 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_plic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 79 2 2 100.00
IF 85 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 79 if (claim_re[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T99
0 Covered T2,T3,T99


LineNo. Expression -1-: 85 if (complete_we[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T99
0 Covered T1,T2,T3


Assert Coverage for Module : rv_plic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 9 90.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 9 90.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmBusIntegrity_A 406578375 0 0 0
FpvSecCmRegWeOnehotCheck_A 406578375 2 0 0
Irq0Tied_A 406578375 406480042 0 0
IrqKnownO_A 406578375 406480042 0 0
MsipKnownO_A 406578375 406480042 0 0
TlAReadyKnownO_A 406578375 406480042 0 0
TlDValidKnownO_A 406578375 406480042 0 0
gen_irq_id_known[0].IrqIdKnownO_A 406578375 406480042 0 0
onehot0Claim 406578375 406480042 0 0
onehot0Complete 406578375 406480042 0 0


FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 2 0 0
T92 231241 0 0 0
T123 126347 0 0 0
T183 693141 0 0 0
T229 415064 0 0 0
T242 160190 1 0 0
T243 0 1 0 0
T319 179500 0 0 0
T329 71650 0 0 0
T330 228913 0 0 0
T331 130875 0 0 0
T332 151899 0 0 0

Irq0Tied_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

IrqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

MsipKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

gen_irq_id_known[0].IrqIdKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

onehot0Claim
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

onehot0Complete
NameAttemptsReal SuccessesFailuresIncomplete
Total 406578375 406480042 0 0
T1 132079 132017 0 0
T2 288539 288383 0 0
T3 227982 227869 0 0
T31 244799 244675 0 0
T63 464900 464784 0 0
T65 154347 154289 0 0
T66 143790 143732 0 0
T67 343540 343485 0 0
T99 271503 271379 0 0
T108 210552 210490 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%