dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.11 98.99 85.52 97.84 81.19 92.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.00 92.03 80.49 97.86 95.33 99.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_wkup_detect[0].u_pinmux_wkup 69.87 77.78 68.18 63.64
gen_wkup_detect[1].u_pinmux_wkup 60.10 66.67 45.45 68.18
gen_wkup_detect[2].u_pinmux_wkup 76.26 83.33 72.73 72.73
gen_wkup_detect[3].u_pinmux_wkup 45.45 50.00 31.82 54.55
gen_wkup_detect[4].u_pinmux_wkup 45.45 50.00 31.82 54.55
gen_wkup_detect[5].u_pinmux_wkup 77.78 83.33 77.27 72.73
gen_wkup_detect[6].u_pinmux_wkup 60.10 66.67 45.45 68.18
gen_wkup_detect[7].u_pinmux_wkup 45.45 50.00 31.82 54.55
u_pinmux_strap_sampling 98.49 99.62 95.65 98.70 100.00
u_reg 92.62 91.79 79.96 98.74 100.00
u_usbdev_aon_wake 98.43 100.00 95.59 98.11 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon
Line No.TotalCoveredPercent
TOTAL89588698.99
CONT_ASSIGN13311100.00
ALWAYS1624141100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN244100.00
CONT_ASSIGN244100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24500
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24600
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24700
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24800
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN251100.00
CONT_ASSIGN251100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26700
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26800
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN26900
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27000
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN31200
CONT_ASSIGN31311100.00
CONT_ASSIGN41211100.00
ALWAYS4151515100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN48811100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN574100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN574100.00
CONT_ASSIGN574100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN574100.00
CONT_ASSIGN574100.00
CONT_ASSIGN57811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
133 1 1
162 1 1
163 1 1
164 1 1
167 1 1
168 1 1
169 1 1
MISSING_ELSE
171 1 1
172 1 1
MISSING_ELSE
174 1 1
175 1 1
MISSING_ELSE
177 1 1
178 1 1
MISSING_ELSE
180 1 1
181 1 1
MISSING_ELSE
183 1 1
184 1 1
MISSING_ELSE
186 1 1
187 1 1
MISSING_ELSE
189 1 1
190 1 1
MISSING_ELSE
192 1 1
193 1 1
MISSING_ELSE
197 1 1
198 1 1
199 1 1
MISSING_ELSE
201 1 1
202 1 1
MISSING_ELSE
204 1 1
205 1 1
MISSING_ELSE
207 1 1
208 1 1
MISSING_ELSE
210 1 1
211 1 1
MISSING_ELSE
213 1 1
214 1 1
MISSING_ELSE
216 1 1
217 1 1
MISSING_ELSE
219 1 1
220 1 1
MISSING_ELSE
222 1 1
223 1 1
MISSING_ELSE
243 16 16
244 14 16
245 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
246 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
247 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
248 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
249 16 16
250 16 16
251 14 16
252 16 16
265 47 47
266 47 47
267 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
268 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
269 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
270 excluded
Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
271 47 47
272 47 47
273 47 47
274 47 47
312 unreachable
313 1 1
412 1 1
415 1 1
416 1 1
417 1 1
418 1 1
419 1 1
420 1 1
422 1 1
425 1 1
426 1 1
427 1 1
428 1 1
MISSING_ELSE
433 1 1
434 1 1
435 1 1
436 1 1
MISSING_ELSE
452 1 1
456 57 57
466 1 1
467 1 1
471 47 47
475 47 47
484 47 47
488 47 47
493 47 47
495 47 47
503 1 1
507 16 16
511 16 16
520 16 16
524 16 16
529 16 16
531 16 16
543 1 1
548 1 1
553 8 8
574 3 8
578 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon
TotalCoveredPercent
Conditions1975168985.52
Logical1975168985.52
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
133-48491.00
484-48883.33
48881.50
488-52489.65
524-55380.95

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon
TotalCoveredPercent
Totals 400 385 96.25
Total Bits 1940 1898 97.84
Total Bits 0->1 970 950 97.94
Total Bits 1->0 970 948 97.73

Ports 400 385 96.25
Port Bits 1940 1898 97.84
Port Bits 0->1 970 950 97.94
Port Bits 1->0 970 948 97.73

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
rst_sys_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
pin_wkup_req_o Yes Yes T14,T15,T18 Yes T14,T15,T13 OUTPUT
usb_wkup_req_o Yes Yes T18,T50,T51 Yes T18,T19,T50 OUTPUT
sleep_en_i Yes Yes T1,T2,T3 Yes T1,T2,T65 INPUT
strap_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
strap_en_override_i Unreachable Unreachable Unreachable INPUT
lc_dft_en_i[3:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
lc_check_byp_en_i[3:0] Yes Yes T6,T44,T93 Yes T45,T6,T44 INPUT
lc_escalate_en_i[3:0] Yes Yes T3,T31,T99 Yes T3,T31,T99 INPUT
pinmux_hw_debug_en_o[3:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
dft_strap_test_o.straps[1:0] No No Yes T90,T91,T92 OUTPUT
dft_strap_test_o.valid Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
lc_jtag_o.tdi Yes Yes T45,T6,T44 Yes T45,T6,T44 OUTPUT
lc_jtag_o.trst_n Yes Yes T6,T44,T93 Yes T45,T6,T57 OUTPUT
lc_jtag_o.tms Yes Yes T45,T6,T44 Yes T45,T6,T44 OUTPUT
lc_jtag_o.tck Yes Yes T45,T6,T44 Yes T45,T6,T57 OUTPUT
lc_jtag_i.tdo_oe Yes Yes T45,T6,T44 Yes T45,T6,T44 INPUT
lc_jtag_i.tdo Yes Yes T45,T6,T44 Yes T45,T6,T44 INPUT
rv_jtag_o.tdi Yes Yes T31,T54,T46 Yes T31,T54,T46 OUTPUT
rv_jtag_o.trst_n Yes Yes T31,T46,T100 Yes T31,T54,T46 OUTPUT
rv_jtag_o.tms Yes Yes T31,T54,T46 Yes T31,T54,T46 OUTPUT
rv_jtag_o.tck Yes Yes T31,T54,T46 Yes T31,T54,T46 OUTPUT
rv_jtag_i.tdo_oe Yes Yes T31,T54,T46 Yes T31,T54,T46 INPUT
rv_jtag_i.tdo Yes Yes T31,T54,T46 Yes T31,T54,T46 INPUT
dft_jtag_o.tdi Yes Yes T100,T101,T90 Yes T100,T101,T90 OUTPUT
dft_jtag_o.trst_n Yes Yes T100,T101,T90 Yes T100,T101,T90 OUTPUT
dft_jtag_o.tms Yes Yes T100,T101,T90 Yes T100,T101,T90 OUTPUT
dft_jtag_o.tck Yes Yes T100,T101,T90 Yes T100,T101,T90 OUTPUT
dft_jtag_i.tdo_oe Yes Yes T100,T101,T90 Yes T100,T101,T90 INPUT
dft_jtag_i.tdo Yes Yes T100,T101,T90 Yes T100,T101,T90 INPUT
usbdev_dppullup_en_i Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
usbdev_dnpullup_en_i Yes Yes T75,T102,T103 Yes T75,T102,T103 INPUT
usb_dppullup_en_o Yes Yes T17,T18,T51 Yes T17,T18,T19 OUTPUT
usb_dnpullup_en_o Yes Yes T75,T102,T103 Yes T75,T102,T103 OUTPUT
usbdev_suspend_req_i Yes Yes T18,T19,T50 Yes T18,T19,T50 INPUT
usbdev_wake_ack_i Yes Yes T18,T19,T50 Yes T18,T19,T50 INPUT
usbdev_bus_not_idle_o Yes Yes T18,T50,T51 Yes T18,T50,T51 OUTPUT
usbdev_bus_reset_o Yes Yes T102 Yes T102 OUTPUT
usbdev_sense_lost_o Yes Yes T18,T50,T51 Yes T18,T19,T50 OUTPUT
usbdev_wake_detect_active_o Yes Yes T18,T50,T51 Yes T18,T19,T50 OUTPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[11:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T54,*T46,*T55 Yes T54,T46,T55 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T46,*T55,*T56 Yes T46,T55,T56 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:3] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[5:0] Yes Yes *T46,*T1,*T2 Yes T46,T1,T2 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T94,T104,T105 Yes T94,T104,T105 INPUT
alert_rx_i[0].ping_n Yes Yes T104,T106,T107 Yes T104,T106,T107 INPUT
alert_rx_i[0].ping_p Yes Yes T104,T106,T107 Yes T104,T106,T107 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T94,T104,T105 Yes T94,T104,T105 OUTPUT
periph_to_mio_i[74:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
periph_to_mio_oe_i[74:0] Yes Yes T25,T26,T27 Yes T14,T15,T16 INPUT
mio_to_periph_o[56:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
periph_to_dio_i[11:0] Yes Yes *T17,*T18,*T19 Yes T17,T18,T19 INPUT
periph_to_dio_i[13:12] No No No INPUT
periph_to_dio_i[15:14] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
periph_to_dio_oe_i[15:0] Yes Yes T17,T23,T24 Yes T17,T23,T24 INPUT
dio_to_periph_o[15:0] Yes Yes T17,T23,T24 Yes T17,T23,T24 OUTPUT
mio_attr_o[0].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[0].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[0].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[0].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[1].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[1].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[2].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[2].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[3].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[3].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[4].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[4].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[5].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[5].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[6].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[6].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[7].pull_en Yes Yes T28,T29,T30 Yes T38,T39,T40 OUTPUT
mio_attr_o[7].pull_select Yes Yes T28,T29,T30 Yes T38,T39,T40 OUTPUT
mio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[8].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[8].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[9].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[9].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[10].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
mio_attr_o[10].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
mio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[11].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[11].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[12].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
mio_attr_o[12].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
mio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[13].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[13].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[14].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[14].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[15].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[15].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
mio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[16].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[16].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[16].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[16].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[17].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[17].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[17].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[17].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[18].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[18].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[18].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[18].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[19].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[19].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[19].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[19].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[20].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[20].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[20].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[20].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[21].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[21].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[21].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[21].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[22].pull_en Yes Yes T41,T42,T43 Yes T41,T42,T43 OUTPUT
mio_attr_o[22].pull_select Yes Yes T41,T42,T43 Yes T41,T42,T43 OUTPUT
mio_attr_o[22].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[22].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[23].pull_en Yes Yes T41,T42,T43 Yes T41,T42,T43 OUTPUT
mio_attr_o[23].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[23].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[23].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[24].pull_en Yes Yes T41,T42,T43 Yes T41,T42,T43 OUTPUT
mio_attr_o[24].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[24].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[24].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[25].pull_en Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[25].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[26].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[26].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[26].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[26].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[27].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[27].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[27].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[27].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[28].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[28].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[28].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[28].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[29].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[29].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[29].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[29].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[30].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[30].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[30].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[30].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[31].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[31].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[31].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[31].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[32].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[32].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[32].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[32].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[33].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[33].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[33].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[33].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[34].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[34].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[34].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[34].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[35].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[35].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[35].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[35].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[36].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[36].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[36].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[36].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[37].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[37].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[37].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[37].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[38].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[38].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[38].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[38].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[39].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[39].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[39].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[39].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[40].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[40].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[40].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[40].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[41].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[41].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[41].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[41].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[42].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[42].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[42].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[42].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[43].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[43].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[43].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[43].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[44].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[44].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[44].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[44].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[45].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[45].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[45].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[45].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[46].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[46].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[46].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
mio_attr_o[46].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_out_o[46:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
mio_oe_o[46:0] Yes Yes T25,T26,T27 Yes T14,T15,T16 OUTPUT
mio_in_i[46:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
dio_attr_o[0].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[0].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[0].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T2,*T3,*T31 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[1].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[1].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].drive_strength[0] Yes Yes *T2,*T3,*T31 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[2].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[2].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[3].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[3].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[4].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[4].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[5].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[5].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T10 OUTPUT
dio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[6].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[6].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[7].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[7].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[8].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[8].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[9].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[9].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T28,T29,T30 Yes T35,T36,T37 OUTPUT
dio_attr_o[10].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[10].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T28,T29,T30 Yes T35,T36,T37 OUTPUT
dio_attr_o[11].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[11].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[12].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[12].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].drive_strength[0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[13].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].pull_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[13].pull_select Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].drive_strength[0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[14].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
dio_attr_o[14].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
dio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].invert Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T28,T29,T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[15].pull_en Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
dio_attr_o[15].pull_select Yes Yes T28,T29,T30 Yes T32,T33,T34 OUTPUT
dio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].drive_strength[0] Yes Yes *T28,*T29,*T30 Yes T28,T29,T30 OUTPUT
dio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_out_o[11:0] Yes Yes *T17,*T18,*T19 Yes T17,T18,T19 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T10,T11,T12 Yes T7,T10,T11 OUTPUT
dio_oe_o[15:0] Yes Yes T17,T23,T24 Yes T17,T7,T23 OUTPUT
dio_in_i[15:0] Yes Yes T17,T23,T24 Yes T17,T23,T24 INPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon
Line No.TotalCoveredPercent
Branches 776 630 81.19
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 2 50.00
TERNARY 488 4 2 50.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 4 100.00
TERNARY 488 4 4 100.00
TERNARY 471 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 484 4 3 75.00
TERNARY 488 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 3 75.00
TERNARY 524 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 3 75.00
TERNARY 524 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 4 100.00
TERNARY 524 4 4 100.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 3 75.00
TERNARY 524 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 4 100.00
TERNARY 524 4 4 100.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 3 75.00
TERNARY 524 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 4 100.00
TERNARY 524 4 4 100.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 3 75.00
TERNARY 524 4 3 75.00
TERNARY 507 2 2 100.00
TERNARY 511 2 2 100.00
TERNARY 520 4 2 50.00
TERNARY 524 4 2 50.00
TERNARY 553 2 1 50.00
TERNARY 553 2 1 50.00
TERNARY 553 2 2 100.00
TERNARY 553 2 1 50.00
TERNARY 553 2 1 50.00
TERNARY 553 2 2 100.00
TERNARY 553 2 1 50.00
TERNARY 553 2 1 50.00
IF 162 2 2 100.00
IF 415 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T46
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T46
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T49
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T49
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T8
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T8
0 1 - Covered T14,T15,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T7
0 1 - Covered T14,T15,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T46
0 1 - Covered T14,T15,T49
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T15,T46
0 1 - Covered T14,T15,T49
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T7
0 1 - Covered T14,T15,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T7
0 1 - Covered T14,T15,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T46,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T46,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[16].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[16].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[17].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[17].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[18].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[18].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[19].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[19].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[20].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[20].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[21].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[21].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[22].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[22].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[23].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[23].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[24].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[24].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[25].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[25].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[26].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[26].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[27].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[27].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[28].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[28].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[29].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[29].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[30].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[30].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[31].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[31].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[32].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[32].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[33].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[33].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T46,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[34].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[34].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[35].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[35].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[36].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[36].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[37].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[37].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[38].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[38].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[39].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[39].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[40].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[40].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[41].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[41].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[42].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[42].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[43].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[43].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[44].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[44].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[45].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[45].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 471 (reg2hw.mio_pad_sleep_status[46].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 475 (reg2hw.mio_pad_sleep_status[46].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 484 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? -2-: 484 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? -3-: 484 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 488 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? -2-: 488 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? -3-: 488 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T8,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T8,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T46,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T9
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T46


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T46
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T9
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 507 (reg2hw.dio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 511 (reg2hw.dio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 520 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 520 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 520 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 524 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 524 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 524 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T9
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[0].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[1].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[2].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[3].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[4].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[5].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T46,T97,T98
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[6].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (reg2hw.wkup_detector[7].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 162 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 415 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 23 92.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 23 92.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 101885381 101259447 0 0
AonWkupReqKnownO_A 1336705 1169787 0 0
DftJtagTckKnown_A 101885381 101259447 0 0
DftJtagTmsKnown_A 101885381 101259447 0 0
DftJtagTrstKnown_A 101885381 101259447 0 0
DftStrapsKnown_A 101885381 101259447 0 0
DioKnownO_A 101885381 101259447 0 0
DioOeKnownO_A 101885381 101259447 0 0
FpvSecCmBusIntegrity_A 101885381 0 0 0
FpvSecCmRegWeOnehotCheck_A 101885381 6 0 0
LcJtagTckKnown_A 101885381 101259447 0 0
LcJtagTmsKnown_A 101885381 101259447 0 0
LcJtagTrstKnown_A 101885381 101259447 0 0
MioKnownO_A 101885381 101259447 0 0
MioOeKnownO_A 101885381 101259447 0 0
PinmuxWkupStable_A 1336705 4570 0 0
PwrMgrStrapSampleOnce0_A 101885381 1583 0 0
PwrMgrStrapSampleOnce1_A 101885381 0 0 880
RvJtagTckKnown_A 101885381 101259447 0 0
RvJtagTmsKnown_A 101885381 101259447 0 0
RvJtagTrstKnown_A 101885381 101259447 0 0
TlAReadyKnownO_A 101885381 101259447 0 0
TlDValidKnownO_A 101885381 101259447 0 0
UsbWakeDetectActiveKnownO_A 1336705 1169787 0 0
UsbWkupReqKnownO_A 1336705 1169787 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

AonWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1336705 1169787 0 0
T1 623 460 0 0
T2 1328 1163 0 0
T3 925 762 0 0
T31 894 729 0 0
T63 1601 1437 0 0
T65 618 454 0 0
T66 651 487 0 0
T67 917 755 0 0
T99 900 735 0 0
T108 704 540 0 0

DftJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

DftJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

DftJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

DftStrapsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

DioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

DioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 6 0 0
T105 68961 1 0 0
T109 0 1 0 0
T110 0 1 0 0
T111 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 45110 0 0 0
T115 51702 0 0 0
T116 23354 0 0 0
T117 16106 0 0 0
T118 84282 0 0 0
T119 53526 0 0 0
T120 42410 0 0 0
T121 41136 0 0 0
T122 77525 0 0 0

LcJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

LcJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

LcJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

MioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

MioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

PinmuxWkupStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1336705 4570 0 0
T13 0 387 0 0
T14 630 86 0 0
T15 0 136 0 0
T18 0 507 0 0
T45 262 0 0 0
T49 0 21 0 0
T50 0 26 0 0
T51 0 509 0 0
T52 0 427 0 0
T53 0 537 0 0
T68 413 0 0 0
T123 0 24 0 0
T124 809 0 0 0
T125 652 0 0 0
T126 388 0 0 0
T127 895 0 0 0
T128 553 0 0 0
T129 412 0 0 0
T130 349 0 0 0

PwrMgrStrapSampleOnce0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 1583 0 0
T1 56164 1 0 0
T2 73341 2 0 0
T3 55924 2 0 0
T31 59930 2 0 0
T63 113297 1 0 0
T65 41866 1 0 0
T66 39343 1 0 0
T67 92952 1 0 0
T99 66488 2 0 0
T108 51276 1 0 0

PwrMgrStrapSampleOnce1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 0 0 880

RvJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

RvJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

RvJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101885381 101259447 0 0
T1 56164 55371 0 0
T2 73341 72904 0 0
T3 55924 55455 0 0
T31 59930 59489 0 0
T63 113297 112869 0 0
T65 41866 41412 0 0
T66 39343 39000 0 0
T67 92952 91919 0 0
T99 66488 65900 0 0
T108 51276 50902 0 0

UsbWakeDetectActiveKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1336705 1169787 0 0
T1 623 460 0 0
T2 1328 1163 0 0
T3 925 762 0 0
T31 894 729 0 0
T63 1601 1437 0 0
T65 618 454 0 0
T66 651 487 0 0
T67 917 755 0 0
T99 900 735 0 0
T108 704 540 0 0

UsbWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1336705 1169787 0 0
T1 623 460 0 0
T2 1328 1163 0 0
T3 925 762 0 0
T31 894 729 0 0
T63 1601 1437 0 0
T65 618 454 0 0
T66 651 487 0 0
T67 917 755 0 0
T99 900 735 0 0
T108 704 540 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%