Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.66 99.11 88.35 98.76 85.05 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.30 99.82 66.67 100.00 100.00 90.00 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T177,T61,T229 Yes T177,T61,T229 INPUT
alert_req_i Yes Yes T166,T117,T225 Yes T230,T166,T117 INPUT
alert_ack_o Yes Yes T230,T166,T117 Yes T230,T166,T117 OUTPUT
alert_state_o Yes Yes T166,T117,T225 Yes T230,T166,T117 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T64,T280,T177 Yes T64,T280,T177 INPUT
alert_rx_i.ping_n Yes Yes T64,T82,T61 Yes T64,T82,T85 INPUT
alert_rx_i.ping_p Yes Yes T64,T82,T85 Yes T64,T82,T61 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T64,T280,T177 Yes T64,T280,T177 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 12 9 75.00
Total Bits 24 18 75.00
Total Bits 0->1 12 9 75.00
Total Bits 1->0 12 9 75.00

Ports 12 9 75.00
Port Bits 24 18 75.00
Port Bits 0->1 12 9 75.00
Port Bits 1->0 12 9 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T61,T49,T62 Yes T61,T49,T62 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T82,T61,T49 Yes T82,T61,T49 INPUT
alert_rx_i.ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i.ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T82,T61,T49 Yes T82,T61,T49 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T30,T31,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_req_i Yes Yes T83,T84,T92 Yes T83,T84,T91 INPUT
alert_ack_o Yes Yes T83,T84,T91 Yes T83,T84,T91 OUTPUT
alert_state_o Yes Yes T83,T84,T92 Yes T83,T84,T91 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_rx_i.ping_n Yes Yes T82,T85,T86 Yes T82,T85,T87 INPUT
alert_rx_i.ping_p Yes Yes T82,T85,T87 Yes T82,T85,T86 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T82,T83,T84 Yes T82,T83,T84 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_req_i Yes Yes T280 Yes T280,T282 INPUT
alert_ack_o Yes Yes T280,T282 Yes T280,T282 OUTPUT
alert_state_o Yes Yes T280 Yes T280,T282 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T64,T280,T82 Yes T64,T280,T82 INPUT
alert_rx_i.ping_n Yes Yes T64,T82,T61 Yes T64,T82,T85 INPUT
alert_rx_i.ping_p Yes Yes T64,T82,T85 Yes T64,T82,T61 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T64,T280,T82 Yes T64,T280,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T61,T62,T52 Yes T61,T62,T52 INPUT
alert_req_i Yes Yes T242,T664,T665 Yes T242,T664,T665 INPUT
alert_ack_o Yes Yes T242,T664,T665 Yes T242,T664,T665 OUTPUT
alert_state_o Yes Yes T242,T664,T665 Yes T242,T664,T665 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T64,T82,T242 Yes T64,T82,T242 INPUT
alert_rx_i.ping_n Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_rx_i.ping_p Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T64,T82,T242 Yes T64,T82,T242 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T177,T61,T229 Yes T177,T61,T229 INPUT
alert_req_i Yes Yes T49,T52 Yes T49,T52 INPUT
alert_ack_o Yes Yes T49,T52 Yes T49,T52 OUTPUT
alert_state_o Yes Yes T49,T52 Yes T49,T52 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T177,T82,T61 Yes T177,T82,T61 INPUT
alert_rx_i.ping_n Yes Yes T82,T185,T85 Yes T82,T85,T87 INPUT
alert_rx_i.ping_p Yes Yes T82,T85,T87 Yes T82,T185,T85 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T177,T82,T61 Yes T177,T82,T61 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T61,T62,T52 Yes T61,T62,T52 INPUT
alert_req_i Yes Yes T166,T117,T225 Yes T230,T166,T117 INPUT
alert_ack_o Yes Yes T230,T166,T117 Yes T230,T166,T117 OUTPUT
alert_state_o Yes Yes T166,T117,T225 Yes T230,T166,T117 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T230,T166,T117 Yes T230,T166,T117 INPUT
alert_rx_i.ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i.ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T230,T166,T117 Yes T230,T166,T117 OUTPUT

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