Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.33 72.73 55.56 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.27 82.35 55.56 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.52 52.63 38.46 45.45 gen_wkup_detect[2].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.33 72.73 55.56 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.27 82.35 55.56 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.52 52.63 38.46 45.45 gen_wkup_detect[7].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.07 68.42 69.23 54.55 gen_wkup_detect[3].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
56.72 63.16 61.54 45.45 gen_wkup_detect[6].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.40 57.89 53.85 45.45 gen_wkup_detect[0].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.07 68.42 69.23 54.55 gen_wkup_detect[1].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
61.50 68.42 61.54 54.55 gen_wkup_detect[4].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.07 68.42 69.23 54.55 gen_wkup_detect[5].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Module : prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11872.73
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 2 100.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T49
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11872.73
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 2 100.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T49
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT49,T57,T52
01CoveredT49,T57,T52
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT49,T57,T52
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T57,T52

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T49,T57,T52


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT52
01CoveredT52
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT52
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT52

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T52


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T17,T88
01CoveredT16,T17,T88
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT16,T17,T88
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T17,T88

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T16,T17,T88


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT49,T53,T54
01CoveredT49,T53,T55
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT49,T53,T54
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T53,T55

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T49
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T49,T53,T54


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT47,T49
01CoveredT47,T49
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT47,T49
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT47,T49

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT52

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T52
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T47,T49


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT56
01CoveredT56
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT56
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT56

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T49
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T56


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT18,T48,T58
01CoveredT18,T48,T58
10CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT18,T48,T58
1CoveredT1,T2,T3

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T48,T58

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T52

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T49,T52
0 Covered T1,T2,T3


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T18,T48,T58


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%