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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.49 94.26 95.69 94.98 97.38 99.55


Total test records in report: 2783
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T403 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2656225978 Apr 30 04:24:51 PM PDT 24 Apr 30 04:34:19 PM PDT 24 3794771280 ps
T404 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2221470506 Apr 30 04:42:41 PM PDT 24 Apr 30 04:54:25 PM PDT 24 5938462556 ps
T346 /workspace/coverage/default/27.chip_sw_all_escalation_resets.59167594 Apr 30 04:48:15 PM PDT 24 Apr 30 04:55:42 PM PDT 24 4529188628 ps
T405 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.692148787 Apr 30 04:31:34 PM PDT 24 Apr 30 04:38:23 PM PDT 24 2977345656 ps
T861 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3570744991 Apr 30 04:34:04 PM PDT 24 Apr 30 04:38:30 PM PDT 24 2699715970 ps
T167 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.278482112 Apr 30 04:22:39 PM PDT 24 Apr 30 04:25:22 PM PDT 24 3137209834 ps
T862 /workspace/coverage/default/1.chip_sw_aes_smoketest.3075187404 Apr 30 04:33:40 PM PDT 24 Apr 30 04:38:03 PM PDT 24 3290940778 ps
T82 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.988627985 Apr 30 04:31:28 PM PDT 24 Apr 30 04:38:24 PM PDT 24 3250637378 ps
T334 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1534932385 Apr 30 04:25:29 PM PDT 24 Apr 30 04:34:12 PM PDT 24 18012725534 ps
T327 /workspace/coverage/default/1.chip_sw_hmac_enc.2924617373 Apr 30 04:33:04 PM PDT 24 Apr 30 04:37:17 PM PDT 24 2777989184 ps
T863 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3094219771 Apr 30 04:31:37 PM PDT 24 Apr 30 04:36:51 PM PDT 24 3263944638 ps
T864 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.973830809 Apr 30 04:22:30 PM PDT 24 Apr 30 04:39:25 PM PDT 24 5641351994 ps
T162 /workspace/coverage/default/75.chip_sw_all_escalation_resets.627957818 Apr 30 04:52:00 PM PDT 24 Apr 30 04:59:07 PM PDT 24 4566734360 ps
T328 /workspace/coverage/default/2.chip_sw_hmac_enc.3460021212 Apr 30 04:41:20 PM PDT 24 Apr 30 04:47:16 PM PDT 24 3538911670 ps
T712 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3499542565 Apr 30 04:51:49 PM PDT 24 Apr 30 04:59:32 PM PDT 24 4266227134 ps
T865 /workspace/coverage/default/1.chip_sw_kmac_idle.2589438494 Apr 30 04:30:48 PM PDT 24 Apr 30 04:34:44 PM PDT 24 2667425198 ps
T866 /workspace/coverage/default/1.chip_sw_edn_kat.1497421965 Apr 30 04:31:46 PM PDT 24 Apr 30 04:42:08 PM PDT 24 3064784174 ps
T168 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.86389011 Apr 30 04:36:41 PM PDT 24 Apr 30 04:39:03 PM PDT 24 3046673637 ps
T48 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.593497840 Apr 30 04:41:58 PM PDT 24 Apr 30 04:48:52 PM PDT 24 3387684800 ps
T867 /workspace/coverage/default/0.chip_sw_kmac_app_rom.27353299 Apr 30 04:25:44 PM PDT 24 Apr 30 04:29:08 PM PDT 24 2746170160 ps
T204 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.244378740 Apr 30 04:36:30 PM PDT 24 Apr 30 08:18:32 PM PDT 24 77024424770 ps
T868 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2379778881 Apr 30 04:31:54 PM PDT 24 Apr 30 04:36:22 PM PDT 24 2856752764 ps
T658 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982822737 Apr 30 04:46:23 PM PDT 24 Apr 30 04:52:38 PM PDT 24 3101011464 ps
T869 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3867797868 Apr 30 04:26:06 PM PDT 24 Apr 30 04:39:33 PM PDT 24 8025358758 ps
T870 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2923084973 Apr 30 04:48:23 PM PDT 24 Apr 30 04:58:30 PM PDT 24 4788999960 ps
T871 /workspace/coverage/default/3.chip_sw_uart_tx_rx.55423747 Apr 30 04:45:42 PM PDT 24 Apr 30 04:54:41 PM PDT 24 4234195560 ps
T656 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1033197335 Apr 30 04:49:46 PM PDT 24 Apr 30 04:55:47 PM PDT 24 3589739808 ps
T872 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3719049965 Apr 30 04:44:42 PM PDT 24 Apr 30 05:14:52 PM PDT 24 9997308678 ps
T261 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2288093616 Apr 30 04:31:22 PM PDT 24 Apr 30 04:36:13 PM PDT 24 3341495180 ps
T873 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2588467097 Apr 30 04:25:10 PM PDT 24 Apr 30 04:31:52 PM PDT 24 4376269688 ps
T672 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2276504652 Apr 30 04:47:27 PM PDT 24 Apr 30 04:57:47 PM PDT 24 5587244800 ps
T874 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.471904045 Apr 30 04:36:52 PM PDT 24 Apr 30 04:42:37 PM PDT 24 2772236360 ps
T425 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3919843981 Apr 30 04:24:19 PM PDT 24 Apr 30 04:38:27 PM PDT 24 4150163336 ps
T875 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.493140996 Apr 30 04:31:25 PM PDT 24 Apr 30 05:29:39 PM PDT 24 18572780436 ps
T178 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.864912087 Apr 30 04:24:21 PM PDT 24 Apr 30 05:39:32 PM PDT 24 44566871268 ps
T657 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3006392472 Apr 30 04:48:28 PM PDT 24 Apr 30 04:55:53 PM PDT 24 5143543198 ps
T363 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.143388764 Apr 30 04:29:44 PM PDT 24 Apr 30 05:25:09 PM PDT 24 13795313680 ps
T218 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1093005792 Apr 30 04:24:16 PM PDT 24 Apr 30 04:53:36 PM PDT 24 8670318472 ps
T876 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3682953428 Apr 30 04:39:29 PM PDT 24 Apr 30 04:46:22 PM PDT 24 3478393262 ps
T877 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3333436639 Apr 30 04:27:22 PM PDT 24 Apr 30 04:31:41 PM PDT 24 2414969398 ps
T878 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1898419099 Apr 30 04:30:08 PM PDT 24 Apr 30 04:35:10 PM PDT 24 2511273976 ps
T189 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1153421395 Apr 30 04:47:11 PM PDT 24 Apr 30 04:56:47 PM PDT 24 4350958392 ps
T732 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1474868596 Apr 30 04:47:30 PM PDT 24 Apr 30 04:56:41 PM PDT 24 5806752944 ps
T185 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2975549357 Apr 30 04:32:28 PM PDT 24 Apr 30 04:37:11 PM PDT 24 3122862360 ps
T879 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.654862979 Apr 30 04:27:01 PM PDT 24 Apr 30 04:31:01 PM PDT 24 3067365084 ps
T54 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.39416916 Apr 30 04:21:41 PM PDT 24 Apr 30 04:26:25 PM PDT 24 2806187992 ps
T880 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1170323334 Apr 30 04:31:54 PM PDT 24 Apr 30 04:39:27 PM PDT 24 4081995261 ps
T711 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078797994 Apr 30 04:47:10 PM PDT 24 Apr 30 04:52:47 PM PDT 24 3143018546 ps
T666 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.830691114 Apr 30 04:48:09 PM PDT 24 Apr 30 04:57:04 PM PDT 24 4002946270 ps
T364 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1028557305 Apr 30 04:40:19 PM PDT 24 Apr 30 04:55:11 PM PDT 24 4533111872 ps
T174 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2697678654 Apr 30 04:32:14 PM PDT 24 Apr 30 04:37:02 PM PDT 24 3009310646 ps
T120 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3991285651 Apr 30 04:41:52 PM PDT 24 Apr 30 05:06:30 PM PDT 24 8171338107 ps
T289 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4256036776 Apr 30 04:25:43 PM PDT 24 Apr 30 04:56:13 PM PDT 24 13526578374 ps
T290 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1105255084 Apr 30 04:24:13 PM PDT 24 Apr 30 04:37:33 PM PDT 24 7130497462 ps
T291 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.579983012 Apr 30 04:41:31 PM PDT 24 Apr 30 05:01:09 PM PDT 24 10717235376 ps
T211 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1179228843 Apr 30 04:39:56 PM PDT 24 Apr 30 05:21:39 PM PDT 24 20435709231 ps
T292 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2110380516 Apr 30 04:23:39 PM PDT 24 Apr 30 04:42:13 PM PDT 24 5925322024 ps
T172 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1848871866 Apr 30 04:42:45 PM PDT 24 Apr 30 04:55:33 PM PDT 24 7841959520 ps
T191 /workspace/coverage/default/2.chip_sw_power_idle_load.1331404295 Apr 30 04:45:10 PM PDT 24 Apr 30 04:54:43 PM PDT 24 3600941070 ps
T293 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3113417215 Apr 30 04:31:23 PM PDT 24 Apr 30 04:36:10 PM PDT 24 2554809300 ps
T881 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2665935080 Apr 30 04:44:59 PM PDT 24 Apr 30 05:09:31 PM PDT 24 8283178956 ps
T882 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3123819331 Apr 30 04:44:45 PM PDT 24 Apr 30 04:49:13 PM PDT 24 3668102551 ps
T883 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2986191893 Apr 30 04:31:31 PM PDT 24 Apr 30 04:43:12 PM PDT 24 4753498250 ps
T192 /workspace/coverage/default/1.chip_sw_power_idle_load.2368368675 Apr 30 04:32:48 PM PDT 24 Apr 30 04:44:07 PM PDT 24 4525009500 ps
T240 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.168187811 Apr 30 04:51:49 PM PDT 24 Apr 30 04:59:15 PM PDT 24 4014623352 ps
T884 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3362831922 Apr 30 04:25:28 PM PDT 24 Apr 30 04:30:57 PM PDT 24 2682677525 ps
T47 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3655552937 Apr 30 04:32:32 PM PDT 24 Apr 30 04:59:35 PM PDT 24 19627594496 ps
T885 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2357957931 Apr 30 04:38:31 PM PDT 24 Apr 30 04:43:01 PM PDT 24 2883343818 ps
T886 /workspace/coverage/default/0.chip_sw_aes_idle.3872773128 Apr 30 04:27:03 PM PDT 24 Apr 30 04:32:20 PM PDT 24 3398570492 ps
T887 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3944661163 Apr 30 04:22:53 PM PDT 24 Apr 30 04:42:58 PM PDT 24 5882564819 ps
T368 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.565149278 Apr 30 04:28:56 PM PDT 24 Apr 30 04:38:17 PM PDT 24 6071567476 ps
T888 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3212084842 Apr 30 04:44:25 PM PDT 24 Apr 30 04:53:55 PM PDT 24 6041498862 ps
T889 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3757304855 Apr 30 04:29:02 PM PDT 24 Apr 30 04:37:45 PM PDT 24 4035119720 ps
T890 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.487788201 Apr 30 04:46:58 PM PDT 24 Apr 30 05:10:44 PM PDT 24 12884447219 ps
T891 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.41757091 Apr 30 04:22:04 PM PDT 24 Apr 30 04:33:10 PM PDT 24 3753220300 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.3239402527 Apr 30 04:38:40 PM PDT 24 Apr 30 04:45:07 PM PDT 24 3437796607 ps
T322 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.940134000 Apr 30 04:33:36 PM PDT 24 Apr 30 04:47:27 PM PDT 24 4933131602 ps
T892 /workspace/coverage/default/1.chip_sw_aes_enc.2060247757 Apr 30 04:31:39 PM PDT 24 Apr 30 04:37:38 PM PDT 24 3167401330 ps
T648 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.622068632 Apr 30 04:50:03 PM PDT 24 Apr 30 04:54:35 PM PDT 24 3002439072 ps
T34 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3467214504 Apr 30 04:36:27 PM PDT 24 Apr 30 04:39:34 PM PDT 24 2903226000 ps
T893 /workspace/coverage/default/1.chip_sw_otbn_randomness.2128459509 Apr 30 04:31:12 PM PDT 24 Apr 30 04:44:07 PM PDT 24 6313410390 ps
T894 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2237528433 Apr 30 04:30:10 PM PDT 24 Apr 30 04:34:56 PM PDT 24 2452988036 ps
T653 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446455982 Apr 30 04:52:22 PM PDT 24 Apr 30 04:58:09 PM PDT 24 3740562496 ps
T895 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2432237367 Apr 30 04:45:31 PM PDT 24 Apr 30 04:52:54 PM PDT 24 4526001891 ps
T227 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.736162557 Apr 30 04:22:12 PM PDT 24 Apr 30 05:49:50 PM PDT 24 50697134514 ps
T68 /workspace/coverage/default/0.chip_sw_usbdev_pullup.4014230482 Apr 30 04:22:44 PM PDT 24 Apr 30 04:28:07 PM PDT 24 3146526616 ps
T83 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3707474364 Apr 30 04:32:33 PM PDT 24 Apr 30 04:58:04 PM PDT 24 12463859034 ps
T230 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4237832391 Apr 30 04:30:43 PM PDT 24 Apr 30 04:37:46 PM PDT 24 4848762518 ps
T643 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3507073623 Apr 30 04:38:30 PM PDT 24 Apr 30 04:49:13 PM PDT 24 4473436624 ps
T190 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.771998944 Apr 30 04:44:39 PM PDT 24 Apr 30 04:53:13 PM PDT 24 3558680080 ps
T896 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2825637846 Apr 30 04:40:40 PM PDT 24 Apr 30 04:44:48 PM PDT 24 2129391432 ps
T897 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4288804641 Apr 30 04:44:31 PM PDT 24 Apr 30 04:51:38 PM PDT 24 4922493900 ps
T898 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2834729256 Apr 30 04:32:08 PM PDT 24 Apr 30 04:43:28 PM PDT 24 4893779908 ps
T743 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.490251910 Apr 30 04:50:58 PM PDT 24 Apr 30 04:56:51 PM PDT 24 4132185734 ps
T899 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1563153683 Apr 30 04:43:17 PM PDT 24 Apr 30 04:49:49 PM PDT 24 4099823196 ps
T900 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.814934566 Apr 30 04:30:02 PM PDT 24 Apr 30 04:50:44 PM PDT 24 7277658072 ps
T901 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2130351612 Apr 30 04:47:46 PM PDT 24 Apr 30 04:51:56 PM PDT 24 3193736503 ps
T902 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3575152798 Apr 30 04:43:00 PM PDT 24 Apr 30 04:52:22 PM PDT 24 5647480680 ps
T903 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3164584754 Apr 30 04:25:26 PM PDT 24 Apr 30 04:33:12 PM PDT 24 4797451288 ps
T217 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3130329389 Apr 30 04:43:53 PM PDT 24 Apr 30 04:52:15 PM PDT 24 4697303378 ps
T694 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218953928 Apr 30 04:54:34 PM PDT 24 Apr 30 05:00:39 PM PDT 24 3276042200 ps
T677 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4101058152 Apr 30 04:49:52 PM PDT 24 Apr 30 04:55:19 PM PDT 24 3810645722 ps
T904 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3532884969 Apr 30 04:34:50 PM PDT 24 Apr 30 04:39:37 PM PDT 24 3346007923 ps
T219 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2083215054 Apr 30 04:40:41 PM PDT 24 Apr 30 05:08:22 PM PDT 24 8667290288 ps
T905 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3779962199 Apr 30 04:31:27 PM PDT 24 Apr 30 04:55:01 PM PDT 24 7374232540 ps
T329 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3791904554 Apr 30 04:31:33 PM PDT 24 Apr 30 04:45:02 PM PDT 24 4772253380 ps
T906 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.942465717 Apr 30 04:31:42 PM PDT 24 Apr 30 04:45:50 PM PDT 24 8496687986 ps
T244 /workspace/coverage/default/1.chip_sw_power_sleep_load.1197911359 Apr 30 04:33:36 PM PDT 24 Apr 30 04:40:12 PM PDT 24 5083099708 ps
T907 /workspace/coverage/default/2.chip_sw_aes_entropy.169393532 Apr 30 04:40:36 PM PDT 24 Apr 30 04:45:17 PM PDT 24 3199834828 ps
T194 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4094861507 Apr 30 04:36:52 PM PDT 24 Apr 30 04:44:11 PM PDT 24 5029754750 ps
T87 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626947007 Apr 30 04:52:29 PM PDT 24 Apr 30 04:58:29 PM PDT 24 3799997328 ps
T908 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2232165539 Apr 30 04:35:32 PM PDT 24 Apr 30 05:07:37 PM PDT 24 27507244838 ps
T909 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1257178663 Apr 30 04:33:40 PM PDT 24 Apr 30 04:50:30 PM PDT 24 7462144328 ps
T426 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.15684265 Apr 30 04:41:10 PM PDT 24 Apr 30 04:57:35 PM PDT 24 5619183767 ps
T718 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.285092458 Apr 30 04:53:45 PM PDT 24 Apr 30 05:00:33 PM PDT 24 4122065148 ps
T910 /workspace/coverage/default/1.chip_sw_aes_idle.1448841190 Apr 30 04:33:21 PM PDT 24 Apr 30 04:37:31 PM PDT 24 3441289330 ps
T611 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4176672763 Apr 30 04:33:19 PM PDT 24 Apr 30 04:40:58 PM PDT 24 4774139941 ps
T707 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745348577 Apr 30 04:53:28 PM PDT 24 Apr 30 04:59:04 PM PDT 24 3767571300 ps
T695 /workspace/coverage/default/89.chip_sw_all_escalation_resets.427710900 Apr 30 04:52:05 PM PDT 24 Apr 30 04:58:50 PM PDT 24 6014590424 ps
T671 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.9466608 Apr 30 04:49:34 PM PDT 24 Apr 30 04:56:15 PM PDT 24 3459251992 ps
T911 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.569519043 Apr 30 04:22:26 PM PDT 24 Apr 30 04:30:49 PM PDT 24 5097198050 ps
T912 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3690164479 Apr 30 04:51:03 PM PDT 24 Apr 30 05:24:00 PM PDT 24 12831656580 ps
T913 /workspace/coverage/default/2.chip_sw_uart_smoketest.2317131384 Apr 30 04:46:13 PM PDT 24 Apr 30 04:51:49 PM PDT 24 3078358000 ps
T602 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2123654505 Apr 30 04:24:15 PM PDT 24 Apr 30 04:53:48 PM PDT 24 6365053656 ps
T112 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4084869339 Apr 30 04:42:58 PM PDT 24 Apr 30 05:30:16 PM PDT 24 21249038422 ps
T175 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1243800655 Apr 30 04:42:28 PM PDT 24 Apr 30 04:54:04 PM PDT 24 8510802838 ps
T914 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.216693191 Apr 30 04:41:33 PM PDT 24 Apr 30 04:46:53 PM PDT 24 2827976936 ps
T312 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1143227953 Apr 30 04:39:16 PM PDT 24 Apr 30 04:51:18 PM PDT 24 4157629124 ps
T220 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4085508722 Apr 30 04:40:25 PM PDT 24 Apr 30 05:05:08 PM PDT 24 9781780000 ps
T132 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.477294406 Apr 30 04:41:45 PM PDT 24 Apr 30 04:56:22 PM PDT 24 5738186136 ps
T729 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.24717595 Apr 30 04:50:25 PM PDT 24 Apr 30 04:56:23 PM PDT 24 3995414656 ps
T324 /workspace/coverage/default/64.chip_sw_all_escalation_resets.813731616 Apr 30 04:52:02 PM PDT 24 Apr 30 04:59:19 PM PDT 24 5628816406 ps
T652 /workspace/coverage/default/90.chip_sw_all_escalation_resets.490291053 Apr 30 04:51:15 PM PDT 24 Apr 30 05:00:50 PM PDT 24 5093457576 ps
T915 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.818508654 Apr 30 04:40:06 PM PDT 24 Apr 30 04:54:11 PM PDT 24 4797083888 ps
T916 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3048087166 Apr 30 04:24:50 PM PDT 24 Apr 30 04:32:04 PM PDT 24 3508436360 ps
T917 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1631913769 Apr 30 04:31:15 PM PDT 24 Apr 30 04:36:48 PM PDT 24 3866035577 ps
T317 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.301513727 Apr 30 04:34:57 PM PDT 24 Apr 30 04:46:27 PM PDT 24 4418655000 ps
T176 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1182880259 Apr 30 04:26:25 PM PDT 24 Apr 30 04:30:57 PM PDT 24 2920130180 ps
T918 /workspace/coverage/default/1.chip_sw_kmac_entropy.1249773511 Apr 30 04:30:57 PM PDT 24 Apr 30 04:34:21 PM PDT 24 2840315500 ps
T919 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1963837486 Apr 30 04:40:37 PM PDT 24 Apr 30 04:47:45 PM PDT 24 4246164380 ps
T920 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.194997825 Apr 30 04:25:21 PM PDT 24 Apr 30 04:32:13 PM PDT 24 2733535172 ps
T331 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3716323797 Apr 30 04:49:37 PM PDT 24 Apr 30 04:59:00 PM PDT 24 6062986892 ps
T921 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1714075275 Apr 30 04:41:41 PM PDT 24 Apr 30 05:17:52 PM PDT 24 9731249870 ps
T922 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3797655819 Apr 30 04:47:53 PM PDT 24 Apr 30 04:59:42 PM PDT 24 10343349847 ps
T228 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2100457984 Apr 30 04:23:10 PM PDT 24 Apr 30 05:49:15 PM PDT 24 50085432695 ps
T923 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1923036629 Apr 30 04:48:31 PM PDT 24 Apr 30 05:11:00 PM PDT 24 8693606384 ps
T924 /workspace/coverage/default/0.chip_sw_otbn_randomness.3178873537 Apr 30 04:25:19 PM PDT 24 Apr 30 04:42:20 PM PDT 24 5448076654 ps
T231 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2953516040 Apr 30 04:24:58 PM PDT 24 Apr 30 04:31:25 PM PDT 24 4948875425 ps
T925 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.936453260 Apr 30 04:31:56 PM PDT 24 Apr 30 04:36:21 PM PDT 24 3182705497 ps
T170 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3472813387 Apr 30 04:41:42 PM PDT 24 Apr 30 04:53:21 PM PDT 24 5043412460 ps
T733 /workspace/coverage/default/78.chip_sw_all_escalation_resets.160670657 Apr 30 04:50:21 PM PDT 24 Apr 30 05:00:33 PM PDT 24 6388286400 ps
T197 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1218208937 Apr 30 04:47:15 PM PDT 24 Apr 30 04:56:48 PM PDT 24 3943344900 ps
T696 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1352958818 Apr 30 04:51:33 PM PDT 24 Apr 30 04:58:52 PM PDT 24 3967454408 ps
T926 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1514920420 Apr 30 04:50:44 PM PDT 24 Apr 30 04:57:04 PM PDT 24 4072537060 ps
T75 /workspace/coverage/default/2.chip_jtag_csr_rw.1125710269 Apr 30 04:34:55 PM PDT 24 Apr 30 04:39:32 PM PDT 24 3645503476 ps
T927 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.743678158 Apr 30 04:36:07 PM PDT 24 Apr 30 04:43:06 PM PDT 24 5862159448 ps
T212 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1732580520 Apr 30 04:23:32 PM PDT 24 Apr 30 04:32:51 PM PDT 24 4777001113 ps
T928 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3115316607 Apr 30 04:32:17 PM PDT 24 Apr 30 04:51:39 PM PDT 24 11767016508 ps
T929 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3230747056 Apr 30 04:29:30 PM PDT 24 Apr 30 04:36:30 PM PDT 24 5431652438 ps
T930 /workspace/coverage/default/0.chip_sw_hmac_smoketest.538700152 Apr 30 04:30:33 PM PDT 24 Apr 30 04:36:20 PM PDT 24 2896611172 ps
T931 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4241955183 Apr 30 04:31:04 PM PDT 24 Apr 30 04:41:59 PM PDT 24 6037779760 ps
T932 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3077892469 Apr 30 04:45:35 PM PDT 24 Apr 30 05:09:33 PM PDT 24 8586798412 ps
T705 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2341658358 Apr 30 04:47:57 PM PDT 24 Apr 30 04:57:40 PM PDT 24 6146920280 ps
T933 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1994763581 Apr 30 04:32:29 PM PDT 24 Apr 30 04:36:54 PM PDT 24 2923640228 ps
T934 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1193374329 Apr 30 04:23:37 PM PDT 24 Apr 30 04:27:03 PM PDT 24 2431989928 ps
T935 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4228078896 Apr 30 04:27:01 PM PDT 24 Apr 30 04:32:45 PM PDT 24 3635584895 ps
T64 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2559658436 Apr 30 04:43:03 PM PDT 24 Apr 30 04:48:52 PM PDT 24 3772327752 ps
T23 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3542579971 Apr 30 04:35:42 PM PDT 24 Apr 30 04:40:15 PM PDT 24 3260346401 ps
T205 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3678132514 Apr 30 04:31:15 PM PDT 24 Apr 30 07:35:36 PM PDT 24 64274235012 ps
T936 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.701484987 Apr 30 04:41:20 PM PDT 24 Apr 30 05:00:49 PM PDT 24 7049034212 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3597474156 Apr 30 04:21:08 PM PDT 24 Apr 30 04:28:28 PM PDT 24 3094846460 ps
T24 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.107659277 Apr 30 04:29:14 PM PDT 24 Apr 30 04:36:28 PM PDT 24 3647037170 ps
T372 /workspace/coverage/default/80.chip_sw_all_escalation_resets.2551701819 Apr 30 04:51:05 PM PDT 24 Apr 30 05:01:40 PM PDT 24 5297710294 ps
T88 /workspace/coverage/default/34.chip_sw_all_escalation_resets.1501170476 Apr 30 04:48:10 PM PDT 24 Apr 30 04:58:21 PM PDT 24 5445816200 ps
T373 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1491392765 Apr 30 04:32:23 PM PDT 24 Apr 30 04:52:42 PM PDT 24 5513348998 ps
T374 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3693288760 Apr 30 04:40:10 PM PDT 24 Apr 30 04:50:55 PM PDT 24 5901651780 ps
T375 /workspace/coverage/default/46.chip_sw_all_escalation_resets.203489482 Apr 30 04:50:14 PM PDT 24 Apr 30 04:57:48 PM PDT 24 5565278974 ps
T376 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1916839824 Apr 30 04:39:00 PM PDT 24 Apr 30 04:41:57 PM PDT 24 2320602758 ps
T377 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3253927560 Apr 30 04:52:27 PM PDT 24 Apr 30 05:01:59 PM PDT 24 5920758756 ps
T313 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.858210296 Apr 30 04:39:38 PM PDT 24 Apr 30 04:52:01 PM PDT 24 4591053946 ps
T245 /workspace/coverage/default/0.chip_sw_power_sleep_load.2959413466 Apr 30 04:31:29 PM PDT 24 Apr 30 04:38:08 PM PDT 24 4529481438 ps
T415 /workspace/coverage/default/4.chip_tap_straps_prod.3871498446 Apr 30 04:46:43 PM PDT 24 Apr 30 05:09:58 PM PDT 24 14607686049 ps
T416 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3887955881 Apr 30 04:46:26 PM PDT 24 Apr 30 04:56:30 PM PDT 24 4225070420 ps
T417 /workspace/coverage/default/2.chip_tap_straps_rma.3229385676 Apr 30 04:43:37 PM PDT 24 Apr 30 04:52:21 PM PDT 24 5363693657 ps
T418 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2115292742 Apr 30 04:43:23 PM PDT 24 Apr 30 05:02:42 PM PDT 24 5459589382 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.534302950 Apr 30 04:24:24 PM PDT 24 Apr 30 04:34:03 PM PDT 24 5576431960 ps
T206 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2793076696 Apr 30 04:22:46 PM PDT 24 Apr 30 07:57:30 PM PDT 24 77316326544 ps
T419 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.725037233 Apr 30 04:31:42 PM PDT 24 Apr 30 04:55:40 PM PDT 24 8728856340 ps
T937 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4018932218 Apr 30 04:30:41 PM PDT 24 Apr 30 04:41:07 PM PDT 24 4046469360 ps
T938 /workspace/coverage/default/2.chip_sw_example_flash.857175419 Apr 30 04:38:52 PM PDT 24 Apr 30 04:42:22 PM PDT 24 2414186364 ps
T713 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962691494 Apr 30 04:51:53 PM PDT 24 Apr 30 04:57:57 PM PDT 24 3801538450 ps
T25 /workspace/coverage/default/0.chip_sw_gpio.1794025410 Apr 30 04:21:48 PM PDT 24 Apr 30 04:30:05 PM PDT 24 4228943576 ps
T939 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3096534536 Apr 30 04:41:26 PM PDT 24 Apr 30 04:52:25 PM PDT 24 7152005372 ps
T179 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3962264084 Apr 30 04:32:46 PM PDT 24 Apr 30 05:55:58 PM PDT 24 43183863244 ps
T262 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1916484428 Apr 30 04:41:45 PM PDT 24 Apr 30 04:43:29 PM PDT 24 1730101804 ps
T706 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3052717413 Apr 30 04:52:06 PM PDT 24 Apr 30 04:59:57 PM PDT 24 4268752408 ps
T225 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.666712899 Apr 30 04:31:56 PM PDT 24 Apr 30 05:01:25 PM PDT 24 18636292108 ps
T301 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4139823045 Apr 30 04:30:35 PM PDT 24 Apr 30 05:02:59 PM PDT 24 11304290744 ps
T349 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3169729634 Apr 30 04:22:54 PM PDT 24 Apr 30 04:30:51 PM PDT 24 3189454350 ps
T660 /workspace/coverage/default/82.chip_sw_all_escalation_resets.106296502 Apr 30 04:50:42 PM PDT 24 Apr 30 05:01:05 PM PDT 24 5659464730 ps
T940 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.204163456 Apr 30 04:24:06 PM PDT 24 Apr 30 04:40:59 PM PDT 24 5022551356 ps
T252 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2421151352 Apr 30 04:33:36 PM PDT 24 Apr 30 08:04:37 PM PDT 24 255686103900 ps
T678 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3129828243 Apr 30 04:51:52 PM PDT 24 Apr 30 04:59:15 PM PDT 24 4569727046 ps
T721 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1552786768 Apr 30 04:49:27 PM PDT 24 Apr 30 04:59:47 PM PDT 24 5542870948 ps
T941 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.524844378 Apr 30 04:34:38 PM PDT 24 Apr 30 04:43:00 PM PDT 24 4938761336 ps
T942 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.437158584 Apr 30 04:29:38 PM PDT 24 Apr 30 04:58:19 PM PDT 24 8799535360 ps
T943 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2293860417 Apr 30 04:46:05 PM PDT 24 Apr 30 05:02:15 PM PDT 24 12126644046 ps
T177 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2987075734 Apr 30 04:31:31 PM PDT 24 Apr 30 04:35:36 PM PDT 24 3192003920 ps
T944 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2586958240 Apr 30 04:26:41 PM PDT 24 Apr 30 04:33:04 PM PDT 24 3379540310 ps
T304 /workspace/coverage/default/2.chip_plic_all_irqs_0.1021394695 Apr 30 04:41:50 PM PDT 24 Apr 30 05:00:35 PM PDT 24 6164802202 ps
T945 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3670079325 Apr 30 04:31:27 PM PDT 24 Apr 30 04:34:48 PM PDT 24 2661564648 ps
T738 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3071781895 Apr 30 04:48:44 PM PDT 24 Apr 30 04:59:37 PM PDT 24 5134585420 ps
T946 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.76039051 Apr 30 04:44:13 PM PDT 24 Apr 30 04:53:40 PM PDT 24 3458257518 ps
T947 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4054159279 Apr 30 04:47:19 PM PDT 24 Apr 30 04:58:25 PM PDT 24 4008870300 ps
T332 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1437469800 Apr 30 04:48:18 PM PDT 24 Apr 30 04:58:27 PM PDT 24 5330273890 ps
T948 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.141020174 Apr 30 04:31:35 PM PDT 24 Apr 30 04:39:38 PM PDT 24 5510870374 ps
T601 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.260363968 Apr 30 04:46:04 PM PDT 24 Apr 30 06:01:13 PM PDT 24 29103394096 ps
T949 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1786296961 Apr 30 04:41:27 PM PDT 24 Apr 30 05:07:03 PM PDT 24 7924807196 ps
T273 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1634921634 Apr 30 04:29:43 PM PDT 24 Apr 30 04:39:23 PM PDT 24 5103555734 ps
T263 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4172909665 Apr 30 04:39:29 PM PDT 24 Apr 30 04:41:26 PM PDT 24 1921388289 ps
T950 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1183063447 Apr 30 04:36:33 PM PDT 24 Apr 30 04:42:40 PM PDT 24 2957394198 ps
T697 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3481619341 Apr 30 04:53:16 PM PDT 24 Apr 30 05:04:21 PM PDT 24 5100903088 ps
T951 /workspace/coverage/default/0.chip_tap_straps_prod.1758187710 Apr 30 04:28:48 PM PDT 24 Apr 30 04:30:59 PM PDT 24 2583875991 ps
T952 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2016674630 Apr 30 04:36:49 PM PDT 24 Apr 30 05:01:47 PM PDT 24 9454689280 ps
T953 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2561248228 Apr 30 04:29:58 PM PDT 24 Apr 30 04:52:38 PM PDT 24 8336728640 ps
T171 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3132364751 Apr 30 04:27:46 PM PDT 24 Apr 30 04:37:15 PM PDT 24 4984998617 ps
T704 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3090936639 Apr 30 04:51:01 PM PDT 24 Apr 30 04:58:43 PM PDT 24 5777147240 ps
T954 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.676677528 Apr 30 04:35:40 PM PDT 24 Apr 30 04:39:00 PM PDT 24 3307753560 ps
T309 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.898006359 Apr 30 04:22:57 PM PDT 24 Apr 30 04:35:42 PM PDT 24 4093909068 ps
T955 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1305807525 Apr 30 04:42:38 PM PDT 24 Apr 30 04:52:10 PM PDT 24 4444924560 ps
T725 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2996415381 Apr 30 04:50:24 PM PDT 24 Apr 30 04:57:35 PM PDT 24 3839399480 ps
T956 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2615934439 Apr 30 04:39:59 PM PDT 24 Apr 30 04:46:01 PM PDT 24 3158008288 ps
T957 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1361527554 Apr 30 04:47:30 PM PDT 24 Apr 30 04:55:30 PM PDT 24 5446263360 ps
T274 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2886078146 Apr 30 04:26:30 PM PDT 24 Apr 30 04:39:11 PM PDT 24 5485181926 ps
T958 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1305282186 Apr 30 04:34:59 PM PDT 24 Apr 30 04:50:07 PM PDT 24 9330483785 ps
T627 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2489699534 Apr 30 04:41:22 PM PDT 24 Apr 30 08:12:31 PM PDT 24 256201497248 ps
T356 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.80720259 Apr 30 04:42:20 PM PDT 24 Apr 30 04:46:05 PM PDT 24 3145763968 ps
T680 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2023466229 Apr 30 04:52:32 PM PDT 24 Apr 30 05:03:02 PM PDT 24 5767296688 ps
T959 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.50629910 Apr 30 04:31:24 PM PDT 24 Apr 30 04:41:03 PM PDT 24 4487944060 ps
T275 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3237521650 Apr 30 04:30:47 PM PDT 24 Apr 30 04:37:27 PM PDT 24 5071627327 ps
T229 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3735233212 Apr 30 04:29:52 PM PDT 24 Apr 30 05:00:16 PM PDT 24 21659719982 ps
T960 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3712275577 Apr 30 04:23:31 PM PDT 24 Apr 30 04:42:13 PM PDT 24 8597380054 ps
T961 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.458918064 Apr 30 04:40:55 PM PDT 24 Apr 30 05:02:47 PM PDT 24 6100371256 ps
T315 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3336192807 Apr 30 04:25:10 PM PDT 24 Apr 30 04:54:29 PM PDT 24 7461885500 ps
T962 /workspace/coverage/default/2.chip_sw_power_sleep_load.3574290232 Apr 30 04:42:34 PM PDT 24 Apr 30 04:49:39 PM PDT 24 4572729696 ps
T963 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1066920790 Apr 30 04:42:18 PM PDT 24 Apr 30 04:52:19 PM PDT 24 5030172780 ps
T964 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3281338444 Apr 30 04:25:35 PM PDT 24 Apr 30 04:39:15 PM PDT 24 6327457956 ps
T135 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3467921699 Apr 30 04:47:48 PM PDT 24 Apr 30 05:00:14 PM PDT 24 5819368916 ps
T703 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1993468586 Apr 30 04:47:53 PM PDT 24 Apr 30 04:58:54 PM PDT 24 5806048296 ps
T965 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1103148767 Apr 30 04:36:16 PM PDT 24 Apr 30 04:56:16 PM PDT 24 7207010020 ps
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