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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.49 94.26 95.69 94.98 97.38 99.55


Total test records in report: 2783
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T1105 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2614929288 Apr 30 04:45:56 PM PDT 24 Apr 30 04:54:01 PM PDT 24 4511472104 ps
T1106 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193603045 Apr 30 04:47:55 PM PDT 24 Apr 30 04:52:30 PM PDT 24 3378741644 ps
T1107 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2139701566 Apr 30 04:23:50 PM PDT 24 Apr 30 04:31:45 PM PDT 24 6826602324 ps
T1108 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4101225137 Apr 30 04:24:46 PM PDT 24 Apr 30 04:45:48 PM PDT 24 9078036068 ps
T693 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1145998679 Apr 30 04:35:11 PM PDT 24 Apr 30 04:47:55 PM PDT 24 3963184028 ps
T1109 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2016542693 Apr 30 04:38:05 PM PDT 24 Apr 30 05:12:21 PM PDT 24 26852213276 ps
T1110 /workspace/coverage/default/0.chip_sw_coremark.817029155 Apr 30 04:27:21 PM PDT 24 Apr 30 07:04:28 PM PDT 24 49923199734 ps
T1111 /workspace/coverage/default/2.chip_sw_aes_idle.1016906969 Apr 30 04:39:55 PM PDT 24 Apr 30 04:45:05 PM PDT 24 2569479424 ps
T702 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.395636161 Apr 30 04:52:36 PM PDT 24 Apr 30 04:59:42 PM PDT 24 3725913260 ps
T1112 /workspace/coverage/default/0.chip_sival_flash_info_access.3817491896 Apr 30 04:23:17 PM PDT 24 Apr 30 04:27:50 PM PDT 24 3447209496 ps
T1113 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3322297307 Apr 30 04:49:38 PM PDT 24 Apr 30 04:58:32 PM PDT 24 5067047512 ps
T1114 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3114225542 Apr 30 04:23:31 PM PDT 24 Apr 30 04:31:24 PM PDT 24 7386410165 ps
T1115 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2420959932 Apr 30 04:32:30 PM PDT 24 Apr 30 04:40:29 PM PDT 24 4735180576 ps
T348 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3362712175 Apr 30 04:27:05 PM PDT 24 Apr 30 04:40:52 PM PDT 24 4911647982 ps
T184 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1811325516 Apr 30 04:24:53 PM PDT 24 Apr 30 04:39:30 PM PDT 24 8961238652 ps
T1116 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2909577721 Apr 30 04:46:58 PM PDT 24 Apr 30 05:23:39 PM PDT 24 12895735310 ps
T1117 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2497062366 Apr 30 04:43:30 PM PDT 24 Apr 30 04:48:05 PM PDT 24 3221902688 ps
T1118 /workspace/coverage/default/0.chip_sw_uart_smoketest.1763644399 Apr 30 04:30:27 PM PDT 24 Apr 30 04:34:17 PM PDT 24 2881765920 ps
T89 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3996101730 Apr 30 04:52:08 PM PDT 24 Apr 30 05:01:09 PM PDT 24 5045754812 ps
T670 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3950656064 Apr 30 04:52:44 PM PDT 24 Apr 30 05:01:19 PM PDT 24 5896416844 ps
T1119 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1522088620 Apr 30 04:39:58 PM PDT 24 Apr 30 04:46:35 PM PDT 24 7312000128 ps
T1120 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3179886568 Apr 30 04:33:52 PM PDT 24 Apr 30 04:46:35 PM PDT 24 5042302468 ps
T1121 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2198404905 Apr 30 04:52:06 PM PDT 24 Apr 30 04:59:42 PM PDT 24 4510338008 ps
T1122 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3959175713 Apr 30 04:42:54 PM PDT 24 Apr 30 04:49:51 PM PDT 24 3227463830 ps
T49 /workspace/coverage/default/0.chip_jtag_csr_rw.4074663161 Apr 30 04:18:13 PM PDT 24 Apr 30 05:05:21 PM PDT 24 22235561920 ps
T90 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163968269 Apr 30 04:50:26 PM PDT 24 Apr 30 04:56:47 PM PDT 24 3431375656 ps
T379 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3197033262 Apr 30 04:27:11 PM PDT 24 Apr 30 04:58:54 PM PDT 24 8495746683 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3452209961 Apr 30 04:26:03 PM PDT 24 Apr 30 04:33:28 PM PDT 24 4848679920 ps
T381 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649063680 Apr 30 04:52:08 PM PDT 24 Apr 30 04:57:09 PM PDT 24 3706302280 ps
T382 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1141246685 Apr 30 04:36:20 PM PDT 24 Apr 30 04:54:57 PM PDT 24 5783788709 ps
T383 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1073821574 Apr 30 04:47:54 PM PDT 24 Apr 30 05:13:47 PM PDT 24 8655975088 ps
T384 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.427073313 Apr 30 04:22:58 PM PDT 24 Apr 30 05:18:57 PM PDT 24 18429163074 ps
T232 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.491283515 Apr 30 04:29:59 PM PDT 24 Apr 30 05:52:52 PM PDT 24 48368117895 ps
T385 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.413339317 Apr 30 04:37:45 PM PDT 24 Apr 30 05:20:26 PM PDT 24 32248939656 ps
T1123 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.50921468 Apr 30 04:23:40 PM PDT 24 Apr 30 04:53:18 PM PDT 24 8322430176 ps
T1124 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3794347415 Apr 30 04:51:24 PM PDT 24 Apr 30 04:56:43 PM PDT 24 3603576416 ps
T1125 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3364088068 Apr 30 04:40:18 PM PDT 24 Apr 30 04:53:25 PM PDT 24 5840239371 ps
T1126 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1719691247 Apr 30 04:40:14 PM PDT 24 Apr 30 04:58:21 PM PDT 24 5126949117 ps
T1127 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.232267808 Apr 30 04:23:43 PM PDT 24 Apr 30 04:47:58 PM PDT 24 12291342526 ps
T1128 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1981225082 Apr 30 04:42:16 PM PDT 24 Apr 30 04:47:29 PM PDT 24 3103963768 ps
T136 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3431880008 Apr 30 04:41:34 PM PDT 24 Apr 30 04:49:45 PM PDT 24 5032095094 ps
T1129 /workspace/coverage/default/1.chip_sw_plic_sw_irq.2832180926 Apr 30 04:31:30 PM PDT 24 Apr 30 04:36:13 PM PDT 24 2961470228 ps
T686 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.965654141 Apr 30 04:47:30 PM PDT 24 Apr 30 04:52:56 PM PDT 24 3679197536 ps
T617 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1929164951 Apr 30 04:22:11 PM PDT 24 Apr 30 04:24:09 PM PDT 24 3735203633 ps
T1130 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2712424755 Apr 30 04:28:47 PM PDT 24 Apr 30 04:32:39 PM PDT 24 3551466079 ps
T731 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2138555399 Apr 30 04:49:03 PM PDT 24 Apr 30 04:57:54 PM PDT 24 5324314060 ps
T1131 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2397894070 Apr 30 04:24:58 PM PDT 24 Apr 30 04:29:09 PM PDT 24 2728764872 ps
T1132 /workspace/coverage/default/1.chip_tap_straps_dev.3072133416 Apr 30 04:31:18 PM PDT 24 Apr 30 05:04:45 PM PDT 24 16608984683 ps
T1133 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.182877677 Apr 30 04:37:24 PM PDT 24 Apr 30 05:11:34 PM PDT 24 24361957119 ps
T1134 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.411411240 Apr 30 04:38:33 PM PDT 24 Apr 30 04:55:28 PM PDT 24 8224554876 ps
T1135 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2856179388 Apr 30 04:34:11 PM PDT 24 Apr 30 04:38:42 PM PDT 24 3321812760 ps
T1136 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4087076177 Apr 30 04:39:29 PM PDT 24 Apr 30 04:45:45 PM PDT 24 7297670838 ps
T1137 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3640027724 Apr 30 04:47:27 PM PDT 24 Apr 30 04:52:59 PM PDT 24 3445152792 ps
T1138 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.350791603 Apr 30 04:37:32 PM PDT 24 Apr 30 04:40:32 PM PDT 24 2630104948 ps
T1139 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2573587577 Apr 30 04:33:44 PM PDT 24 Apr 30 04:37:00 PM PDT 24 2650495886 ps
T1140 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2228298710 Apr 30 04:38:10 PM PDT 24 Apr 30 04:48:43 PM PDT 24 5425269188 ps
T350 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3865750731 Apr 30 04:31:11 PM PDT 24 Apr 30 04:45:45 PM PDT 24 4920798760 ps
T1141 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1149008191 Apr 30 04:40:12 PM PDT 24 Apr 30 04:47:48 PM PDT 24 4839443268 ps
T710 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3367743255 Apr 30 04:52:36 PM PDT 24 Apr 30 05:03:45 PM PDT 24 6182609640 ps
T358 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3471924229 Apr 30 04:34:17 PM PDT 24 Apr 30 04:38:08 PM PDT 24 2545956072 ps
T1142 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1821439409 Apr 30 04:31:25 PM PDT 24 Apr 30 04:44:11 PM PDT 24 8676795710 ps
T1143 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1435854085 Apr 30 04:44:54 PM PDT 24 Apr 30 04:55:06 PM PDT 24 4688732548 ps
T613 /workspace/coverage/default/3.chip_tap_straps_dev.1058449493 Apr 30 04:46:03 PM PDT 24 Apr 30 05:03:53 PM PDT 24 10969425229 ps
T91 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138905333 Apr 30 04:48:43 PM PDT 24 Apr 30 04:54:59 PM PDT 24 3746764868 ps
T1144 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.622099167 Apr 30 04:32:29 PM PDT 24 Apr 30 04:37:08 PM PDT 24 3161256305 ps
T1145 /workspace/coverage/default/0.chip_sw_csrng_smoketest.324451055 Apr 30 04:33:05 PM PDT 24 Apr 30 04:38:54 PM PDT 24 2967698832 ps
T1146 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.819896093 Apr 30 04:46:42 PM PDT 24 Apr 30 04:57:22 PM PDT 24 5433308580 ps
T1147 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1959141631 Apr 30 04:36:31 PM PDT 24 Apr 30 04:46:34 PM PDT 24 3861185556 ps
T647 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3966865237 Apr 30 04:48:17 PM PDT 24 Apr 30 04:54:41 PM PDT 24 3787233934 ps
T1148 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2375382657 Apr 30 04:39:43 PM PDT 24 Apr 30 04:44:09 PM PDT 24 3140095000 ps
T251 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2012606355 Apr 30 04:42:57 PM PDT 24 Apr 30 04:52:39 PM PDT 24 3962607170 ps
T1149 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2091276859 Apr 30 04:38:21 PM PDT 24 Apr 30 04:44:47 PM PDT 24 4591133680 ps
T1150 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.254062542 Apr 30 04:23:48 PM PDT 24 Apr 30 04:29:45 PM PDT 24 4312862160 ps
T1151 /workspace/coverage/default/0.rom_keymgr_functest.2854747710 Apr 30 04:31:58 PM PDT 24 Apr 30 04:40:42 PM PDT 24 4471284704 ps
T337 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2493342940 Apr 30 04:29:22 PM PDT 24 Apr 30 04:38:51 PM PDT 24 3714149258 ps
T355 /workspace/coverage/default/45.chip_sw_all_escalation_resets.448923583 Apr 30 04:48:44 PM PDT 24 Apr 30 04:56:43 PM PDT 24 6245579944 ps
T742 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448538869 Apr 30 04:51:58 PM PDT 24 Apr 30 04:57:41 PM PDT 24 4150143664 ps
T302 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2073838676 Apr 30 04:38:33 PM PDT 24 Apr 30 05:06:58 PM PDT 24 12465325528 ps
T1152 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2899561117 Apr 30 04:49:33 PM PDT 24 Apr 30 04:56:51 PM PDT 24 4324500480 ps
T1153 /workspace/coverage/default/0.chip_sw_power_idle_load.3688071637 Apr 30 04:27:15 PM PDT 24 Apr 30 04:38:32 PM PDT 24 4454917528 ps
T1154 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3462320983 Apr 30 04:23:44 PM PDT 24 Apr 30 04:47:21 PM PDT 24 7063323790 ps
T1155 /workspace/coverage/default/0.chip_sw_aes_entropy.450070039 Apr 30 04:23:34 PM PDT 24 Apr 30 04:28:16 PM PDT 24 2803615476 ps
T1156 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2550146134 Apr 30 04:27:43 PM PDT 24 Apr 30 04:45:50 PM PDT 24 7249383951 ps
T1157 /workspace/coverage/default/1.chip_sw_csrng_smoketest.4291027507 Apr 30 04:34:18 PM PDT 24 Apr 30 04:37:55 PM PDT 24 2676029132 ps
T1158 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1177307210 Apr 30 04:24:59 PM PDT 24 Apr 30 05:48:42 PM PDT 24 46607044670 ps
T1159 /workspace/coverage/default/59.chip_sw_all_escalation_resets.864079915 Apr 30 04:53:05 PM PDT 24 Apr 30 05:03:37 PM PDT 24 5489057992 ps
T665 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2527394175 Apr 30 04:51:53 PM PDT 24 Apr 30 05:02:16 PM PDT 24 5863421090 ps
T1160 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.872449467 Apr 30 04:27:25 PM PDT 24 Apr 30 05:02:46 PM PDT 24 20754143034 ps
T1161 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2129919336 Apr 30 04:46:17 PM PDT 24 Apr 30 04:55:12 PM PDT 24 3549226224 ps
T398 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1362822063 Apr 30 04:27:14 PM PDT 24 Apr 30 04:53:26 PM PDT 24 19169091790 ps
T1162 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1063516125 Apr 30 04:48:42 PM PDT 24 Apr 30 04:57:04 PM PDT 24 5699875440 ps
T1163 /workspace/coverage/default/4.chip_tap_straps_rma.4241445720 Apr 30 04:45:36 PM PDT 24 Apr 30 04:50:35 PM PDT 24 3973420399 ps
T414 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657549516 Apr 30 04:48:49 PM PDT 24 Apr 30 04:56:55 PM PDT 24 3912077800 ps
T1164 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2606846161 Apr 30 04:29:46 PM PDT 24 Apr 30 04:33:40 PM PDT 24 2851158408 ps
T1165 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3530338762 Apr 30 04:38:29 PM PDT 24 Apr 30 07:55:29 PM PDT 24 64853288809 ps
T1166 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1147723260 Apr 30 04:34:05 PM PDT 24 Apr 30 04:38:34 PM PDT 24 3354296944 ps
T1167 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3225107915 Apr 30 04:34:15 PM PDT 24 Apr 30 04:41:50 PM PDT 24 3084971320 ps
T1168 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3017968910 Apr 30 04:45:49 PM PDT 24 Apr 30 04:58:13 PM PDT 24 4862171224 ps
T1169 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3861419273 Apr 30 04:32:25 PM PDT 24 Apr 30 04:38:03 PM PDT 24 2887199421 ps
T8 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2544766107 Apr 30 04:31:05 PM PDT 24 Apr 30 04:36:00 PM PDT 24 2718557300 ps
T1170 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750193356 Apr 30 04:52:12 PM PDT 24 Apr 30 04:59:34 PM PDT 24 3801812106 ps
T1171 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2429180339 Apr 30 04:27:47 PM PDT 24 Apr 30 04:38:01 PM PDT 24 5311171235 ps
T1172 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.519373082 Apr 30 04:35:31 PM PDT 24 Apr 30 04:41:51 PM PDT 24 2967236500 ps
T1173 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1727450145 Apr 30 04:41:09 PM PDT 24 Apr 30 04:45:17 PM PDT 24 2626573364 ps
T1174 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4074485035 Apr 30 04:40:40 PM PDT 24 Apr 30 05:01:37 PM PDT 24 11544967112 ps
T92 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2730969734 Apr 30 04:50:30 PM PDT 24 Apr 30 04:59:29 PM PDT 24 4630188792 ps
T1175 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.255965190 Apr 30 04:51:55 PM PDT 24 Apr 30 04:58:09 PM PDT 24 4022493410 ps
T1176 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2131478694 Apr 30 04:51:46 PM PDT 24 Apr 30 04:57:52 PM PDT 24 3299276864 ps
T1177 /workspace/coverage/default/0.chip_sw_kmac_entropy.1644269465 Apr 30 04:21:34 PM PDT 24 Apr 30 04:25:29 PM PDT 24 3149872636 ps
T1178 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2853995901 Apr 30 04:37:31 PM PDT 24 Apr 30 04:39:35 PM PDT 24 2666471533 ps
T1179 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.781808516 Apr 30 04:34:17 PM PDT 24 Apr 30 04:45:03 PM PDT 24 4616656828 ps
T690 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.932375367 Apr 30 04:50:32 PM PDT 24 Apr 30 04:55:24 PM PDT 24 3547842154 ps
T1180 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.801292853 Apr 30 04:43:47 PM PDT 24 Apr 30 05:15:29 PM PDT 24 27118019711 ps
T287 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3925105092 Apr 30 04:42:42 PM PDT 24 Apr 30 04:47:11 PM PDT 24 2959535534 ps
T1181 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1807121679 Apr 30 04:46:14 PM PDT 24 Apr 30 05:07:35 PM PDT 24 8360177858 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1333304973 Apr 30 04:38:03 PM PDT 24 Apr 30 04:42:54 PM PDT 24 3153752132 ps
T1182 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2945550569 Apr 30 04:51:11 PM PDT 24 Apr 30 05:00:59 PM PDT 24 6100902642 ps
T1183 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.80894034 Apr 30 04:43:42 PM PDT 24 Apr 30 04:48:54 PM PDT 24 3272112650 ps
T500 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.605731290 Apr 30 04:45:04 PM PDT 24 Apr 30 04:53:46 PM PDT 24 5283973451 ps
T719 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810410263 Apr 30 04:40:40 PM PDT 24 Apr 30 04:47:39 PM PDT 24 3549865500 ps
T1184 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3690652251 Apr 30 04:31:09 PM PDT 24 Apr 30 04:44:25 PM PDT 24 4505686808 ps
T1185 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3352202400 Apr 30 04:30:21 PM PDT 24 Apr 30 04:32:16 PM PDT 24 1982364498 ps
T1186 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3283273580 Apr 30 04:33:19 PM PDT 24 Apr 30 04:38:56 PM PDT 24 2637391328 ps
T1187 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.897654054 Apr 30 04:34:12 PM PDT 24 Apr 30 04:39:53 PM PDT 24 6622741728 ps
T1188 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2337435658 Apr 30 04:42:09 PM PDT 24 Apr 30 04:50:49 PM PDT 24 5145101106 ps
T352 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1541061604 Apr 30 04:37:00 PM PDT 24 Apr 30 04:51:24 PM PDT 24 4796719536 ps
T1189 /workspace/coverage/default/0.chip_sw_flash_init.2732932456 Apr 30 04:21:41 PM PDT 24 Apr 30 04:52:03 PM PDT 24 18365286794 ps
T1190 /workspace/coverage/default/1.chip_sw_flash_init.2687852939 Apr 30 04:30:35 PM PDT 24 Apr 30 05:02:02 PM PDT 24 22536092556 ps
T1191 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2446852841 Apr 30 04:44:15 PM PDT 24 Apr 30 04:47:03 PM PDT 24 2848360544 ps
T149 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3198249875 Apr 30 04:35:45 PM PDT 24 Apr 30 07:14:36 PM PDT 24 59252795759 ps
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T1215 /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2552574335 Apr 30 04:03:16 PM PDT 24 Apr 30 04:03:55 PM PDT 24 1045544018 ps
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