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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.49 94.26 95.69 94.98 97.38 99.55


Total test records in report: 2783
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T966 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3232994133 Apr 30 04:46:43 PM PDT 24 Apr 30 05:00:29 PM PDT 24 8130032331 ps
T967 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2404421507 Apr 30 04:31:09 PM PDT 24 Apr 30 04:43:45 PM PDT 24 4715680320 ps
T420 /workspace/coverage/default/0.chip_jtag_mem_access.3969731074 Apr 30 04:18:16 PM PDT 24 Apr 30 04:46:37 PM PDT 24 14055893370 ps
T651 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3724884557 Apr 30 04:50:33 PM PDT 24 Apr 30 04:56:44 PM PDT 24 3756693424 ps
T968 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3955012160 Apr 30 04:29:01 PM PDT 24 Apr 30 04:33:39 PM PDT 24 3376377298 ps
T412 /workspace/coverage/default/79.chip_sw_all_escalation_resets.889724828 Apr 30 04:51:11 PM PDT 24 Apr 30 05:02:54 PM PDT 24 6164462800 ps
T969 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1135390305 Apr 30 04:32:26 PM PDT 24 Apr 30 04:42:38 PM PDT 24 3480203900 ps
T700 /workspace/coverage/default/98.chip_sw_all_escalation_resets.2796839551 Apr 30 04:51:47 PM PDT 24 Apr 30 04:58:54 PM PDT 24 5919629720 ps
T734 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.143024705 Apr 30 04:49:48 PM PDT 24 Apr 30 04:55:58 PM PDT 24 3229189064 ps
T970 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2723682641 Apr 30 04:49:35 PM PDT 24 Apr 30 04:56:26 PM PDT 24 3399029608 ps
T659 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2458148047 Apr 30 04:30:38 PM PDT 24 Apr 30 04:41:33 PM PDT 24 5950288078 ps
T99 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.920056559 Apr 30 04:27:02 PM PDT 24 Apr 30 04:33:25 PM PDT 24 7170616146 ps
T50 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3673240344 Apr 30 04:35:45 PM PDT 24 Apr 30 04:40:11 PM PDT 24 3431153450 ps
T390 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4010429497 Apr 30 04:35:22 PM PDT 24 Apr 30 04:42:55 PM PDT 24 3791649544 ps
T391 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.169142353 Apr 30 04:29:54 PM PDT 24 Apr 30 04:45:15 PM PDT 24 5406987176 ps
T392 /workspace/coverage/default/0.chip_sw_example_flash.135377890 Apr 30 04:21:35 PM PDT 24 Apr 30 04:25:32 PM PDT 24 2554082708 ps
T393 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.996432225 Apr 30 04:46:28 PM PDT 24 Apr 30 05:00:29 PM PDT 24 11444752635 ps
T394 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3061588233 Apr 30 04:53:23 PM PDT 24 Apr 30 05:02:58 PM PDT 24 5861549466 ps
T395 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3580945309 Apr 30 04:31:24 PM PDT 24 Apr 30 05:37:52 PM PDT 24 17751782496 ps
T396 /workspace/coverage/default/2.chip_sw_kmac_smoketest.239626712 Apr 30 04:44:39 PM PDT 24 Apr 30 04:47:45 PM PDT 24 2796789416 ps
T397 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1273789179 Apr 30 04:31:00 PM PDT 24 Apr 30 04:40:09 PM PDT 24 9013116460 ps
T353 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2586930513 Apr 30 04:25:49 PM PDT 24 Apr 30 04:44:47 PM PDT 24 7036056980 ps
T159 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1705348644 Apr 30 04:29:40 PM PDT 24 Apr 30 04:31:09 PM PDT 24 2298070017 ps
T971 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2880670192 Apr 30 04:36:39 PM PDT 24 Apr 30 04:41:00 PM PDT 24 2922652152 ps
T972 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1705509983 Apr 30 04:45:47 PM PDT 24 Apr 30 04:56:27 PM PDT 24 4564759720 ps
T973 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.540376149 Apr 30 04:39:25 PM PDT 24 Apr 30 04:49:41 PM PDT 24 5726604472 ps
T727 /workspace/coverage/default/31.chip_sw_all_escalation_resets.4149387176 Apr 30 04:48:49 PM PDT 24 Apr 30 04:58:13 PM PDT 24 5342582124 ps
T57 /workspace/coverage/default/2.chip_sw_alert_test.969861153 Apr 30 04:40:33 PM PDT 24 Apr 30 04:45:57 PM PDT 24 2652935172 ps
T974 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2126309846 Apr 30 04:38:24 PM PDT 24 Apr 30 04:59:42 PM PDT 24 11947739647 ps
T674 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3681880709 Apr 30 04:47:57 PM PDT 24 Apr 30 04:57:55 PM PDT 24 4475182704 ps
T614 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2567144256 Apr 30 04:24:01 PM PDT 24 Apr 30 04:25:59 PM PDT 24 3009216202 ps
T975 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.90473613 Apr 30 04:27:25 PM PDT 24 Apr 30 04:40:45 PM PDT 24 6682679080 ps
T699 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3043867386 Apr 30 04:52:14 PM PDT 24 Apr 30 04:58:45 PM PDT 24 3793517944 ps
T740 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3098156864 Apr 30 04:48:48 PM PDT 24 Apr 30 04:55:52 PM PDT 24 4892034728 ps
T286 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2435890304 Apr 30 04:27:09 PM PDT 24 Apr 30 04:31:50 PM PDT 24 2427907068 ps
T237 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2723863154 Apr 30 04:37:28 PM PDT 24 Apr 30 04:49:56 PM PDT 24 6688618138 ps
T38 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1497583796 Apr 30 04:40:42 PM PDT 24 Apr 30 04:47:30 PM PDT 24 4896227410 ps
T976 /workspace/coverage/default/61.chip_sw_all_escalation_resets.3925579034 Apr 30 04:49:20 PM PDT 24 Apr 30 04:57:32 PM PDT 24 3802616750 ps
T661 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2117958068 Apr 30 04:25:10 PM PDT 24 Apr 30 04:50:20 PM PDT 24 11471624640 ps
T154 /workspace/coverage/default/0.chip_plic_all_irqs_10.2842562098 Apr 30 04:26:05 PM PDT 24 Apr 30 04:36:35 PM PDT 24 3780770722 ps
T977 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1506609758 Apr 30 04:44:59 PM PDT 24 Apr 30 04:57:57 PM PDT 24 8310693911 ps
T978 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1488726735 Apr 30 04:25:35 PM PDT 24 Apr 30 04:32:08 PM PDT 24 5329216390 ps
T979 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1169467248 Apr 30 04:40:47 PM PDT 24 Apr 30 04:46:19 PM PDT 24 3222363618 ps
T980 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2896091820 Apr 30 04:36:15 PM PDT 24 Apr 30 04:45:46 PM PDT 24 5609476412 ps
T981 /workspace/coverage/default/3.chip_tap_straps_prod.4276220060 Apr 30 04:44:27 PM PDT 24 Apr 30 05:09:32 PM PDT 24 17613895827 ps
T982 /workspace/coverage/default/0.chip_sw_rv_timer_irq.4286274235 Apr 30 04:22:48 PM PDT 24 Apr 30 04:28:13 PM PDT 24 2906364956 ps
T983 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872988972 Apr 30 04:48:40 PM PDT 24 Apr 30 04:56:34 PM PDT 24 4047770138 ps
T984 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3554281519 Apr 30 04:45:14 PM PDT 24 Apr 30 04:55:39 PM PDT 24 5049513550 ps
T985 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1283494529 Apr 30 04:30:06 PM PDT 24 Apr 30 04:39:45 PM PDT 24 4452531212 ps
T736 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1937602197 Apr 30 04:50:16 PM PDT 24 Apr 30 04:59:37 PM PDT 24 4913707100 ps
T986 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3471063778 Apr 30 04:40:45 PM PDT 24 Apr 30 04:45:07 PM PDT 24 3015171623 ps
T147 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3545708198 Apr 30 04:31:15 PM PDT 24 Apr 30 07:12:54 PM PDT 24 59189197698 ps
T987 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3285283409 Apr 30 04:47:50 PM PDT 24 Apr 30 04:50:43 PM PDT 24 2683970722 ps
T988 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4257401280 Apr 30 04:33:25 PM PDT 24 Apr 30 04:43:59 PM PDT 24 18195629676 ps
T989 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.293595002 Apr 30 04:25:03 PM PDT 24 Apr 30 04:36:07 PM PDT 24 4552164332 ps
T100 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3632360143 Apr 30 04:44:20 PM PDT 24 Apr 30 04:51:04 PM PDT 24 7827908556 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.723860852 Apr 30 04:41:22 PM PDT 24 Apr 30 05:46:30 PM PDT 24 17493563918 ps
T990 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3805354795 Apr 30 04:32:15 PM PDT 24 Apr 30 04:50:02 PM PDT 24 10227427776 ps
T991 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3405291925 Apr 30 04:31:18 PM PDT 24 Apr 30 05:03:52 PM PDT 24 22013268480 ps
T347 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3383815609 Apr 30 04:48:34 PM PDT 24 Apr 30 04:58:13 PM PDT 24 4827371748 ps
T992 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2533923368 Apr 30 04:23:37 PM PDT 24 Apr 30 05:20:21 PM PDT 24 17179482076 ps
T735 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2481716575 Apr 30 04:51:09 PM PDT 24 Apr 30 05:00:11 PM PDT 24 5551784522 ps
T993 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2807147573 Apr 30 04:28:46 PM PDT 24 Apr 30 04:37:49 PM PDT 24 5264300320 ps
T654 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.158601060 Apr 30 04:50:45 PM PDT 24 Apr 30 04:56:41 PM PDT 24 3791517500 ps
T667 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1932996421 Apr 30 04:45:11 PM PDT 24 Apr 30 04:53:25 PM PDT 24 4599099310 ps
T994 /workspace/coverage/default/0.chip_sw_gpio_smoketest.89906809 Apr 30 04:29:15 PM PDT 24 Apr 30 04:33:55 PM PDT 24 3096178356 ps
T233 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1357138727 Apr 30 04:41:37 PM PDT 24 Apr 30 06:07:03 PM PDT 24 46891760076 ps
T995 /workspace/coverage/default/2.rom_keymgr_functest.881271645 Apr 30 04:45:55 PM PDT 24 Apr 30 04:55:32 PM PDT 24 4619533450 ps
T996 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2254707316 Apr 30 04:43:25 PM PDT 24 Apr 30 04:49:33 PM PDT 24 3659440660 ps
T160 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.85234225 Apr 30 04:22:22 PM PDT 24 Apr 30 04:26:00 PM PDT 24 2432238582 ps
T997 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1405380079 Apr 30 04:36:10 PM PDT 24 Apr 30 04:47:25 PM PDT 24 4511694728 ps
T739 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238450515 Apr 30 04:50:31 PM PDT 24 Apr 30 04:57:17 PM PDT 24 3953267712 ps
T684 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545987321 Apr 30 04:54:18 PM PDT 24 Apr 30 05:00:09 PM PDT 24 4081793436 ps
T998 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.992902161 Apr 30 04:25:09 PM PDT 24 Apr 30 04:53:51 PM PDT 24 22935826344 ps
T698 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1939926556 Apr 30 04:50:01 PM PDT 24 Apr 30 04:59:40 PM PDT 24 4764461332 ps
T999 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2162862904 Apr 30 04:29:25 PM PDT 24 Apr 30 04:47:36 PM PDT 24 10666359364 ps
T1000 /workspace/coverage/default/20.chip_sw_all_escalation_resets.675022826 Apr 30 04:49:17 PM PDT 24 Apr 30 04:57:42 PM PDT 24 5060938600 ps
T649 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1668792909 Apr 30 04:46:55 PM PDT 24 Apr 30 04:54:29 PM PDT 24 5358934264 ps
T1001 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.480954329 Apr 30 04:30:25 PM PDT 24 Apr 30 04:34:11 PM PDT 24 2908376339 ps
T1002 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1735989947 Apr 30 04:33:18 PM PDT 24 Apr 30 04:36:50 PM PDT 24 3051630269 ps
T1003 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2160427836 Apr 30 04:45:50 PM PDT 24 Apr 30 05:20:18 PM PDT 24 13408591570 ps
T1004 /workspace/coverage/default/2.chip_tap_straps_dev.2085049745 Apr 30 04:43:40 PM PDT 24 Apr 30 04:47:13 PM PDT 24 3462813221 ps
T1005 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1769187037 Apr 30 04:31:48 PM PDT 24 Apr 30 04:42:12 PM PDT 24 5296153000 ps
T316 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3269292954 Apr 30 04:41:33 PM PDT 24 Apr 30 05:01:57 PM PDT 24 6450518168 ps
T1006 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.593119528 Apr 30 04:42:34 PM PDT 24 Apr 30 04:45:53 PM PDT 24 2552273290 ps
T1007 /workspace/coverage/default/2.chip_sw_kmac_app_rom.753201036 Apr 30 04:41:39 PM PDT 24 Apr 30 04:46:14 PM PDT 24 3308431122 ps
T238 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3765228977 Apr 30 04:34:54 PM PDT 24 Apr 30 04:43:15 PM PDT 24 4932559370 ps
T1008 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.930923327 Apr 30 04:42:56 PM PDT 24 Apr 30 04:46:02 PM PDT 24 3238882540 ps
T1009 /workspace/coverage/default/0.chip_sw_example_manufacturer.2856134660 Apr 30 04:22:03 PM PDT 24 Apr 30 04:25:41 PM PDT 24 2381823320 ps
T249 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3335323903 Apr 30 04:27:13 PM PDT 24 Apr 30 04:35:24 PM PDT 24 4231257976 ps
T1010 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.4088762538 Apr 30 04:30:46 PM PDT 24 Apr 30 04:44:12 PM PDT 24 5631889709 ps
T1011 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.991206413 Apr 30 04:42:05 PM PDT 24 Apr 30 04:52:09 PM PDT 24 7608650896 ps
T276 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.755518632 Apr 30 04:22:28 PM PDT 24 Apr 30 04:36:15 PM PDT 24 5612859976 ps
T1012 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3980873238 Apr 30 04:45:04 PM PDT 24 Apr 30 04:50:29 PM PDT 24 5939429048 ps
T720 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2869239532 Apr 30 04:51:04 PM PDT 24 Apr 30 04:59:37 PM PDT 24 5763446616 ps
T1013 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1544770513 Apr 30 04:45:50 PM PDT 24 Apr 30 04:53:57 PM PDT 24 5307724353 ps
T326 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2877552006 Apr 30 04:32:09 PM PDT 24 Apr 30 04:41:55 PM PDT 24 4474966737 ps
T668 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388476935 Apr 30 04:50:35 PM PDT 24 Apr 30 04:55:59 PM PDT 24 3825739184 ps
T709 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3301973963 Apr 30 04:50:13 PM PDT 24 Apr 30 04:58:21 PM PDT 24 3715512670 ps
T146 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2632514935 Apr 30 04:23:57 PM PDT 24 Apr 30 04:33:52 PM PDT 24 4041282984 ps
T717 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1506467733 Apr 30 04:48:05 PM PDT 24 Apr 30 04:55:07 PM PDT 24 4385431702 ps
T53 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.383240075 Apr 30 04:27:14 PM PDT 24 Apr 30 04:53:21 PM PDT 24 19740460520 ps
T615 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2056229948 Apr 30 04:21:50 PM PDT 24 Apr 30 04:23:49 PM PDT 24 3139152852 ps
T1014 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2530892073 Apr 30 04:22:04 PM PDT 24 Apr 30 04:53:57 PM PDT 24 23689673583 ps
T1015 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.171566454 Apr 30 04:44:58 PM PDT 24 Apr 30 04:49:32 PM PDT 24 2916600184 ps
T1016 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.859657917 Apr 30 04:30:09 PM PDT 24 Apr 30 08:09:16 PM PDT 24 76862091975 ps
T1017 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4264102511 Apr 30 04:26:27 PM PDT 24 Apr 30 04:33:48 PM PDT 24 5249737903 ps
T1018 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2126893640 Apr 30 04:26:21 PM PDT 24 Apr 30 04:37:07 PM PDT 24 4338723590 ps
T650 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.840091176 Apr 30 04:51:38 PM PDT 24 Apr 30 04:56:36 PM PDT 24 3681820440 ps
T1019 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2620869277 Apr 30 04:32:32 PM PDT 24 Apr 30 04:43:20 PM PDT 24 5029517914 ps
T1020 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1231040848 Apr 30 04:30:25 PM PDT 24 Apr 30 04:40:31 PM PDT 24 4495695554 ps
T1021 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1687741989 Apr 30 04:25:10 PM PDT 24 Apr 30 04:36:56 PM PDT 24 8219611380 ps
T603 /workspace/coverage/default/2.chip_sw_edn_boot_mode.4128507518 Apr 30 04:40:06 PM PDT 24 Apr 30 04:48:53 PM PDT 24 3164851152 ps
T267 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1911642138 Apr 30 04:45:29 PM PDT 24 Apr 30 04:56:52 PM PDT 24 6119953720 ps
T1022 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.569909235 Apr 30 04:42:36 PM PDT 24 Apr 30 04:47:59 PM PDT 24 2570811452 ps
T1023 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.996047629 Apr 30 04:49:38 PM PDT 24 Apr 30 04:56:39 PM PDT 24 3806937488 ps
T605 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2477035696 Apr 30 04:24:02 PM PDT 24 Apr 30 04:32:00 PM PDT 24 3290639800 ps
T250 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3034986848 Apr 30 04:31:13 PM PDT 24 Apr 30 04:39:49 PM PDT 24 3716353490 ps
T35 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2818286140 Apr 30 04:30:37 PM PDT 24 Apr 30 04:36:26 PM PDT 24 2542350120 ps
T277 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2069054183 Apr 30 04:24:40 PM PDT 24 Apr 30 04:33:45 PM PDT 24 4387353860 ps
T715 /workspace/coverage/default/18.chip_sw_all_escalation_resets.2315891026 Apr 30 04:47:32 PM PDT 24 Apr 30 04:58:01 PM PDT 24 5653298600 ps
T369 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3404886648 Apr 30 04:34:34 PM PDT 24 Apr 30 04:39:20 PM PDT 24 3367231344 ps
T737 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688789025 Apr 30 04:46:54 PM PDT 24 Apr 30 04:53:07 PM PDT 24 3522945216 ps
T223 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3691808659 Apr 30 04:25:41 PM PDT 24 Apr 30 05:39:16 PM PDT 24 18042998762 ps
T1024 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.749906752 Apr 30 04:25:16 PM PDT 24 Apr 30 04:50:41 PM PDT 24 8937661990 ps
T744 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2647430730 Apr 30 04:47:31 PM PDT 24 Apr 30 04:57:10 PM PDT 24 5860006700 ps
T1025 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2529071909 Apr 30 04:42:37 PM PDT 24 Apr 30 04:51:52 PM PDT 24 4818971112 ps
T1026 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3870033083 Apr 30 04:39:31 PM PDT 24 Apr 30 04:45:07 PM PDT 24 5525368445 ps
T1027 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2908644908 Apr 30 04:51:05 PM PDT 24 Apr 30 04:58:44 PM PDT 24 5869431784 ps
T691 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2206196966 Apr 30 04:51:53 PM PDT 24 Apr 30 05:02:35 PM PDT 24 4510140320 ps
T675 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3044219749 Apr 30 04:50:00 PM PDT 24 Apr 30 05:00:11 PM PDT 24 4560934960 ps
T1028 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.269185658 Apr 30 04:22:10 PM PDT 24 Apr 30 04:33:00 PM PDT 24 4023056246 ps
T1029 /workspace/coverage/default/1.rom_keymgr_functest.2360994280 Apr 30 04:33:55 PM PDT 24 Apr 30 04:42:11 PM PDT 24 4265796240 ps
T1030 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1444591058 Apr 30 04:50:15 PM PDT 24 Apr 30 04:57:31 PM PDT 24 3589149400 ps
T370 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3348782955 Apr 30 04:44:27 PM PDT 24 Apr 30 05:12:22 PM PDT 24 22060649562 ps
T730 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015331597 Apr 30 04:49:23 PM PDT 24 Apr 30 04:57:07 PM PDT 24 3661985140 ps
T181 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3343660573 Apr 30 04:40:48 PM PDT 24 Apr 30 04:49:09 PM PDT 24 3627218330 ps
T1031 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2155329616 Apr 30 04:35:18 PM PDT 24 Apr 30 04:49:24 PM PDT 24 5957898508 ps
T51 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.4094408147 Apr 30 04:22:26 PM PDT 24 Apr 30 04:27:06 PM PDT 24 3382294568 ps
T1032 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3223362843 Apr 30 04:46:52 PM PDT 24 Apr 30 04:54:06 PM PDT 24 6054078836 ps
T1033 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.576845408 Apr 30 04:27:23 PM PDT 24 Apr 30 04:31:12 PM PDT 24 2776503962 ps
T321 /workspace/coverage/default/0.chip_sw_pattgen_ios.4075909350 Apr 30 04:22:35 PM PDT 24 Apr 30 04:27:50 PM PDT 24 2792371000 ps
T1034 /workspace/coverage/default/2.chip_sw_example_rom.1188316392 Apr 30 04:35:04 PM PDT 24 Apr 30 04:37:07 PM PDT 24 2755870648 ps
T708 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3698932674 Apr 30 04:48:40 PM PDT 24 Apr 30 04:56:05 PM PDT 24 3798398676 ps
T1035 /workspace/coverage/default/2.chip_sw_aes_enc.3173204240 Apr 30 04:40:44 PM PDT 24 Apr 30 04:45:05 PM PDT 24 2752465832 ps
T1036 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.837326852 Apr 30 04:32:06 PM PDT 24 Apr 30 04:47:55 PM PDT 24 7856266082 ps
T1037 /workspace/coverage/default/66.chip_sw_all_escalation_resets.783778922 Apr 30 04:51:43 PM PDT 24 Apr 30 05:01:31 PM PDT 24 6049806120 ps
T1038 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4002779462 Apr 30 04:24:36 PM PDT 24 Apr 30 04:35:31 PM PDT 24 5133168176 ps
T1039 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1603032032 Apr 30 04:31:34 PM PDT 24 Apr 30 04:48:18 PM PDT 24 5240985080 ps
T52 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3982538712 Apr 30 04:36:05 PM PDT 24 Apr 30 04:41:09 PM PDT 24 3512430780 ps
T413 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2979781536 Apr 30 04:49:48 PM PDT 24 Apr 30 04:58:05 PM PDT 24 6313855320 ps
T1040 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4017020596 Apr 30 04:37:35 PM PDT 24 Apr 30 04:53:23 PM PDT 24 5795122206 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3211465184 Apr 30 04:27:02 PM PDT 24 Apr 30 04:32:02 PM PDT 24 2533802266 ps
T1042 /workspace/coverage/default/0.chip_sw_hmac_enc.1023429013 Apr 30 04:24:56 PM PDT 24 Apr 30 04:29:22 PM PDT 24 2705635448 ps
T1043 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3171288039 Apr 30 04:41:43 PM PDT 24 Apr 30 04:51:40 PM PDT 24 5165484728 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1422611974 Apr 30 04:25:02 PM PDT 24 Apr 30 05:08:06 PM PDT 24 26192765875 ps
T1045 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.27908702 Apr 30 04:47:06 PM PDT 24 Apr 30 04:57:32 PM PDT 24 4186127620 ps
T1046 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3927737821 Apr 30 04:40:15 PM PDT 24 Apr 30 04:56:00 PM PDT 24 6961006096 ps
T1047 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3543141258 Apr 30 04:41:58 PM PDT 24 Apr 30 04:48:51 PM PDT 24 3717059800 ps
T357 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2238266416 Apr 30 04:31:55 PM PDT 24 Apr 30 04:35:55 PM PDT 24 2556705306 ps
T1048 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.648964576 Apr 30 04:33:34 PM PDT 24 Apr 30 04:39:13 PM PDT 24 2942913912 ps
T182 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.825702425 Apr 30 04:25:11 PM PDT 24 Apr 30 04:33:13 PM PDT 24 3855192320 ps
T1049 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.941466461 Apr 30 04:25:13 PM PDT 24 Apr 30 04:49:33 PM PDT 24 9208853528 ps
T1050 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4175924793 Apr 30 04:31:05 PM PDT 24 Apr 30 04:42:29 PM PDT 24 5760336824 ps
T676 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1188295886 Apr 30 04:52:20 PM PDT 24 Apr 30 05:01:56 PM PDT 24 5864982584 ps
T1051 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3945014484 Apr 30 04:28:38 PM PDT 24 Apr 30 05:25:19 PM PDT 24 24206208973 ps
T716 /workspace/coverage/default/41.chip_sw_all_escalation_resets.124621363 Apr 30 04:48:51 PM PDT 24 Apr 30 04:59:31 PM PDT 24 6117774442 ps
T1052 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1375560512 Apr 30 04:47:49 PM PDT 24 Apr 30 05:10:28 PM PDT 24 8440865728 ps
T616 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1793071852 Apr 30 04:28:19 PM PDT 24 Apr 30 04:29:52 PM PDT 24 2013847908 ps
T1053 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4263135472 Apr 30 04:48:51 PM PDT 24 Apr 30 04:58:45 PM PDT 24 3974761032 ps
T226 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3068564560 Apr 30 04:29:40 PM PDT 24 Apr 30 06:02:46 PM PDT 24 49882387909 ps
T1054 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.169937045 Apr 30 04:24:30 PM PDT 24 Apr 30 04:30:33 PM PDT 24 5220327016 ps
T1055 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3547805986 Apr 30 04:40:37 PM PDT 24 Apr 30 04:44:47 PM PDT 24 2320169377 ps
T1056 /workspace/coverage/default/1.chip_sw_aes_entropy.3656873842 Apr 30 04:33:58 PM PDT 24 Apr 30 04:38:07 PM PDT 24 2844729540 ps
T1057 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3940810630 Apr 30 04:45:12 PM PDT 24 Apr 30 04:48:27 PM PDT 24 3085037086 ps
T1058 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2306863973 Apr 30 04:23:29 PM PDT 24 Apr 30 04:26:59 PM PDT 24 2498377256 ps
T1059 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3030949911 Apr 30 04:29:31 PM PDT 24 Apr 30 04:49:48 PM PDT 24 6839538984 ps
T1060 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2186123031 Apr 30 04:30:38 PM PDT 24 Apr 30 04:45:16 PM PDT 24 6975910497 ps
T1061 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3643182535 Apr 30 04:24:31 PM PDT 24 Apr 30 04:35:19 PM PDT 24 4086577408 ps
T1062 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3976956033 Apr 30 04:41:00 PM PDT 24 Apr 30 05:00:19 PM PDT 24 5747485074 ps
T687 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540384271 Apr 30 04:47:45 PM PDT 24 Apr 30 04:54:43 PM PDT 24 4118579524 ps
T679 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.224605547 Apr 30 04:47:39 PM PDT 24 Apr 30 04:52:35 PM PDT 24 3132425740 ps
T1063 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2534960019 Apr 30 04:34:57 PM PDT 24 Apr 30 04:42:32 PM PDT 24 5050775636 ps
T1064 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3459922100 Apr 30 04:30:23 PM PDT 24 Apr 30 04:47:21 PM PDT 24 5617928590 ps
T495 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3143359858 Apr 30 04:23:08 PM PDT 24 Apr 30 04:36:21 PM PDT 24 4977729720 ps
T1065 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2459276001 Apr 30 04:32:11 PM PDT 24 Apr 30 04:58:14 PM PDT 24 7253961590 ps
T1066 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1096058629 Apr 30 04:39:31 PM PDT 24 Apr 30 04:54:35 PM PDT 24 5559850632 ps
T1067 /workspace/coverage/default/1.chip_sw_example_manufacturer.4194896803 Apr 30 04:30:33 PM PDT 24 Apr 30 04:34:48 PM PDT 24 2633934876 ps
T655 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434008882 Apr 30 04:51:52 PM PDT 24 Apr 30 04:58:50 PM PDT 24 4119231768 ps
T1068 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321324820 Apr 30 04:24:41 PM PDT 24 Apr 30 04:36:07 PM PDT 24 3498380992 ps
T1069 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1970545155 Apr 30 04:43:58 PM PDT 24 Apr 30 04:47:55 PM PDT 24 2870543186 ps
T1070 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1634523737 Apr 30 04:45:43 PM PDT 24 Apr 30 05:21:12 PM PDT 24 12960837048 ps
T1071 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2295586467 Apr 30 04:51:09 PM PDT 24 Apr 30 04:58:36 PM PDT 24 5306067550 ps
T1072 /workspace/coverage/default/2.chip_sw_kmac_entropy.1123343626 Apr 30 04:40:55 PM PDT 24 Apr 30 04:44:58 PM PDT 24 2414088408 ps
T1073 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3439996794 Apr 30 04:44:15 PM PDT 24 Apr 30 04:47:49 PM PDT 24 2898402856 ps
T1074 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3159863260 Apr 30 04:23:10 PM PDT 24 Apr 30 04:35:32 PM PDT 24 9832145276 ps
T305 /workspace/coverage/default/2.chip_plic_all_irqs_20.3987997316 Apr 30 04:41:47 PM PDT 24 Apr 30 04:53:15 PM PDT 24 4284537980 ps
T253 /workspace/coverage/default/83.chip_sw_all_escalation_resets.4193715738 Apr 30 04:51:32 PM PDT 24 Apr 30 04:59:39 PM PDT 24 4926045864 ps
T1075 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2060817030 Apr 30 04:30:25 PM PDT 24 Apr 30 04:40:41 PM PDT 24 4550028250 ps
T1076 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.807962488 Apr 30 04:24:50 PM PDT 24 Apr 30 04:34:29 PM PDT 24 4532037736 ps
T1077 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2090256048 Apr 30 04:29:04 PM PDT 24 Apr 30 04:47:34 PM PDT 24 6150246200 ps
T319 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2818540537 Apr 30 04:23:09 PM PDT 24 Apr 30 04:41:30 PM PDT 24 4978828992 ps
T1078 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3983964194 Apr 30 04:27:53 PM PDT 24 Apr 30 04:35:43 PM PDT 24 3643093400 ps
T1079 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.576300848 Apr 30 04:23:47 PM PDT 24 Apr 30 04:33:37 PM PDT 24 4545091430 ps
T1080 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.802308501 Apr 30 04:37:25 PM PDT 24 Apr 30 04:47:44 PM PDT 24 5361014790 ps
T1081 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1861819245 Apr 30 04:45:41 PM PDT 24 Apr 30 04:54:16 PM PDT 24 5219067472 ps
T1082 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3690118122 Apr 30 04:22:49 PM PDT 24 Apr 30 04:33:34 PM PDT 24 4300755231 ps
T242 /workspace/coverage/default/1.chip_jtag_mem_access.2514283146 Apr 30 04:23:37 PM PDT 24 Apr 30 04:49:06 PM PDT 24 13804361069 ps
T741 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3184865632 Apr 30 04:50:53 PM PDT 24 Apr 30 04:56:56 PM PDT 24 3922733480 ps
T726 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3539261212 Apr 30 04:50:04 PM PDT 24 Apr 30 04:58:50 PM PDT 24 5201769368 ps
T338 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2688288726 Apr 30 04:25:15 PM PDT 24 Apr 30 04:29:13 PM PDT 24 2788453361 ps
T1083 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3106846138 Apr 30 04:36:27 PM PDT 24 Apr 30 05:00:29 PM PDT 24 8359706216 ps
T1084 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2152355208 Apr 30 04:42:41 PM PDT 24 Apr 30 04:50:50 PM PDT 24 3713579040 ps
T1085 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4053932469 Apr 30 04:23:57 PM PDT 24 Apr 30 05:14:42 PM PDT 24 20130305954 ps
T183 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2106642950 Apr 30 04:31:32 PM PDT 24 Apr 30 04:39:04 PM PDT 24 3709076460 ps
T1086 /workspace/coverage/default/0.chip_tap_straps_rma.2610281580 Apr 30 04:26:04 PM PDT 24 Apr 30 04:33:56 PM PDT 24 5985361546 ps
T688 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.355434184 Apr 30 04:49:54 PM PDT 24 Apr 30 04:55:27 PM PDT 24 4475640700 ps
T673 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2318392492 Apr 30 04:46:10 PM PDT 24 Apr 30 04:52:05 PM PDT 24 3316677862 ps
T320 /workspace/coverage/default/1.chip_plic_all_irqs_20.1760725339 Apr 30 04:33:17 PM PDT 24 Apr 30 04:44:45 PM PDT 24 4754461942 ps
T207 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.866493386 Apr 30 04:21:56 PM PDT 24 Apr 30 07:26:01 PM PDT 24 64182268169 ps
T681 /workspace/coverage/default/91.chip_sw_all_escalation_resets.979008823 Apr 30 04:51:33 PM PDT 24 Apr 30 05:00:24 PM PDT 24 4740000194 ps
T1087 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2641845849 Apr 30 04:34:07 PM PDT 24 Apr 30 04:37:47 PM PDT 24 2145446104 ps
T1088 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2749038354 Apr 30 04:51:08 PM PDT 24 Apr 30 05:01:50 PM PDT 24 4505612622 ps
T1089 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.368399376 Apr 30 04:37:25 PM PDT 24 Apr 30 04:56:20 PM PDT 24 6719318864 ps
T148 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.268502622 Apr 30 04:23:15 PM PDT 24 Apr 30 07:21:44 PM PDT 24 59300013260 ps
T1090 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.384500610 Apr 30 04:49:00 PM PDT 24 Apr 30 04:55:39 PM PDT 24 3750361600 ps
T1091 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1263129485 Apr 30 04:29:55 PM PDT 24 Apr 30 04:36:45 PM PDT 24 3590862130 ps
T1092 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.378994771 Apr 30 04:39:35 PM PDT 24 Apr 30 04:45:35 PM PDT 24 3435486800 ps
T354 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3205915333 Apr 30 04:51:04 PM PDT 24 Apr 30 05:01:42 PM PDT 24 5448097072 ps
T1093 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3271872604 Apr 30 04:27:10 PM PDT 24 Apr 30 04:29:59 PM PDT 24 2293979744 ps
T1094 /workspace/coverage/default/2.chip_sw_flash_init.3158140331 Apr 30 04:37:20 PM PDT 24 Apr 30 05:12:09 PM PDT 24 18484171751 ps
T1095 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2514953677 Apr 30 04:52:18 PM PDT 24 Apr 30 05:01:48 PM PDT 24 4722680720 ps
T682 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1028583471 Apr 30 04:49:39 PM PDT 24 Apr 30 04:59:37 PM PDT 24 5331120720 ps
T1096 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2296445978 Apr 30 04:25:11 PM PDT 24 Apr 30 04:32:48 PM PDT 24 5471889208 ps
T1097 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3939539602 Apr 30 04:45:14 PM PDT 24 Apr 30 04:53:21 PM PDT 24 3770739650 ps
T254 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4068060324 Apr 30 04:24:57 PM PDT 24 Apr 30 04:34:18 PM PDT 24 5509728878 ps
T1098 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1800323237 Apr 30 04:38:17 PM PDT 24 Apr 30 04:46:36 PM PDT 24 4768518040 ps
T1099 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4080876308 Apr 30 04:50:20 PM PDT 24 Apr 30 04:55:56 PM PDT 24 3820035240 ps
T1100 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756295982 Apr 30 04:49:45 PM PDT 24 Apr 30 04:55:37 PM PDT 24 3016258750 ps
T1101 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2605827064 Apr 30 04:22:14 PM PDT 24 Apr 30 05:08:32 PM PDT 24 12815879884 ps
T1102 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1449715454 Apr 30 04:50:51 PM PDT 24 Apr 30 04:57:30 PM PDT 24 4412134576 ps
T612 /workspace/coverage/default/4.chip_tap_straps_dev.643992742 Apr 30 04:44:34 PM PDT 24 Apr 30 04:57:35 PM PDT 24 8801803905 ps
T701 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3651097340 Apr 30 04:47:47 PM PDT 24 Apr 30 04:52:44 PM PDT 24 3851077500 ps
T628 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2488218726 Apr 30 04:42:38 PM PDT 24 Apr 30 04:46:42 PM PDT 24 2533553640 ps
T26 /workspace/coverage/default/1.chip_sw_gpio.1871887869 Apr 30 04:30:27 PM PDT 24 Apr 30 04:40:45 PM PDT 24 4058782786 ps
T728 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2800500486 Apr 30 04:51:27 PM PDT 24 Apr 30 04:59:33 PM PDT 24 5529845124 ps
T1103 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1661607854 Apr 30 04:33:01 PM PDT 24 Apr 30 04:44:17 PM PDT 24 5041122296 ps
T692 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1300309873 Apr 30 04:47:06 PM PDT 24 Apr 30 04:59:54 PM PDT 24 5701321940 ps
T689 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767976984 Apr 30 04:50:34 PM PDT 24 Apr 30 04:57:27 PM PDT 24 3895475960 ps
T1104 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1228694107 Apr 30 04:46:09 PM PDT 24 Apr 30 05:07:11 PM PDT 24 8514638820 ps
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