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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 95.29 93.71 95.58 94.38 97.38 99.53


Total test records in report: 2788
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T865 /workspace/coverage/default/2.chip_sw_otbn_smoketest.36504841 May 02 04:59:53 PM PDT 24 May 02 05:28:40 PM PDT 24 9921872156 ps
T11 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.469189425 May 02 04:51:52 PM PDT 24 May 02 05:01:17 PM PDT 24 4418211995 ps
T309 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.814776601 May 02 05:00:26 PM PDT 24 May 02 05:09:30 PM PDT 24 3796634164 ps
T325 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2394719884 May 02 04:46:42 PM PDT 24 May 02 05:18:51 PM PDT 24 23043676360 ps
T866 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2673677776 May 02 04:59:54 PM PDT 24 May 02 05:05:31 PM PDT 24 2541073986 ps
T323 /workspace/coverage/default/11.chip_sw_all_escalation_resets.303367472 May 02 05:00:53 PM PDT 24 May 02 05:12:50 PM PDT 24 5412400996 ps
T736 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.727124215 May 02 05:05:27 PM PDT 24 May 02 05:10:46 PM PDT 24 3704869808 ps
T113 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4030417572 May 02 04:59:54 PM PDT 24 May 02 05:27:07 PM PDT 24 12166211751 ps
T288 /workspace/coverage/default/1.chip_plic_all_irqs_20.2798405728 May 02 04:49:48 PM PDT 24 May 02 05:00:27 PM PDT 24 3980861888 ps
T867 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3826386142 May 02 04:51:18 PM PDT 24 May 02 04:55:27 PM PDT 24 2523548080 ps
T733 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2130447689 May 02 05:05:08 PM PDT 24 May 02 05:11:17 PM PDT 24 3639964310 ps
T868 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1104289023 May 02 04:48:53 PM PDT 24 May 02 04:59:32 PM PDT 24 4568752460 ps
T136 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2668959125 May 02 05:00:16 PM PDT 24 May 02 05:41:03 PM PDT 24 18327977105 ps
T869 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4151323016 May 02 05:01:48 PM PDT 24 May 02 05:22:11 PM PDT 24 7891737762 ps
T870 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2304007367 May 02 04:42:10 PM PDT 24 May 02 04:53:35 PM PDT 24 4813774040 ps
T871 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2231542244 May 02 04:41:01 PM PDT 24 May 02 04:47:50 PM PDT 24 3684717194 ps
T22 /workspace/coverage/default/0.chip_sw_usbdev_dpi.4138133647 May 02 04:40:15 PM PDT 24 May 02 05:27:14 PM PDT 24 11897395692 ps
T400 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1179469502 May 02 04:44:19 PM PDT 24 May 02 04:49:36 PM PDT 24 3177915180 ps
T207 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2784634351 May 02 04:49:11 PM PDT 24 May 02 05:24:17 PM PDT 24 16864610027 ps
T755 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1810421555 May 02 05:05:48 PM PDT 24 May 02 05:12:38 PM PDT 24 3758096066 ps
T739 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040374673 May 02 05:00:09 PM PDT 24 May 02 05:08:00 PM PDT 24 4287672620 ps
T872 /workspace/coverage/default/1.chip_sw_example_flash.2303646463 May 02 04:44:21 PM PDT 24 May 02 04:48:33 PM PDT 24 3366186796 ps
T276 /workspace/coverage/default/90.chip_sw_all_escalation_resets.150312546 May 02 05:08:03 PM PDT 24 May 02 05:18:13 PM PDT 24 5390225176 ps
T278 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3934225488 May 02 04:47:34 PM PDT 24 May 02 04:55:00 PM PDT 24 6863137810 ps
T279 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096505363 May 02 05:08:21 PM PDT 24 May 02 05:13:39 PM PDT 24 4355064256 ps
T280 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032600891 May 02 05:06:47 PM PDT 24 May 02 05:11:49 PM PDT 24 3579814630 ps
T281 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.4083401672 May 02 04:44:59 PM PDT 24 May 02 05:00:33 PM PDT 24 6434745781 ps
T282 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2918246829 May 02 04:41:10 PM PDT 24 May 02 04:52:48 PM PDT 24 4152213924 ps
T283 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.152195504 May 02 04:43:01 PM PDT 24 May 02 04:47:47 PM PDT 24 3466911457 ps
T284 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3956095441 May 02 05:01:55 PM PDT 24 May 02 05:08:26 PM PDT 24 4022533080 ps
T200 /workspace/coverage/default/30.chip_sw_all_escalation_resets.247003638 May 02 05:05:03 PM PDT 24 May 02 05:13:22 PM PDT 24 4845643650 ps
T285 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.462260115 May 02 04:39:55 PM PDT 24 May 02 05:01:28 PM PDT 24 8737209364 ps
T873 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.17370112 May 02 05:01:47 PM PDT 24 May 02 05:14:55 PM PDT 24 11238742296 ps
T874 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.863874173 May 02 04:44:33 PM PDT 24 May 02 05:36:08 PM PDT 24 14615596050 ps
T219 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2292505478 May 02 04:55:34 PM PDT 24 May 02 05:22:40 PM PDT 24 14224058778 ps
T875 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.967719773 May 02 04:54:22 PM PDT 24 May 02 05:10:26 PM PDT 24 12787856493 ps
T103 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.929401910 May 02 04:59:36 PM PDT 24 May 02 05:24:13 PM PDT 24 23560272952 ps
T308 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.301418681 May 02 05:00:47 PM PDT 24 May 02 05:10:57 PM PDT 24 3779618494 ps
T169 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3487099893 May 02 04:53:20 PM PDT 24 May 02 06:09:30 PM PDT 24 43941627324 ps
T876 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1836811508 May 02 04:57:37 PM PDT 24 May 02 05:10:55 PM PDT 24 5033291972 ps
T877 /workspace/coverage/default/1.chip_sw_aes_idle.340967007 May 02 04:49:51 PM PDT 24 May 02 04:54:10 PM PDT 24 2857145254 ps
T878 /workspace/coverage/default/2.chip_tap_straps_prod.820461758 May 02 04:57:58 PM PDT 24 May 02 05:10:29 PM PDT 24 8528767125 ps
T623 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3542664611 May 02 04:55:56 PM PDT 24 May 02 05:00:46 PM PDT 24 2894812700 ps
T229 /workspace/coverage/default/2.chip_sw_plic_sw_irq.471456247 May 02 04:58:32 PM PDT 24 May 02 05:02:41 PM PDT 24 3070695852 ps
T292 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1164978029 May 02 04:40:28 PM PDT 24 May 02 04:51:30 PM PDT 24 3994440550 ps
T686 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.403916358 May 02 05:06:12 PM PDT 24 May 02 05:12:44 PM PDT 24 3905384632 ps
T879 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2105271227 May 02 05:02:30 PM PDT 24 May 02 05:39:26 PM PDT 24 12948690962 ps
T39 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2185976237 May 02 04:42:42 PM PDT 24 May 02 04:50:18 PM PDT 24 3583524459 ps
T880 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2728248543 May 02 04:58:35 PM PDT 24 May 02 05:07:36 PM PDT 24 5721520566 ps
T600 /workspace/coverage/default/2.chip_sw_edn_boot_mode.4083316640 May 02 04:59:06 PM PDT 24 May 02 05:07:26 PM PDT 24 3403392396 ps
T881 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.915742041 May 02 04:44:28 PM PDT 24 May 02 04:48:43 PM PDT 24 2311188586 ps
T620 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3054774632 May 02 04:54:40 PM PDT 24 May 02 05:08:19 PM PDT 24 5267057592 ps
T684 /workspace/coverage/default/0.chip_sw_edn_kat.818778506 May 02 04:42:47 PM PDT 24 May 02 04:52:36 PM PDT 24 3577856448 ps
T160 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3771065316 May 02 04:58:00 PM PDT 24 May 02 05:09:08 PM PDT 24 4695570310 ps
T716 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1590870505 May 02 05:05:28 PM PDT 24 May 02 05:11:51 PM PDT 24 3295370848 ps
T882 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.565003335 May 02 04:48:26 PM PDT 24 May 02 05:21:20 PM PDT 24 10476564470 ps
T883 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2910512554 May 02 04:52:26 PM PDT 24 May 02 05:02:29 PM PDT 24 3596646762 ps
T161 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2501844038 May 02 04:49:30 PM PDT 24 May 02 04:59:33 PM PDT 24 5528930161 ps
T129 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.511435509 May 02 05:01:24 PM PDT 24 May 02 05:18:36 PM PDT 24 6926455160 ps
T884 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3639130515 May 02 04:43:26 PM PDT 24 May 02 04:48:40 PM PDT 24 2636805992 ps
T86 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1945522877 May 02 04:52:08 PM PDT 24 May 02 04:56:02 PM PDT 24 2628490004 ps
T319 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2585189217 May 02 04:58:56 PM PDT 24 May 02 05:05:04 PM PDT 24 3544682140 ps
T315 /workspace/coverage/default/2.chip_sival_flash_info_access.752908808 May 02 04:52:42 PM PDT 24 May 02 04:56:57 PM PDT 24 2516868176 ps
T885 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1911665408 May 02 04:58:02 PM PDT 24 May 02 05:07:51 PM PDT 24 4129839568 ps
T886 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2135163099 May 02 04:57:31 PM PDT 24 May 02 05:07:41 PM PDT 24 6261266748 ps
T33 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.453063072 May 02 04:41:53 PM PDT 24 May 02 04:47:06 PM PDT 24 3157512216 ps
T152 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2648128863 May 02 04:53:58 PM PDT 24 May 02 04:57:42 PM PDT 24 3184134256 ps
T744 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771405532 May 02 05:07:22 PM PDT 24 May 02 05:13:09 PM PDT 24 3669376272 ps
T887 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.983540881 May 02 04:42:45 PM PDT 24 May 02 04:54:24 PM PDT 24 4284288920 ps
T888 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1246164790 May 02 04:41:43 PM PDT 24 May 02 04:53:56 PM PDT 24 6084586820 ps
T622 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.52011595 May 02 04:40:26 PM PDT 24 May 02 04:45:20 PM PDT 24 3520290680 ps
T77 /workspace/coverage/default/0.chip_jtag_mem_access.4126368472 May 02 04:33:35 PM PDT 24 May 02 04:54:22 PM PDT 24 13624672079 ps
T130 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2382894347 May 02 04:47:04 PM PDT 24 May 02 05:05:26 PM PDT 24 7974587456 ps
T341 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3649554 May 02 05:08:03 PM PDT 24 May 02 05:14:29 PM PDT 24 4086645110 ps
T889 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3359033287 May 02 04:57:39 PM PDT 24 May 02 05:01:19 PM PDT 24 2637712406 ps
T890 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3969868039 May 02 04:48:16 PM PDT 24 May 02 05:00:42 PM PDT 24 4683604552 ps
T342 /workspace/coverage/default/52.chip_sw_all_escalation_resets.4178144833 May 02 05:04:08 PM PDT 24 May 02 05:12:05 PM PDT 24 5178933294 ps
T721 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1447213731 May 02 05:05:11 PM PDT 24 May 02 05:14:00 PM PDT 24 3988928204 ps
T891 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.664479817 May 02 04:49:16 PM PDT 24 May 02 04:59:18 PM PDT 24 3530989400 ps
T892 /workspace/coverage/default/1.chip_sw_aes_smoketest.299530050 May 02 04:50:29 PM PDT 24 May 02 04:54:18 PM PDT 24 2962819512 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2386859363 May 02 04:41:22 PM PDT 24 May 02 04:46:49 PM PDT 24 3017150212 ps
T220 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3148248834 May 02 04:41:48 PM PDT 24 May 02 05:10:07 PM PDT 24 13288272440 ps
T679 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.545003442 May 02 05:04:24 PM PDT 24 May 02 05:11:10 PM PDT 24 3840405848 ps
T893 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2696288627 May 02 04:48:00 PM PDT 24 May 02 05:40:34 PM PDT 24 17222635000 ps
T894 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1265949967 May 02 04:43:48 PM PDT 24 May 02 04:47:51 PM PDT 24 2772571382 ps
T895 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3506704848 May 02 04:48:53 PM PDT 24 May 02 04:59:28 PM PDT 24 5305978130 ps
T896 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3575338285 May 02 04:54:41 PM PDT 24 May 02 05:12:50 PM PDT 24 5459092488 ps
T897 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3832298681 May 02 04:55:00 PM PDT 24 May 02 05:07:03 PM PDT 24 7676190592 ps
T898 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.313997532 May 02 04:52:40 PM PDT 24 May 02 05:10:21 PM PDT 24 5773014610 ps
T402 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.605744841 May 02 04:59:28 PM PDT 24 May 02 05:14:10 PM PDT 24 4145175598 ps
T65 /workspace/coverage/default/3.chip_tap_straps_testunlock0.536458346 May 02 04:58:59 PM PDT 24 May 02 05:05:00 PM PDT 24 4883763527 ps
T237 /workspace/coverage/default/51.chip_sw_all_escalation_resets.340936382 May 02 05:05:41 PM PDT 24 May 02 05:17:45 PM PDT 24 6497703400 ps
T899 /workspace/coverage/default/1.rom_keymgr_functest.160835463 May 02 04:50:25 PM PDT 24 May 02 04:58:03 PM PDT 24 4917749294 ps
T677 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.257054883 May 02 05:07:02 PM PDT 24 May 02 05:13:26 PM PDT 24 4064296144 ps
T900 /workspace/coverage/default/3.chip_sw_uart_tx_rx.98704237 May 02 05:05:27 PM PDT 24 May 02 05:15:27 PM PDT 24 3512403000 ps
T901 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3073666223 May 02 04:57:57 PM PDT 24 May 02 05:09:37 PM PDT 24 4604715592 ps
T902 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1988057094 May 02 04:45:40 PM PDT 24 May 02 04:49:38 PM PDT 24 2881558180 ps
T681 /workspace/coverage/default/24.chip_sw_all_escalation_resets.4069824061 May 02 05:03:09 PM PDT 24 May 02 05:15:30 PM PDT 24 5211751160 ps
T21 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2469960745 May 02 04:55:34 PM PDT 24 May 02 05:24:17 PM PDT 24 24658979144 ps
T903 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.515151854 May 02 04:59:10 PM PDT 24 May 02 05:02:31 PM PDT 24 2519247754 ps
T904 /workspace/coverage/default/2.chip_tap_straps_dev.576821388 May 02 05:00:49 PM PDT 24 May 02 05:36:26 PM PDT 24 19267348735 ps
T905 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2375407957 May 02 04:49:33 PM PDT 24 May 02 04:56:02 PM PDT 24 3977363896 ps
T906 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4257618119 May 02 04:59:47 PM PDT 24 May 02 05:06:36 PM PDT 24 5588298084 ps
T907 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4194329226 May 02 05:01:17 PM PDT 24 May 02 05:06:44 PM PDT 24 6776116006 ps
T908 /workspace/coverage/default/1.chip_sw_aes_entropy.960856268 May 02 04:50:11 PM PDT 24 May 02 04:54:55 PM PDT 24 3249242040 ps
T49 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2094866442 May 02 04:40:32 PM PDT 24 May 02 04:46:56 PM PDT 24 4138622856 ps
T698 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.755619127 May 02 05:03:45 PM PDT 24 May 02 05:10:24 PM PDT 24 3775712148 ps
T296 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1454963087 May 02 04:52:56 PM PDT 24 May 02 05:05:39 PM PDT 24 5267331342 ps
T609 /workspace/coverage/default/2.chip_sw_power_sleep_load.3121217406 May 02 04:59:04 PM PDT 24 May 02 05:04:38 PM PDT 24 4321466930 ps
T727 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4230976397 May 02 05:08:08 PM PDT 24 May 02 05:13:57 PM PDT 24 4025448550 ps
T305 /workspace/coverage/default/0.chip_sw_pattgen_ios.4222008323 May 02 04:41:35 PM PDT 24 May 02 04:46:37 PM PDT 24 3082588744 ps
T909 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3776375969 May 02 04:48:27 PM PDT 24 May 02 05:18:10 PM PDT 24 22093129296 ps
T910 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2595524100 May 02 04:41:56 PM PDT 24 May 02 04:54:04 PM PDT 24 9243043660 ps
T911 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2339033636 May 02 04:47:36 PM PDT 24 May 02 04:56:28 PM PDT 24 5877048694 ps
T912 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.109077522 May 02 04:53:28 PM PDT 24 May 02 05:08:46 PM PDT 24 9026061200 ps
T666 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3554919450 May 02 04:42:41 PM PDT 24 May 02 04:54:18 PM PDT 24 4866155178 ps
T186 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1951465714 May 02 04:44:27 PM PDT 24 May 02 07:45:03 PM PDT 24 65183234753 ps
T913 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1752790161 May 02 04:41:43 PM PDT 24 May 02 04:47:48 PM PDT 24 4003761246 ps
T162 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2355061177 May 02 04:47:16 PM PDT 24 May 02 04:59:41 PM PDT 24 5024517178 ps
T176 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1821170196 May 02 04:40:17 PM PDT 24 May 02 04:52:03 PM PDT 24 6312942075 ps
T273 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2515532091 May 02 04:58:36 PM PDT 24 May 02 05:13:27 PM PDT 24 9392602703 ps
T914 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3684702975 May 02 04:39:58 PM PDT 24 May 02 04:48:02 PM PDT 24 3937199457 ps
T915 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1345722643 May 02 04:50:20 PM PDT 24 May 02 05:02:16 PM PDT 24 4218448650 ps
T916 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2197557595 May 02 04:46:32 PM PDT 24 May 02 05:03:10 PM PDT 24 6152067418 ps
T34 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4052531269 May 02 04:51:40 PM PDT 24 May 02 04:56:46 PM PDT 24 3151201640 ps
T670 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2667805866 May 02 05:03:45 PM PDT 24 May 02 05:15:35 PM PDT 24 5679430800 ps
T216 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2481037120 May 02 04:54:13 PM PDT 24 May 02 05:05:29 PM PDT 24 6063984360 ps
T917 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2685264625 May 02 04:58:17 PM PDT 24 May 02 05:06:11 PM PDT 24 5096226150 ps
T918 /workspace/coverage/default/2.chip_tap_straps_rma.2194221843 May 02 04:59:13 PM PDT 24 May 02 05:05:53 PM PDT 24 4503139255 ps
T198 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1879026936 May 02 04:50:30 PM PDT 24 May 02 04:57:06 PM PDT 24 5059412323 ps
T473 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2831219551 May 02 04:41:59 PM PDT 24 May 02 05:10:34 PM PDT 24 11364224681 ps
T919 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1168701180 May 02 04:40:15 PM PDT 24 May 02 04:44:25 PM PDT 24 2851365000 ps
T706 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3245133334 May 02 05:02:31 PM PDT 24 May 02 05:10:48 PM PDT 24 4086634440 ps
T211 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2797620933 May 02 04:45:00 PM PDT 24 May 02 06:14:11 PM PDT 24 48585588553 ps
T920 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.168731438 May 02 04:50:33 PM PDT 24 May 02 05:13:14 PM PDT 24 11876581480 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.242233655 May 02 04:42:02 PM PDT 24 May 02 04:51:48 PM PDT 24 4654871646 ps
T921 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.817967789 May 02 04:54:40 PM PDT 24 May 02 05:11:55 PM PDT 24 7543093975 ps
T922 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3718491297 May 02 04:41:36 PM PDT 24 May 02 04:54:02 PM PDT 24 3649816340 ps
T298 /workspace/coverage/default/2.chip_plic_all_irqs_20.359596251 May 02 04:58:17 PM PDT 24 May 02 05:10:25 PM PDT 24 4427845488 ps
T923 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2278964764 May 02 04:59:52 PM PDT 24 May 02 05:03:34 PM PDT 24 2804671000 ps
T924 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1131702438 May 02 05:02:05 PM PDT 24 May 02 05:07:48 PM PDT 24 6725650600 ps
T347 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4112355863 May 02 04:48:31 PM PDT 24 May 02 05:11:04 PM PDT 24 6763537880 ps
T925 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2125464712 May 02 05:02:51 PM PDT 24 May 02 05:16:54 PM PDT 24 9354020922 ps
T728 /workspace/coverage/default/45.chip_sw_all_escalation_resets.184685111 May 02 05:04:44 PM PDT 24 May 02 05:14:47 PM PDT 24 4403401272 ps
T260 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3846299658 May 02 04:57:31 PM PDT 24 May 02 05:06:30 PM PDT 24 4699318666 ps
T125 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3306987509 May 02 04:48:38 PM PDT 24 May 02 04:56:46 PM PDT 24 5470765688 ps
T740 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.214468702 May 02 05:05:52 PM PDT 24 May 02 05:10:42 PM PDT 24 3348449200 ps
T138 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1748022266 May 02 04:57:16 PM PDT 24 May 02 05:02:22 PM PDT 24 2577138515 ps
T926 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4079121318 May 02 05:01:21 PM PDT 24 May 02 05:23:20 PM PDT 24 8077700654 ps
T328 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.315507669 May 02 04:52:03 PM PDT 24 May 02 05:03:36 PM PDT 24 4020830278 ps
T927 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.4123517409 May 02 04:48:32 PM PDT 24 May 02 04:53:25 PM PDT 24 2388285208 ps
T688 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287554970 May 02 05:03:02 PM PDT 24 May 02 05:08:08 PM PDT 24 3415464908 ps
T928 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.63139308 May 02 04:59:31 PM PDT 24 May 02 05:07:57 PM PDT 24 4074939068 ps
T345 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2897901007 May 02 04:47:19 PM PDT 24 May 02 04:52:33 PM PDT 24 3155106254 ps
T642 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3373385192 May 02 04:41:50 PM PDT 24 May 02 05:06:07 PM PDT 24 21603985792 ps
T89 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1438129998 May 02 05:07:02 PM PDT 24 May 02 05:17:44 PM PDT 24 4985688244 ps
T929 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4009596692 May 02 04:59:01 PM PDT 24 May 02 05:10:13 PM PDT 24 4352263560 ps
T674 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3897792349 May 02 05:07:22 PM PDT 24 May 02 05:19:01 PM PDT 24 5527170080 ps
T930 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2063857743 May 02 04:51:04 PM PDT 24 May 02 04:59:24 PM PDT 24 5633646992 ps
T680 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3269174959 May 02 05:05:47 PM PDT 24 May 02 05:13:44 PM PDT 24 4932913240 ps
T931 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2899564783 May 02 04:54:15 PM PDT 24 May 02 04:59:35 PM PDT 24 2749766375 ps
T932 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3186970574 May 02 04:47:03 PM PDT 24 May 02 04:53:48 PM PDT 24 5511402970 ps
T933 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2544534926 May 02 04:42:08 PM PDT 24 May 02 05:06:40 PM PDT 24 8582413970 ps
T934 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3606345113 May 02 04:52:34 PM PDT 24 May 02 05:02:58 PM PDT 24 7035679306 ps
T397 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3173112841 May 02 04:44:12 PM PDT 24 May 02 04:47:40 PM PDT 24 2554389046 ps
T730 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2077281050 May 02 05:08:42 PM PDT 24 May 02 05:15:49 PM PDT 24 4729319596 ps
T78 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1182553296 May 02 04:43:40 PM PDT 24 May 02 07:22:37 PM PDT 24 58918217640 ps
T935 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2168334004 May 02 04:39:40 PM PDT 24 May 02 04:59:55 PM PDT 24 8664025650 ps
T299 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2878192891 May 02 04:59:43 PM PDT 24 May 02 05:26:19 PM PDT 24 7435757360 ps
T630 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2786776062 May 02 04:52:05 PM PDT 24 May 02 05:16:17 PM PDT 24 8544750840 ps
T936 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2180351710 May 02 04:50:19 PM PDT 24 May 02 05:00:12 PM PDT 24 4232371492 ps
T54 /workspace/coverage/default/2.chip_jtag_csr_rw.62665555 May 02 04:50:12 PM PDT 24 May 02 05:24:29 PM PDT 24 17134317916 ps
T300 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4127856894 May 02 04:40:25 PM PDT 24 May 02 05:05:52 PM PDT 24 6250025790 ps
T937 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4171715624 May 02 05:01:29 PM PDT 24 May 02 05:06:27 PM PDT 24 2929200593 ps
T938 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.527815405 May 02 04:58:56 PM PDT 24 May 02 05:08:23 PM PDT 24 4827540056 ps
T25 /workspace/coverage/default/1.chip_sw_gpio.3254231385 May 02 04:44:15 PM PDT 24 May 02 04:52:53 PM PDT 24 4337060617 ps
T139 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3747346376 May 02 04:40:54 PM PDT 24 May 02 04:50:32 PM PDT 24 9443103036 ps
T747 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3031610787 May 02 05:07:09 PM PDT 24 May 02 05:16:16 PM PDT 24 5753827926 ps
T939 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1010712652 May 02 05:01:13 PM PDT 24 May 02 05:08:45 PM PDT 24 4656121227 ps
T708 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.370885434 May 02 05:06:28 PM PDT 24 May 02 05:13:32 PM PDT 24 3960811192 ps
T940 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1073789660 May 02 04:55:13 PM PDT 24 May 02 05:18:54 PM PDT 24 12228255852 ps
T47 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.342376065 May 02 04:44:51 PM PDT 24 May 02 05:11:57 PM PDT 24 18149540736 ps
T941 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.614391130 May 02 04:42:46 PM PDT 24 May 02 04:47:13 PM PDT 24 3159748712 ps
T217 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1040001582 May 02 05:06:25 PM PDT 24 May 02 05:16:37 PM PDT 24 6233829788 ps
T210 /workspace/coverage/default/2.chip_sw_flash_init.562914659 May 02 04:52:57 PM PDT 24 May 02 05:25:10 PM PDT 24 19261427872 ps
T7 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3782922834 May 02 04:44:52 PM PDT 24 May 02 04:49:12 PM PDT 24 3244540556 ps
T678 /workspace/coverage/default/98.chip_sw_all_escalation_resets.160780885 May 02 05:07:39 PM PDT 24 May 02 05:17:18 PM PDT 24 4129002168 ps
T212 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4190155275 May 02 04:40:46 PM PDT 24 May 02 06:14:06 PM PDT 24 50412009375 ps
T594 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1614077115 May 02 04:43:26 PM PDT 24 May 02 05:42:19 PM PDT 24 24917816400 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3602993996 May 02 04:56:15 PM PDT 24 May 02 05:03:56 PM PDT 24 5369060536 ps
T942 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3872261532 May 02 05:01:06 PM PDT 24 May 02 05:12:08 PM PDT 24 4336236492 ps
T667 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750236291 May 02 05:05:49 PM PDT 24 May 02 05:11:41 PM PDT 24 4392499292 ps
T943 /workspace/coverage/default/1.chip_sw_example_concurrency.3658908563 May 02 04:44:44 PM PDT 24 May 02 04:48:18 PM PDT 24 2785079640 ps
T291 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.260874484 May 02 04:42:31 PM PDT 24 May 02 04:56:41 PM PDT 24 4949628504 ps
T944 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2962278522 May 02 04:59:47 PM PDT 24 May 02 05:06:02 PM PDT 24 2875494246 ps
T945 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.585234904 May 02 04:42:42 PM PDT 24 May 02 04:53:13 PM PDT 24 4852925016 ps
T8 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2934535101 May 02 04:39:47 PM PDT 24 May 02 04:46:04 PM PDT 24 3097145386 ps
T946 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.281948559 May 02 04:53:04 PM PDT 24 May 02 05:05:13 PM PDT 24 4262886614 ps
T947 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2637867553 May 02 04:41:51 PM PDT 24 May 02 05:15:36 PM PDT 24 26105993330 ps
T233 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.278967714 May 02 04:58:36 PM PDT 24 May 02 05:06:36 PM PDT 24 5214152558 ps
T676 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.321125574 May 02 04:50:45 PM PDT 24 May 02 05:06:57 PM PDT 24 6862648210 ps
T301 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4293922353 May 02 04:41:35 PM PDT 24 May 02 04:57:49 PM PDT 24 5370082370 ps
T948 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2753802279 May 02 04:51:42 PM PDT 24 May 02 04:58:09 PM PDT 24 5904906120 ps
T949 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1067994049 May 02 04:54:23 PM PDT 24 May 02 05:19:38 PM PDT 24 16274339562 ps
T950 /workspace/coverage/default/0.chip_sw_example_manufacturer.663568443 May 02 04:45:49 PM PDT 24 May 02 04:50:14 PM PDT 24 2998433606 ps
T79 /workspace/coverage/default/1.chip_jtag_csr_rw.4026607111 May 02 04:40:34 PM PDT 24 May 02 04:58:13 PM PDT 24 10879417190 ps
T745 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1378341507 May 02 05:05:40 PM PDT 24 May 02 05:10:54 PM PDT 24 3590857480 ps
T672 /workspace/coverage/default/59.chip_sw_all_escalation_resets.684262154 May 02 05:06:26 PM PDT 24 May 02 05:15:18 PM PDT 24 5581956176 ps
T329 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1972205238 May 02 04:45:04 PM PDT 24 May 02 04:49:08 PM PDT 24 3126167629 ps
T951 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2070830771 May 02 04:54:19 PM PDT 24 May 02 05:00:14 PM PDT 24 3230580818 ps
T90 /workspace/coverage/default/28.chip_sw_all_escalation_resets.726937036 May 02 05:02:34 PM PDT 24 May 02 05:14:52 PM PDT 24 4341088936 ps
T277 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2590021355 May 02 05:08:02 PM PDT 24 May 02 05:14:55 PM PDT 24 3514069340 ps
T302 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2915060974 May 02 04:43:52 PM PDT 24 May 02 04:56:31 PM PDT 24 4528195664 ps
T289 /workspace/coverage/default/2.chip_plic_all_irqs_0.272835259 May 02 04:57:13 PM PDT 24 May 02 05:17:18 PM PDT 24 6139209836 ps
T952 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2892179752 May 02 05:04:11 PM PDT 24 May 02 05:14:53 PM PDT 24 4374208570 ps
T707 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1400824577 May 02 05:08:17 PM PDT 24 May 02 05:16:18 PM PDT 24 5669249030 ps
T953 /workspace/coverage/default/0.chip_sw_uart_smoketest.1276841889 May 02 04:46:13 PM PDT 24 May 02 04:51:12 PM PDT 24 2703832422 ps
T149 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.383579655 May 02 04:56:06 PM PDT 24 May 02 08:02:05 PM PDT 24 256028896308 ps
T954 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.477074438 May 02 04:58:11 PM PDT 24 May 02 05:09:06 PM PDT 24 3620157896 ps
T752 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3190901390 May 02 05:06:00 PM PDT 24 May 02 05:14:49 PM PDT 24 5204089554 ps
T703 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.484054717 May 02 05:07:08 PM PDT 24 May 02 05:12:49 PM PDT 24 4284449232 ps
T955 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3662111591 May 02 04:47:18 PM PDT 24 May 02 04:50:41 PM PDT 24 2932997480 ps
T225 /workspace/coverage/default/2.chip_jtag_mem_access.26821099 May 02 04:50:18 PM PDT 24 May 02 05:13:58 PM PDT 24 13495780360 ps
T699 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2497791954 May 02 05:07:24 PM PDT 24 May 02 05:16:30 PM PDT 24 5027880400 ps
T956 /workspace/coverage/default/2.chip_sw_uart_smoketest.3219443115 May 02 04:59:34 PM PDT 24 May 02 05:03:40 PM PDT 24 3442939600 ps
T957 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1275364710 May 02 04:55:20 PM PDT 24 May 02 05:44:34 PM PDT 24 19141822533 ps
T958 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2991529642 May 02 05:02:15 PM PDT 24 May 02 05:44:19 PM PDT 24 12921986808 ps
T959 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3170349256 May 02 05:00:12 PM PDT 24 May 02 05:03:48 PM PDT 24 2476563408 ps
T960 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4145724275 May 02 05:00:38 PM PDT 24 May 02 05:07:28 PM PDT 24 2767585976 ps
T403 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2106850484 May 02 04:42:44 PM PDT 24 May 02 05:03:48 PM PDT 24 5178756650 ps
T961 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3648709640 May 02 04:45:52 PM PDT 24 May 02 05:00:53 PM PDT 24 8052727948 ps
T85 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.617050937 May 02 04:46:21 PM PDT 24 May 02 04:51:04 PM PDT 24 3018195086 ps
T962 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4198183693 May 02 04:48:57 PM PDT 24 May 02 04:54:15 PM PDT 24 2893896882 ps
T963 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3477263950 May 02 05:01:41 PM PDT 24 May 02 05:23:54 PM PDT 24 7777305288 ps
T964 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1167936774 May 02 04:48:25 PM PDT 24 May 02 04:58:55 PM PDT 24 4050388872 ps
T668 /workspace/coverage/default/3.chip_sw_all_escalation_resets.844883293 May 02 05:06:08 PM PDT 24 May 02 05:14:31 PM PDT 24 6059568720 ps
T965 /workspace/coverage/default/3.chip_tap_straps_prod.1175161744 May 02 04:59:52 PM PDT 24 May 02 05:02:41 PM PDT 24 2767839052 ps
T104 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2345312877 May 02 04:48:29 PM PDT 24 May 02 05:13:00 PM PDT 24 17421096152 ps
T669 /workspace/coverage/default/2.chip_sw_all_escalation_resets.4176740578 May 02 04:54:42 PM PDT 24 May 02 05:05:42 PM PDT 24 5855524256 ps
T966 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2671487396 May 02 04:42:55 PM PDT 24 May 02 04:55:27 PM PDT 24 5023492202 ps
T967 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3010552960 May 02 04:53:14 PM PDT 24 May 02 05:04:59 PM PDT 24 3996520880 ps
T610 /workspace/coverage/default/2.chip_sw_power_idle_load.3588782 May 02 04:59:31 PM PDT 24 May 02 05:09:22 PM PDT 24 4118557008 ps
T968 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2421547082 May 02 05:01:17 PM PDT 24 May 02 05:11:10 PM PDT 24 4295320890 ps
T705 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3444281977 May 02 05:07:54 PM PDT 24 May 02 05:15:45 PM PDT 24 4709669720 ps
T729 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2970683336 May 02 05:05:33 PM PDT 24 May 02 05:16:40 PM PDT 24 6145717400 ps
T969 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.591352321 May 02 04:41:39 PM PDT 24 May 02 05:00:36 PM PDT 24 6519602616 ps
T172 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3805771368 May 02 04:47:07 PM PDT 24 May 02 04:50:36 PM PDT 24 2874240072 ps
T154 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2983861655 May 02 04:47:04 PM PDT 24 May 02 04:48:42 PM PDT 24 2021376041 ps
T970 /workspace/coverage/default/0.chip_sw_aes_entropy.2301672094 May 02 04:41:25 PM PDT 24 May 02 04:45:13 PM PDT 24 2934546288 ps
T197 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2256648562 May 02 04:51:55 PM PDT 24 May 02 05:12:55 PM PDT 24 6719745288 ps
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