| T971 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2520509900 |
|
|
May 02 04:46:13 PM PDT 24 |
May 02 04:51:30 PM PDT 24 |
4227343330 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2408872289 |
|
|
May 02 04:44:47 PM PDT 24 |
May 02 04:50:50 PM PDT 24 |
4216903650 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.155473781 |
|
|
May 02 04:41:25 PM PDT 24 |
May 02 04:50:44 PM PDT 24 |
9689621814 ps |
| T595 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.530235643 |
|
|
May 02 04:58:07 PM PDT 24 |
May 02 05:53:55 PM PDT 24 |
24374771245 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1584286116 |
|
|
May 02 04:44:45 PM PDT 24 |
May 02 04:56:24 PM PDT 24 |
5307208472 ps |
| T722 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.169446385 |
|
|
May 02 05:05:47 PM PDT 24 |
May 02 05:21:32 PM PDT 24 |
5736499918 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.440455371 |
|
|
May 02 04:52:43 PM PDT 24 |
May 02 05:02:21 PM PDT 24 |
5898936844 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.79475245 |
|
|
May 02 04:46:23 PM PDT 24 |
May 02 05:00:38 PM PDT 24 |
7709838752 ps |
| T147 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.4134204739 |
|
|
May 02 04:41:49 PM PDT 24 |
May 02 04:49:13 PM PDT 24 |
3402455024 ps |
| T238 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1245383341 |
|
|
May 02 05:01:20 PM PDT 24 |
May 02 05:12:02 PM PDT 24 |
4857021512 ps |
| T976 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3820978797 |
|
|
May 02 05:02:43 PM PDT 24 |
May 02 05:12:15 PM PDT 24 |
5542219930 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.970246524 |
|
|
May 02 04:45:18 PM PDT 24 |
May 02 04:54:14 PM PDT 24 |
5682804074 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1722229074 |
|
|
May 02 04:42:24 PM PDT 24 |
May 02 04:52:37 PM PDT 24 |
5216668200 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1878471647 |
|
|
May 02 04:59:58 PM PDT 24 |
May 02 05:04:59 PM PDT 24 |
2755786224 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1618081300 |
|
|
May 02 04:57:00 PM PDT 24 |
May 02 05:21:04 PM PDT 24 |
7363555108 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3843227919 |
|
|
May 02 04:56:23 PM PDT 24 |
May 02 05:11:14 PM PDT 24 |
5691857463 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3584672308 |
|
|
May 02 04:57:53 PM PDT 24 |
May 02 05:07:48 PM PDT 24 |
4267304760 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4018659153 |
|
|
May 02 04:53:10 PM PDT 24 |
May 02 05:04:15 PM PDT 24 |
3927316208 ps |
| T671 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.262967739 |
|
|
May 02 05:07:41 PM PDT 24 |
May 02 05:16:59 PM PDT 24 |
5032977154 ps |
| T710 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.806638799 |
|
|
May 02 05:07:42 PM PDT 24 |
May 02 05:14:50 PM PDT 24 |
5924778024 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2493806237 |
|
|
May 02 04:57:30 PM PDT 24 |
May 02 05:07:11 PM PDT 24 |
5975502407 ps |
| T682 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.986754399 |
|
|
May 02 04:55:50 PM PDT 24 |
May 02 05:00:53 PM PDT 24 |
2637673113 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3228146271 |
|
|
May 02 04:41:52 PM PDT 24 |
May 02 04:48:21 PM PDT 24 |
4116340152 ps |
| T984 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2013731530 |
|
|
May 02 05:03:54 PM PDT 24 |
May 02 05:12:04 PM PDT 24 |
4189546470 ps |
| T46 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2995782469 |
|
|
May 02 04:48:23 PM PDT 24 |
May 02 04:56:18 PM PDT 24 |
4589282616 ps |
| T632 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2990137030 |
|
|
May 02 04:54:07 PM PDT 24 |
May 02 05:24:25 PM PDT 24 |
23302703745 ps |
| T633 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.777788678 |
|
|
May 02 04:59:38 PM PDT 24 |
May 02 05:03:11 PM PDT 24 |
3628688813 ps |
| T634 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3934290969 |
|
|
May 02 05:03:22 PM PDT 24 |
May 02 05:11:12 PM PDT 24 |
3862482722 ps |
| T635 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2048077831 |
|
|
May 02 04:54:14 PM PDT 24 |
May 02 05:11:11 PM PDT 24 |
8071031910 ps |
| T636 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1814727488 |
|
|
May 02 04:40:09 PM PDT 24 |
May 02 05:34:33 PM PDT 24 |
20493011052 ps |
| T637 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2736117363 |
|
|
May 02 05:01:01 PM PDT 24 |
May 02 05:04:44 PM PDT 24 |
2358845760 ps |
| T638 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3126706906 |
|
|
May 02 05:06:25 PM PDT 24 |
May 02 05:14:49 PM PDT 24 |
5654335128 ps |
| T639 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3427868483 |
|
|
May 02 05:02:02 PM PDT 24 |
May 02 05:15:30 PM PDT 24 |
4368968300 ps |
| T640 |
/workspace/coverage/default/1.chip_sw_example_rom.3377611780 |
|
|
May 02 04:42:01 PM PDT 24 |
May 02 04:43:39 PM PDT 24 |
2678022690 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.77942504 |
|
|
May 02 04:45:09 PM PDT 24 |
May 02 04:50:10 PM PDT 24 |
3430869188 ps |
| T588 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.575086784 |
|
|
May 02 04:44:34 PM PDT 24 |
May 02 04:55:33 PM PDT 24 |
4177562051 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2567094727 |
|
|
May 02 04:48:58 PM PDT 24 |
May 02 05:01:28 PM PDT 24 |
5732793608 ps |
| T321 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3434196904 |
|
|
May 02 04:44:55 PM PDT 24 |
May 02 04:58:19 PM PDT 24 |
4612897600 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3374690071 |
|
|
May 02 04:51:04 PM PDT 24 |
May 02 04:56:07 PM PDT 24 |
2642388006 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3901562730 |
|
|
May 02 04:39:19 PM PDT 24 |
May 02 04:43:21 PM PDT 24 |
2823188750 ps |
| T374 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2361394519 |
|
|
May 02 05:04:12 PM PDT 24 |
May 02 05:15:24 PM PDT 24 |
5350672340 ps |
| T375 |
/workspace/coverage/default/4.chip_tap_straps_dev.3618887547 |
|
|
May 02 04:58:48 PM PDT 24 |
May 02 05:01:29 PM PDT 24 |
3005634801 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.534881026 |
|
|
May 02 04:46:07 PM PDT 24 |
May 02 05:03:24 PM PDT 24 |
9755550550 ps |
| T303 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2733954892 |
|
|
May 02 04:47:32 PM PDT 24 |
May 02 04:59:43 PM PDT 24 |
4911377376 ps |
| T377 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.721265438 |
|
|
May 02 04:43:55 PM PDT 24 |
May 02 04:52:35 PM PDT 24 |
3792235322 ps |
| T378 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.497559767 |
|
|
May 02 04:47:04 PM PDT 24 |
May 02 04:51:23 PM PDT 24 |
3300907389 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2213987155 |
|
|
May 02 04:40:45 PM PDT 24 |
May 02 04:43:25 PM PDT 24 |
3116012839 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2558342880 |
|
|
May 02 04:59:13 PM PDT 24 |
May 02 05:04:06 PM PDT 24 |
2741856712 ps |
| T380 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1353938785 |
|
|
May 02 05:06:32 PM PDT 24 |
May 02 05:16:30 PM PDT 24 |
5539588480 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1148880355 |
|
|
May 02 04:43:17 PM PDT 24 |
May 02 04:47:28 PM PDT 24 |
2503928584 ps |
| T988 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2281786279 |
|
|
May 02 05:00:14 PM PDT 24 |
May 02 05:15:15 PM PDT 24 |
9786450833 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3682437070 |
|
|
May 02 04:40:16 PM PDT 24 |
May 02 04:45:16 PM PDT 24 |
2400836826 ps |
| T723 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002873291 |
|
|
May 02 05:06:58 PM PDT 24 |
May 02 05:12:19 PM PDT 24 |
3180751368 ps |
| T746 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2489407770 |
|
|
May 02 05:03:12 PM PDT 24 |
May 02 05:09:04 PM PDT 24 |
3652112500 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.895453646 |
|
|
May 02 04:39:59 PM PDT 24 |
May 02 06:51:51 PM PDT 24 |
31342235844 ps |
| T989 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3720330407 |
|
|
May 02 05:00:59 PM PDT 24 |
May 02 05:15:26 PM PDT 24 |
10113930220 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3120694491 |
|
|
May 02 04:45:16 PM PDT 24 |
May 02 04:53:51 PM PDT 24 |
9225063888 ps |
| T748 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2405953688 |
|
|
May 02 05:08:47 PM PDT 24 |
May 02 05:17:07 PM PDT 24 |
5437401052 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3878152799 |
|
|
May 02 04:46:16 PM PDT 24 |
May 02 04:56:53 PM PDT 24 |
4477003240 ps |
| T654 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716654471 |
|
|
May 02 05:08:05 PM PDT 24 |
May 02 05:13:28 PM PDT 24 |
3979517004 ps |
| T190 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3931238544 |
|
|
May 02 04:45:55 PM PDT 24 |
May 02 04:55:27 PM PDT 24 |
4731638485 ps |
| T687 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2956433696 |
|
|
May 02 04:56:49 PM PDT 24 |
May 02 05:07:32 PM PDT 24 |
5279636826 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3547384727 |
|
|
May 02 04:43:12 PM PDT 24 |
May 02 04:56:34 PM PDT 24 |
4707773940 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1121213617 |
|
|
May 02 04:56:19 PM PDT 24 |
May 02 05:06:13 PM PDT 24 |
7473025773 ps |
| T26 |
/workspace/coverage/default/2.chip_sw_gpio.239645883 |
|
|
May 02 04:53:49 PM PDT 24 |
May 02 05:04:06 PM PDT 24 |
4041318378 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.119930750 |
|
|
May 02 04:47:12 PM PDT 24 |
May 02 06:17:03 PM PDT 24 |
45175944398 ps |
| T713 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747844890 |
|
|
May 02 05:01:23 PM PDT 24 |
May 02 05:07:12 PM PDT 24 |
4049093384 ps |
| T995 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.3079784825 |
|
|
May 02 04:48:11 PM PDT 24 |
May 02 04:50:54 PM PDT 24 |
3207034663 ps |
| T737 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403472053 |
|
|
May 02 05:07:29 PM PDT 24 |
May 02 05:13:01 PM PDT 24 |
3421109342 ps |
| T611 |
/workspace/coverage/default/1.chip_sw_power_idle_load.300830953 |
|
|
May 02 04:49:12 PM PDT 24 |
May 02 04:59:17 PM PDT 24 |
4161989708 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3324219839 |
|
|
May 02 04:53:33 PM PDT 24 |
May 02 05:07:07 PM PDT 24 |
5591491528 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1520784867 |
|
|
May 02 04:48:58 PM PDT 24 |
May 02 04:53:41 PM PDT 24 |
3597597032 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.275287031 |
|
|
May 02 04:43:55 PM PDT 24 |
May 02 05:08:08 PM PDT 24 |
7814407060 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3369788117 |
|
|
May 02 04:58:45 PM PDT 24 |
May 02 05:02:09 PM PDT 24 |
2195412856 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2245245397 |
|
|
May 02 04:39:39 PM PDT 24 |
May 02 05:57:14 PM PDT 24 |
42715702592 ps |
| T731 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3827737669 |
|
|
May 02 05:03:26 PM PDT 24 |
May 02 05:14:31 PM PDT 24 |
5494425864 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.667677019 |
|
|
May 02 04:56:30 PM PDT 24 |
May 02 05:08:38 PM PDT 24 |
6583413236 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3102497425 |
|
|
May 02 04:42:47 PM PDT 24 |
May 02 04:50:35 PM PDT 24 |
7738156420 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2022302131 |
|
|
May 02 04:42:42 PM PDT 24 |
May 02 04:52:45 PM PDT 24 |
6335865850 ps |
| T701 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238548569 |
|
|
May 02 05:06:51 PM PDT 24 |
May 02 05:13:35 PM PDT 24 |
3328689544 ps |
| T726 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4178328683 |
|
|
May 02 05:04:43 PM PDT 24 |
May 02 05:10:55 PM PDT 24 |
4242771222 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2035680902 |
|
|
May 02 04:44:09 PM PDT 24 |
May 02 04:47:52 PM PDT 24 |
2721679448 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_edn_kat.609335477 |
|
|
May 02 04:56:02 PM PDT 24 |
May 02 05:07:06 PM PDT 24 |
3457738148 ps |
| T126 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.242363718 |
|
|
May 02 04:56:42 PM PDT 24 |
May 02 05:04:31 PM PDT 24 |
5866686544 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1904524454 |
|
|
May 02 04:39:15 PM PDT 24 |
May 02 05:59:59 PM PDT 24 |
18890553724 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1023448211 |
|
|
May 02 04:54:07 PM PDT 24 |
May 02 04:59:06 PM PDT 24 |
2853585168 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.81471972 |
|
|
May 02 04:47:01 PM PDT 24 |
May 02 05:51:37 PM PDT 24 |
18848638077 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2822029771 |
|
|
May 02 04:57:48 PM PDT 24 |
May 02 05:23:21 PM PDT 24 |
8267908390 ps |
| T310 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1285371209 |
|
|
May 02 04:52:27 PM PDT 24 |
May 02 05:08:42 PM PDT 24 |
5262510664 ps |
| T471 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.52341443 |
|
|
May 02 04:49:44 PM PDT 24 |
May 02 05:02:41 PM PDT 24 |
4582404220 ps |
| T673 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3373099724 |
|
|
May 02 04:47:37 PM PDT 24 |
May 02 04:58:16 PM PDT 24 |
5723230622 ps |
| T73 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.149097119 |
|
|
May 02 04:40:45 PM PDT 24 |
May 02 04:49:18 PM PDT 24 |
4218888188 ps |
| T749 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193017417 |
|
|
May 02 05:01:45 PM PDT 24 |
May 02 05:09:09 PM PDT 24 |
3392753026 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1980048504 |
|
|
May 02 04:44:32 PM PDT 24 |
May 02 04:48:06 PM PDT 24 |
2612942688 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.422168455 |
|
|
May 02 04:42:31 PM PDT 24 |
May 02 04:49:15 PM PDT 24 |
3449731480 ps |
| T1008 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1257976891 |
|
|
May 02 05:02:57 PM PDT 24 |
May 02 05:26:08 PM PDT 24 |
8977447850 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1700634281 |
|
|
May 02 04:56:33 PM PDT 24 |
May 02 05:14:01 PM PDT 24 |
5631742516 ps |
| T719 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.128898205 |
|
|
May 02 05:07:14 PM PDT 24 |
May 02 05:13:37 PM PDT 24 |
3565554212 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_alert_test.3781150161 |
|
|
May 02 04:57:33 PM PDT 24 |
May 02 05:03:26 PM PDT 24 |
3176460748 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.949513597 |
|
|
May 02 04:53:13 PM PDT 24 |
May 02 05:06:34 PM PDT 24 |
3843386314 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2994284673 |
|
|
May 02 04:59:14 PM PDT 24 |
May 02 05:04:23 PM PDT 24 |
2600436430 ps |
| T274 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2620351250 |
|
|
May 02 04:47:33 PM PDT 24 |
May 02 05:04:36 PM PDT 24 |
9540923992 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.245900534 |
|
|
May 02 04:40:48 PM PDT 24 |
May 02 04:43:54 PM PDT 24 |
2211739979 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2191765083 |
|
|
May 02 04:56:16 PM PDT 24 |
May 02 05:19:07 PM PDT 24 |
10853363066 ps |
| T1012 |
/workspace/coverage/default/0.chip_sival_flash_info_access.2340216638 |
|
|
May 02 04:39:56 PM PDT 24 |
May 02 04:45:24 PM PDT 24 |
3175598250 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.866072898 |
|
|
May 02 04:40:59 PM PDT 24 |
May 02 04:49:36 PM PDT 24 |
5426052384 ps |
| T647 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099881489 |
|
|
May 02 05:05:43 PM PDT 24 |
May 02 05:12:36 PM PDT 24 |
4351109480 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1890866710 |
|
|
May 02 04:49:40 PM PDT 24 |
May 02 05:10:18 PM PDT 24 |
7309833642 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3074506792 |
|
|
May 02 04:43:40 PM PDT 24 |
May 02 04:50:41 PM PDT 24 |
3728159449 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.731510048 |
|
|
May 02 04:44:41 PM PDT 24 |
May 02 04:53:08 PM PDT 24 |
5057513045 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2150177767 |
|
|
May 02 04:41:59 PM PDT 24 |
May 02 04:46:51 PM PDT 24 |
3408389444 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1595300821 |
|
|
May 02 04:41:37 PM PDT 24 |
May 02 04:51:15 PM PDT 24 |
3819464168 ps |
| T644 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1981349582 |
|
|
May 02 04:56:48 PM PDT 24 |
May 02 05:45:46 PM PDT 24 |
20145415915 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.977120114 |
|
|
May 02 04:43:16 PM PDT 24 |
May 02 04:47:21 PM PDT 24 |
2325275918 ps |
| T320 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1647760921 |
|
|
May 02 04:46:34 PM PDT 24 |
May 02 05:08:46 PM PDT 24 |
6534048830 ps |
| T589 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.499401060 |
|
|
May 02 04:47:19 PM PDT 24 |
May 02 04:49:20 PM PDT 24 |
2340664652 ps |
| T650 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.4211492226 |
|
|
May 02 05:02:36 PM PDT 24 |
May 02 05:13:29 PM PDT 24 |
5978029544 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3427448965 |
|
|
May 02 04:42:34 PM PDT 24 |
May 02 05:04:42 PM PDT 24 |
7526697067 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1669796313 |
|
|
May 02 04:46:41 PM PDT 24 |
May 02 04:52:31 PM PDT 24 |
3670712435 ps |
| T1020 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1909576778 |
|
|
May 02 05:06:18 PM PDT 24 |
May 02 05:15:25 PM PDT 24 |
4158417350 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4264915977 |
|
|
May 02 04:58:18 PM PDT 24 |
May 02 05:05:35 PM PDT 24 |
3409909560 ps |
| T597 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3125836149 |
|
|
May 02 04:46:38 PM PDT 24 |
May 02 04:59:36 PM PDT 24 |
3608566356 ps |
| T646 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1251742768 |
|
|
May 02 05:07:02 PM PDT 24 |
May 02 05:15:04 PM PDT 24 |
5459762932 ps |
| T753 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3209878591 |
|
|
May 02 05:06:17 PM PDT 24 |
May 02 05:13:18 PM PDT 24 |
3664967956 ps |
| T1022 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.868850261 |
|
|
May 02 05:01:03 PM PDT 24 |
May 02 05:10:50 PM PDT 24 |
3746748288 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1320583698 |
|
|
May 02 04:56:32 PM PDT 24 |
May 02 05:01:33 PM PDT 24 |
3167475742 ps |
| T1024 |
/workspace/coverage/default/1.chip_tap_straps_prod.2758515758 |
|
|
May 02 04:48:26 PM PDT 24 |
May 02 04:51:04 PM PDT 24 |
2456635108 ps |
| T738 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.4096690912 |
|
|
May 02 05:04:10 PM PDT 24 |
May 02 05:12:43 PM PDT 24 |
4591395140 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.804919928 |
|
|
May 02 04:42:40 PM PDT 24 |
May 02 04:53:23 PM PDT 24 |
18037797000 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.340127540 |
|
|
May 02 04:56:15 PM PDT 24 |
May 02 05:07:45 PM PDT 24 |
5573654624 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.4136155877 |
|
|
May 02 04:59:30 PM PDT 24 |
May 02 05:03:12 PM PDT 24 |
3139284918 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.1599908801 |
|
|
May 02 04:45:50 PM PDT 24 |
May 02 05:32:09 PM PDT 24 |
11249729326 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3430800141 |
|
|
May 02 04:48:18 PM PDT 24 |
May 02 05:01:06 PM PDT 24 |
12076057092 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1317626880 |
|
|
May 02 04:46:51 PM PDT 24 |
May 02 04:55:47 PM PDT 24 |
5846680552 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1869340929 |
|
|
May 02 04:42:31 PM PDT 24 |
May 02 05:01:43 PM PDT 24 |
5365922068 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3557017326 |
|
|
May 02 04:44:18 PM PDT 24 |
May 02 04:51:32 PM PDT 24 |
4274484800 ps |
| T711 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126428657 |
|
|
May 02 05:05:20 PM PDT 24 |
May 02 05:12:24 PM PDT 24 |
3631808874 ps |
| T1031 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3817891723 |
|
|
May 02 05:06:13 PM PDT 24 |
May 02 05:11:58 PM PDT 24 |
3899236430 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2786646324 |
|
|
May 02 04:45:34 PM PDT 24 |
May 02 04:52:28 PM PDT 24 |
4521596950 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.443460954 |
|
|
May 02 04:42:54 PM PDT 24 |
May 02 05:08:13 PM PDT 24 |
6532887496 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2966795316 |
|
|
May 02 04:39:51 PM PDT 24 |
May 02 04:44:18 PM PDT 24 |
2369343726 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3172454479 |
|
|
May 02 04:59:45 PM PDT 24 |
May 02 05:03:55 PM PDT 24 |
2455693196 ps |
| T226 |
/workspace/coverage/default/1.chip_jtag_mem_access.456595223 |
|
|
May 02 04:40:35 PM PDT 24 |
May 02 05:06:58 PM PDT 24 |
13085611569 ps |
| T213 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3569038377 |
|
|
May 02 04:57:54 PM PDT 24 |
May 02 05:22:18 PM PDT 24 |
12377480672 ps |
| T326 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3552073859 |
|
|
May 02 04:55:13 PM PDT 24 |
May 02 05:02:44 PM PDT 24 |
3744808520 ps |
| T590 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3290014120 |
|
|
May 02 04:47:18 PM PDT 24 |
May 02 04:49:10 PM PDT 24 |
2354004456 ps |
| T1036 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3865295280 |
|
|
May 02 04:44:17 PM PDT 24 |
May 02 05:05:16 PM PDT 24 |
11664301034 ps |
| T656 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.39983463 |
|
|
May 02 05:06:30 PM PDT 24 |
May 02 05:16:08 PM PDT 24 |
4933148648 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1178356913 |
|
|
May 02 04:47:43 PM PDT 24 |
May 02 04:53:32 PM PDT 24 |
3091498172 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2879538025 |
|
|
May 02 04:52:51 PM PDT 24 |
May 02 05:11:40 PM PDT 24 |
6084733310 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1737580687 |
|
|
May 02 04:47:41 PM PDT 24 |
May 02 04:59:21 PM PDT 24 |
5974757780 ps |
| T724 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.430826007 |
|
|
May 02 05:08:41 PM PDT 24 |
May 02 05:17:45 PM PDT 24 |
4650963836 ps |
| T732 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3382905641 |
|
|
May 02 05:04:28 PM PDT 24 |
May 02 05:09:44 PM PDT 24 |
3212392740 ps |
| T1040 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.444339169 |
|
|
May 02 05:02:18 PM PDT 24 |
May 02 05:17:25 PM PDT 24 |
9915857792 ps |
| T709 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.4087284255 |
|
|
May 02 05:03:41 PM PDT 24 |
May 02 05:12:34 PM PDT 24 |
5132518960 ps |
| T91 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2855838652 |
|
|
May 02 05:06:12 PM PDT 24 |
May 02 05:14:11 PM PDT 24 |
4623763310 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2168241188 |
|
|
May 02 04:40:43 PM PDT 24 |
May 02 04:48:50 PM PDT 24 |
3502507560 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1182900981 |
|
|
May 02 05:00:24 PM PDT 24 |
May 02 05:04:46 PM PDT 24 |
2905402224 ps |
| T1042 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2738659631 |
|
|
May 02 04:48:08 PM PDT 24 |
May 02 05:09:50 PM PDT 24 |
7922614248 ps |
| T655 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035638699 |
|
|
May 02 05:05:40 PM PDT 24 |
May 02 05:10:56 PM PDT 24 |
3675232536 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.439698803 |
|
|
May 02 04:51:35 PM PDT 24 |
May 02 05:09:01 PM PDT 24 |
5259862064 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3534882634 |
|
|
May 02 04:56:53 PM PDT 24 |
May 02 05:01:56 PM PDT 24 |
3733224056 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2021114746 |
|
|
May 02 04:50:54 PM PDT 24 |
May 02 04:58:06 PM PDT 24 |
5223885936 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.535040236 |
|
|
May 02 04:58:08 PM PDT 24 |
May 02 05:42:15 PM PDT 24 |
12674246300 ps |
| T240 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.1538889672 |
|
|
May 02 05:01:05 PM PDT 24 |
May 02 05:09:48 PM PDT 24 |
6048443720 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.323426759 |
|
|
May 02 04:40:42 PM PDT 24 |
May 02 04:55:12 PM PDT 24 |
6370648160 ps |
| T714 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1085286589 |
|
|
May 02 05:03:44 PM PDT 24 |
May 02 05:09:28 PM PDT 24 |
3246159936 ps |
| T145 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1319531605 |
|
|
May 02 04:52:48 PM PDT 24 |
May 02 07:53:18 PM PDT 24 |
58330978050 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1382137192 |
|
|
May 02 04:49:01 PM PDT 24 |
May 02 04:56:16 PM PDT 24 |
4400664268 ps |
| T649 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.615117190 |
|
|
May 02 05:04:10 PM PDT 24 |
May 02 05:12:20 PM PDT 24 |
4866570056 ps |
| T1049 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2285712995 |
|
|
May 02 04:59:42 PM PDT 24 |
May 02 05:12:04 PM PDT 24 |
9554930429 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3527262632 |
|
|
May 02 04:40:39 PM PDT 24 |
May 02 04:46:33 PM PDT 24 |
3469081140 ps |
| T1050 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1606970398 |
|
|
May 02 05:02:53 PM PDT 24 |
May 02 05:09:57 PM PDT 24 |
3633604046 ps |
| T661 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.34699960 |
|
|
May 02 05:04:39 PM PDT 24 |
May 02 05:11:14 PM PDT 24 |
3391439652 ps |
| T657 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1545073953 |
|
|
May 02 05:04:15 PM PDT 24 |
May 02 05:13:40 PM PDT 24 |
5266648134 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.426118948 |
|
|
May 02 04:42:56 PM PDT 24 |
May 02 04:51:42 PM PDT 24 |
4432027224 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2454590504 |
|
|
May 02 04:45:54 PM PDT 24 |
May 02 04:56:45 PM PDT 24 |
7996749544 ps |
| T398 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.244585675 |
|
|
May 02 05:07:53 PM PDT 24 |
May 02 05:16:33 PM PDT 24 |
4854182682 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3469780050 |
|
|
May 02 04:46:04 PM PDT 24 |
May 02 05:00:01 PM PDT 24 |
9576943160 ps |
| T1054 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3444079441 |
|
|
May 02 05:01:36 PM PDT 24 |
May 02 05:11:37 PM PDT 24 |
7274407914 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.24022442 |
|
|
May 02 04:39:37 PM PDT 24 |
May 02 04:46:54 PM PDT 24 |
6368826320 ps |
| T472 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.184733118 |
|
|
May 02 04:56:17 PM PDT 24 |
May 02 05:12:54 PM PDT 24 |
4833511696 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2890050112 |
|
|
May 02 04:57:39 PM PDT 24 |
May 02 05:12:19 PM PDT 24 |
7576635742 ps |
| T1056 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.444538412 |
|
|
May 02 05:02:37 PM PDT 24 |
May 02 05:13:12 PM PDT 24 |
5319909460 ps |
| T222 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3246458892 |
|
|
May 02 05:07:00 PM PDT 24 |
May 02 05:15:37 PM PDT 24 |
6017688024 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1507844340 |
|
|
May 02 04:47:46 PM PDT 24 |
May 02 05:08:53 PM PDT 24 |
11715709800 ps |
| T700 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3939835534 |
|
|
May 02 05:06:24 PM PDT 24 |
May 02 05:15:53 PM PDT 24 |
5027392232 ps |
| T1057 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1437926304 |
|
|
May 02 05:00:59 PM PDT 24 |
May 02 05:09:16 PM PDT 24 |
4424583012 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4141207170 |
|
|
May 02 04:42:35 PM PDT 24 |
May 02 04:50:23 PM PDT 24 |
3299440332 ps |
| T1058 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.487959324 |
|
|
May 02 04:43:33 PM PDT 24 |
May 02 04:49:35 PM PDT 24 |
4842279050 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2036588197 |
|
|
May 02 04:42:21 PM PDT 24 |
May 02 04:52:13 PM PDT 24 |
4162966920 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2301660703 |
|
|
May 02 04:40:24 PM PDT 24 |
May 02 05:01:44 PM PDT 24 |
12902505917 ps |
| T1061 |
/workspace/coverage/default/2.rom_keymgr_functest.3715138591 |
|
|
May 02 04:59:12 PM PDT 24 |
May 02 05:07:28 PM PDT 24 |
5262398930 ps |
| T715 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1961302986 |
|
|
May 02 05:03:03 PM PDT 24 |
May 02 05:08:54 PM PDT 24 |
3764254580 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.114312428 |
|
|
May 02 04:45:16 PM PDT 24 |
May 02 04:50:27 PM PDT 24 |
2708120438 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1261845448 |
|
|
May 02 04:47:31 PM PDT 24 |
May 02 05:15:21 PM PDT 24 |
8481799070 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3641642089 |
|
|
May 02 04:51:48 PM PDT 24 |
May 02 04:55:19 PM PDT 24 |
3051185081 ps |
| T591 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2413568499 |
|
|
May 02 04:39:41 PM PDT 24 |
May 02 04:41:36 PM PDT 24 |
2230802352 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3149928350 |
|
|
May 02 04:56:50 PM PDT 24 |
May 02 05:22:09 PM PDT 24 |
9140268910 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.4121953853 |
|
|
May 02 04:51:03 PM PDT 24 |
May 02 04:54:47 PM PDT 24 |
2564703432 ps |
| T1067 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4089956744 |
|
|
May 02 04:42:51 PM PDT 24 |
May 02 05:09:52 PM PDT 24 |
12254262884 ps |
| T1068 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4041511731 |
|
|
May 02 05:06:22 PM PDT 24 |
May 02 05:13:54 PM PDT 24 |
5876735888 ps |
| T361 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1819712238 |
|
|
May 02 04:42:18 PM PDT 24 |
May 02 04:47:59 PM PDT 24 |
3367090710 ps |
| T56 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2237597671 |
|
|
May 02 04:33:29 PM PDT 24 |
May 02 04:49:25 PM PDT 24 |
10564501963 ps |
| T337 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.587470113 |
|
|
May 02 05:00:34 PM PDT 24 |
May 02 05:14:15 PM PDT 24 |
6911889168 ps |
| T751 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.345854582 |
|
|
May 02 05:05:01 PM PDT 24 |
May 02 05:13:53 PM PDT 24 |
5938164112 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2881843726 |
|
|
May 02 04:58:10 PM PDT 24 |
May 02 05:08:33 PM PDT 24 |
3918490660 ps |
| T1070 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3487150773 |
|
|
May 02 05:07:28 PM PDT 24 |
May 02 05:17:24 PM PDT 24 |
6170151292 ps |
| T234 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1495719099 |
|
|
May 02 04:49:04 PM PDT 24 |
May 02 04:58:32 PM PDT 24 |
4708845168 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3536713279 |
|
|
May 02 04:47:09 PM PDT 24 |
May 02 05:11:00 PM PDT 24 |
20497123000 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1286088069 |
|
|
May 02 04:53:56 PM PDT 24 |
May 02 05:30:08 PM PDT 24 |
27784324735 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1086743600 |
|
|
May 02 04:47:05 PM PDT 24 |
May 02 04:51:28 PM PDT 24 |
2829907917 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1187332088 |
|
|
May 02 04:45:40 PM PDT 24 |
May 02 04:52:02 PM PDT 24 |
5523849120 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2669985487 |
|
|
May 02 04:52:45 PM PDT 24 |
May 02 05:13:39 PM PDT 24 |
8679875245 ps |
| T662 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2661650270 |
|
|
May 02 05:07:17 PM PDT 24 |
May 02 05:18:02 PM PDT 24 |
5813426520 ps |
| T720 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2169829375 |
|
|
May 02 05:04:38 PM PDT 24 |
May 02 05:10:20 PM PDT 24 |
3680797768 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3784419864 |
|
|
May 02 04:46:03 PM PDT 24 |
May 02 04:52:41 PM PDT 24 |
3056007902 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2494431729 |
|
|
May 02 04:45:48 PM PDT 24 |
May 02 04:56:19 PM PDT 24 |
4212701938 ps |
| T1076 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.300209590 |
|
|
May 02 04:52:59 PM PDT 24 |
May 02 05:03:42 PM PDT 24 |
4188999458 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4210810201 |
|
|
May 02 04:56:39 PM PDT 24 |
May 02 05:05:36 PM PDT 24 |
7611827210 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1305908220 |
|
|
May 02 04:41:30 PM PDT 24 |
May 02 05:16:10 PM PDT 24 |
24230423409 ps |
| T92 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.532507121 |
|
|
May 02 05:01:24 PM PDT 24 |
May 02 05:10:09 PM PDT 24 |
5589871200 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3641692714 |
|
|
May 02 04:47:47 PM PDT 24 |
May 02 04:58:56 PM PDT 24 |
8737016264 ps |
| T658 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.4048356520 |
|
|
May 02 05:03:45 PM PDT 24 |
May 02 05:13:37 PM PDT 24 |
5656945032 ps |
| T735 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839564530 |
|
|
May 02 05:04:59 PM PDT 24 |
May 02 05:11:45 PM PDT 24 |
3512713240 ps |
| T1080 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.201965184 |
|
|
May 02 05:01:38 PM PDT 24 |
May 02 05:18:14 PM PDT 24 |
8783473004 ps |
| T754 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3457657402 |
|
|
May 02 05:06:05 PM PDT 24 |
May 02 05:15:25 PM PDT 24 |
6029110758 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.238112949 |
|
|
May 02 04:59:22 PM PDT 24 |
May 02 05:03:03 PM PDT 24 |
2855231450 ps |
| T1082 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3838860048 |
|
|
May 02 04:41:41 PM PDT 24 |
May 02 04:52:00 PM PDT 24 |
4023394440 ps |
| T743 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288335030 |
|
|
May 02 05:06:22 PM PDT 24 |
May 02 05:12:52 PM PDT 24 |
3711801300 ps |
| T1083 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111328884 |
|
|
May 02 05:09:54 PM PDT 24 |
May 02 05:15:54 PM PDT 24 |
3489255736 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.247317517 |
|
|
May 02 04:46:18 PM PDT 24 |
May 02 04:57:08 PM PDT 24 |
4590406096 ps |
| T750 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.204833379 |
|
|
May 02 05:05:00 PM PDT 24 |
May 02 05:09:48 PM PDT 24 |
3342725360 ps |
| T651 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2595642761 |
|
|
May 02 05:05:31 PM PDT 24 |
May 02 05:16:19 PM PDT 24 |
5263739684 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.233298958 |
|
|
May 02 04:51:55 PM PDT 24 |
May 02 04:56:23 PM PDT 24 |
3013497216 ps |
| T203 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.608025607 |
|
|
May 02 04:43:14 PM PDT 24 |
May 02 05:50:45 PM PDT 24 |
14510359712 ps |
| T1086 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3794578450 |
|
|
May 02 04:58:50 PM PDT 24 |
May 02 05:16:11 PM PDT 24 |
6030329172 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3514516326 |
|
|
May 02 04:59:25 PM PDT 24 |
May 02 05:02:37 PM PDT 24 |
2347454776 ps |
| T592 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.899848124 |
|
|
May 02 04:40:36 PM PDT 24 |
May 02 04:42:06 PM PDT 24 |
2452426591 ps |
| T27 |
/workspace/coverage/default/0.chip_sw_gpio.676742910 |
|
|
May 02 04:42:01 PM PDT 24 |
May 02 04:52:45 PM PDT 24 |
4799639297 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.47344651 |
|
|
May 02 04:40:31 PM PDT 24 |
May 02 07:27:27 PM PDT 24 |
58915608555 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.447574418 |
|
|
May 02 04:49:34 PM PDT 24 |
May 02 05:07:10 PM PDT 24 |
7165166270 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2438796101 |
|
|
May 02 04:53:33 PM PDT 24 |
May 02 05:02:15 PM PDT 24 |
3766581144 ps |
| T641 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2640028015 |
|
|
May 02 04:44:15 PM PDT 24 |
May 02 04:59:15 PM PDT 24 |
5080186828 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1563189484 |
|
|
May 02 04:51:45 PM PDT 24 |
May 02 05:01:25 PM PDT 24 |
4338051170 ps |
| T58 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.56894901 |
|
|
May 02 04:52:17 PM PDT 24 |
May 02 04:58:54 PM PDT 24 |
5830177310 ps |
| T1091 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3964103571 |
|
|
May 02 05:02:20 PM PDT 24 |
May 02 05:10:26 PM PDT 24 |
4901040592 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.654722942 |
|
|
May 02 04:44:24 PM PDT 24 |
May 02 04:49:20 PM PDT 24 |
5254459888 ps |
| T659 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1733181400 |
|
|
May 02 05:03:31 PM PDT 24 |
May 02 05:11:47 PM PDT 24 |
5046020824 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1255637739 |
|
|
May 02 04:53:16 PM PDT 24 |
May 02 05:01:16 PM PDT 24 |
7175860120 ps |