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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 95.29 93.71 95.58 94.38 97.38 99.53


Total test records in report: 2788
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T1094 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3250673616 May 02 04:52:26 PM PDT 24 May 02 05:22:16 PM PDT 24 8838230088 ps
T1095 /workspace/coverage/default/0.chip_sw_power_idle_load.646634346 May 02 04:45:05 PM PDT 24 May 02 04:54:58 PM PDT 24 3956299576 ps
T663 /workspace/coverage/default/50.chip_sw_all_escalation_resets.497365184 May 02 05:04:17 PM PDT 24 May 02 05:12:51 PM PDT 24 5503265554 ps
T1096 /workspace/coverage/default/2.chip_sw_aes_enc.1068656628 May 02 04:57:23 PM PDT 24 May 02 05:00:24 PM PDT 24 2138884424 ps
T148 /workspace/coverage/default/1.chip_plic_all_irqs_10.2798718926 May 02 04:50:13 PM PDT 24 May 02 05:00:43 PM PDT 24 4042389696 ps
T1097 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2122564159 May 02 04:50:07 PM PDT 24 May 02 05:03:50 PM PDT 24 4887147598 ps
T1098 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1269531331 May 02 04:48:23 PM PDT 24 May 02 04:54:13 PM PDT 24 3000303950 ps
T1099 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2816433886 May 02 04:46:14 PM PDT 24 May 02 04:51:27 PM PDT 24 2764519776 ps
T1100 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2339442855 May 02 05:02:32 PM PDT 24 May 02 05:17:19 PM PDT 24 12028534499 ps
T593 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2962840237 May 02 04:53:18 PM PDT 24 May 02 04:56:04 PM PDT 24 3434000816 ps
T1101 /workspace/coverage/default/2.chip_sw_hmac_enc.1690507891 May 02 04:56:07 PM PDT 24 May 02 05:00:35 PM PDT 24 2861785640 ps
T1102 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3061140844 May 02 04:42:46 PM PDT 24 May 02 05:45:24 PM PDT 24 23529654024 ps
T1103 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2887102064 May 02 04:41:43 PM PDT 24 May 02 04:44:59 PM PDT 24 2856593886 ps
T1104 /workspace/coverage/default/0.chip_sw_aes_idle.3440494136 May 02 04:41:51 PM PDT 24 May 02 04:46:32 PM PDT 24 2960388972 ps
T1105 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1154692069 May 02 04:43:35 PM PDT 24 May 02 04:47:39 PM PDT 24 2440749222 ps
T1106 /workspace/coverage/default/4.chip_tap_straps_rma.2092174428 May 02 05:01:09 PM PDT 24 May 02 05:05:33 PM PDT 24 3370629930 ps
T250 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.508042636 May 02 04:52:01 PM PDT 24 May 02 05:05:35 PM PDT 24 5159296360 ps
T251 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.276726691 May 02 04:45:14 PM PDT 24 May 02 05:00:22 PM PDT 24 4859240200 ps
T252 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.640699165 May 02 04:42:56 PM PDT 24 May 02 04:52:09 PM PDT 24 5215749496 ps
T253 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2712868532 May 02 04:54:52 PM PDT 24 May 02 05:02:26 PM PDT 24 5350539895 ps
T254 /workspace/coverage/default/0.chip_sw_aes_enc.2888097091 May 02 04:42:30 PM PDT 24 May 02 04:45:51 PM PDT 24 2319291486 ps
T255 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1636328119 May 02 04:58:18 PM PDT 24 May 02 05:05:33 PM PDT 24 4469794720 ps
T256 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.650561875 May 02 04:58:45 PM PDT 24 May 02 05:06:19 PM PDT 24 3295577236 ps
T257 /workspace/coverage/default/2.chip_sw_example_concurrency.1097643181 May 02 04:51:07 PM PDT 24 May 02 04:54:39 PM PDT 24 2887361280 ps
T258 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3409686419 May 02 04:41:40 PM PDT 24 May 02 04:47:51 PM PDT 24 3404853527 ps
T259 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2900349101 May 02 04:47:42 PM PDT 24 May 02 08:23:51 PM PDT 24 253907773296 ps
T40 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2776914826 May 02 04:54:26 PM PDT 24 May 02 04:59:51 PM PDT 24 2722930686 ps
T596 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1390468579 May 02 04:49:45 PM PDT 24 May 02 05:46:04 PM PDT 24 25080512672 ps
T1107 /workspace/coverage/default/1.chip_sw_edn_sw_mode.3502994012 May 02 04:44:33 PM PDT 24 May 02 05:09:28 PM PDT 24 8765992636 ps
T1108 /workspace/coverage/default/2.chip_sw_kmac_entropy.733282703 May 02 04:53:13 PM PDT 24 May 02 04:56:41 PM PDT 24 2401200700 ps
T1109 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4052406475 May 02 04:45:42 PM PDT 24 May 02 04:53:33 PM PDT 24 4025279012 ps
T1110 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2301280227 May 02 04:59:16 PM PDT 24 May 02 05:02:42 PM PDT 24 2895087650 ps
T381 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.526017175 May 02 04:43:47 PM PDT 24 May 02 05:09:12 PM PDT 24 22190519190 ps
T1111 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.743205352 May 02 04:52:55 PM PDT 24 May 02 05:10:00 PM PDT 24 8323243234 ps
T1112 /workspace/coverage/default/0.chip_sw_rv_timer_irq.4269798438 May 02 04:42:05 PM PDT 24 May 02 04:46:21 PM PDT 24 3109510904 ps
T741 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2048181464 May 02 05:03:47 PM PDT 24 May 02 05:11:34 PM PDT 24 5520602600 ps
T204 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4062636508 May 02 04:49:53 PM PDT 24 May 02 05:43:57 PM PDT 24 12761468464 ps
T1113 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2336479578 May 02 04:41:56 PM PDT 24 May 02 05:00:22 PM PDT 24 7740032048 ps
T1114 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2741155893 May 02 04:43:35 PM PDT 24 May 02 04:47:16 PM PDT 24 2815507108 ps
T1115 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1399393033 May 02 04:47:09 PM PDT 24 May 02 04:54:31 PM PDT 24 9479231720 ps
T1116 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.245078082 May 02 04:40:38 PM PDT 24 May 02 05:09:46 PM PDT 24 9126721832 ps
T343 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1977603421 May 02 05:06:59 PM PDT 24 May 02 05:14:56 PM PDT 24 5135610880 ps
T1117 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2474634654 May 02 04:40:53 PM PDT 24 May 02 04:44:59 PM PDT 24 2684205906 ps
T1118 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2663982642 May 02 04:39:49 PM PDT 24 May 02 04:51:52 PM PDT 24 6623352150 ps
T1119 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.493440439 May 02 04:40:14 PM PDT 24 May 02 08:24:48 PM PDT 24 77444058434 ps
T1120 /workspace/coverage/default/2.chip_sw_example_rom.3060484219 May 02 04:51:14 PM PDT 24 May 02 04:53:00 PM PDT 24 2487433512 ps
T1121 /workspace/coverage/default/1.chip_sw_kmac_entropy.1998265684 May 02 04:44:22 PM PDT 24 May 02 04:47:42 PM PDT 24 2722121166 ps
T1122 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3212336156 May 02 04:39:22 PM PDT 24 May 02 07:47:25 PM PDT 24 64032969240 ps
T1123 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3330324620 May 02 04:45:27 PM PDT 24 May 02 05:07:15 PM PDT 24 7090025688 ps
T1124 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3481991731 May 02 04:50:32 PM PDT 24 May 02 05:17:13 PM PDT 24 9239378623 ps
T1125 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.884956835 May 02 05:04:06 PM PDT 24 May 02 05:10:39 PM PDT 24 3454922280 ps
T1126 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2821345943 May 02 04:55:59 PM PDT 24 May 02 05:06:33 PM PDT 24 5191666216 ps
T624 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.873426573 May 02 04:44:42 PM PDT 24 May 02 04:48:37 PM PDT 24 3596116696 ps
T1127 /workspace/coverage/default/87.chip_sw_all_escalation_resets.4278035140 May 02 05:07:22 PM PDT 24 May 02 05:15:41 PM PDT 24 5911503482 ps
T1128 /workspace/coverage/default/1.chip_sw_edn_kat.3981228020 May 02 04:47:02 PM PDT 24 May 02 04:58:36 PM PDT 24 3088441126 ps
T1129 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.609405952 May 02 04:47:14 PM PDT 24 May 02 04:49:27 PM PDT 24 3146384239 ps
T93 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3845007541 May 02 05:06:05 PM PDT 24 May 02 05:16:16 PM PDT 24 5142189670 ps
T1130 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.425767528 May 02 04:41:00 PM PDT 24 May 02 04:50:34 PM PDT 24 4836248228 ps
T1131 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3686420536 May 02 04:43:27 PM PDT 24 May 02 04:46:16 PM PDT 24 2125786168 ps
T1132 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3973433377 May 02 04:52:26 PM PDT 24 May 02 04:55:48 PM PDT 24 2493480030 ps
T316 /workspace/coverage/default/1.chip_sival_flash_info_access.3663489410 May 02 04:46:27 PM PDT 24 May 02 04:51:41 PM PDT 24 3337417640 ps
T1133 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2897706406 May 02 04:45:45 PM PDT 24 May 02 04:57:33 PM PDT 24 5192584840 ps
T1134 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.904235894 May 02 04:41:21 PM PDT 24 May 02 04:46:35 PM PDT 24 2971363450 ps
T1135 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.278256159 May 02 04:57:44 PM PDT 24 May 02 05:06:43 PM PDT 24 5085168276 ps
T297 /workspace/coverage/default/1.chip_plic_all_irqs_0.2630201368 May 02 04:48:23 PM PDT 24 May 02 05:08:10 PM PDT 24 6369708436 ps
T1136 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2728480173 May 02 04:43:52 PM PDT 24 May 02 05:03:26 PM PDT 24 10917752602 ps
T1137 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108844132 May 02 05:04:17 PM PDT 24 May 02 05:10:06 PM PDT 24 3419536606 ps
T1138 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.185985604 May 02 04:46:48 PM PDT 24 May 02 04:49:45 PM PDT 24 2173116424 ps
T1139 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1078616364 May 02 04:47:04 PM PDT 24 May 02 05:04:35 PM PDT 24 5554648480 ps
T1140 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3087687505 May 02 05:01:38 PM PDT 24 May 02 05:11:34 PM PDT 24 5613620184 ps
T1141 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3007993454 May 02 04:53:00 PM PDT 24 May 02 05:04:10 PM PDT 24 4649693440 ps
T1142 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1668006565 May 02 05:08:32 PM PDT 24 May 02 05:17:52 PM PDT 24 5153672500 ps
T1143 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1479706270 May 02 04:46:12 PM PDT 24 May 02 04:54:51 PM PDT 24 4939285348 ps
T1144 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3477799733 May 02 04:41:40 PM PDT 24 May 02 04:45:55 PM PDT 24 3276439469 ps
T1145 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1935780713 May 02 04:40:03 PM PDT 24 May 02 04:48:20 PM PDT 24 4864383095 ps
T1146 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.268304882 May 02 04:41:33 PM PDT 24 May 02 04:51:55 PM PDT 24 5755840120 ps
T1147 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3625876392 May 02 04:43:05 PM PDT 24 May 02 04:48:08 PM PDT 24 3578476656 ps
T702 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134190869 May 02 05:06:23 PM PDT 24 May 02 05:12:50 PM PDT 24 3372552500 ps
T1148 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.344751673 May 02 04:57:29 PM PDT 24 May 02 05:09:31 PM PDT 24 5489492323 ps
T57 /workspace/coverage/default/0.chip_sw_alert_test.3418574472 May 02 04:40:50 PM PDT 24 May 02 04:46:21 PM PDT 24 3633943560 ps
T1149 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2740055958 May 02 04:46:59 PM PDT 24 May 02 05:03:02 PM PDT 24 8738879984 ps
T1150 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.134625266 May 02 04:53:48 PM PDT 24 May 02 05:00:47 PM PDT 24 3070114760 ps
T1151 /workspace/coverage/default/1.chip_sw_power_sleep_load.4158473419 May 02 04:50:59 PM PDT 24 May 02 04:59:53 PM PDT 24 10519531384 ps
T648 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2582370751 May 02 05:02:38 PM PDT 24 May 02 05:08:25 PM PDT 24 3767382704 ps
T1152 /workspace/coverage/default/0.chip_sw_flash_init.42762196 May 02 04:39:20 PM PDT 24 May 02 05:13:34 PM PDT 24 18504265405 ps
T1153 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227520734 May 02 05:05:49 PM PDT 24 May 02 05:12:35 PM PDT 24 3381922812 ps
T235 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3604716923 May 02 04:42:15 PM PDT 24 May 02 04:53:59 PM PDT 24 4747224288 ps
T712 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1886905023 May 02 05:01:59 PM PDT 24 May 02 05:08:28 PM PDT 24 3036476084 ps
T1154 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.545489290 May 02 04:55:45 PM PDT 24 May 02 05:00:44 PM PDT 24 2557566248 ps
T742 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392408758 May 02 05:01:45 PM PDT 24 May 02 05:09:15 PM PDT 24 3827106194 ps
T223 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.501873882 May 02 05:04:16 PM PDT 24 May 02 05:09:42 PM PDT 24 3338652144 ps
T1155 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.535139167 May 02 04:58:04 PM PDT 24 May 02 05:12:18 PM PDT 24 8911012936 ps
T598 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1264953446 May 02 04:56:48 PM PDT 24 May 02 05:19:59 PM PDT 24 5728638440 ps
T1156 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1961693248 May 02 04:57:24 PM PDT 24 May 02 05:25:11 PM PDT 24 21992889845 ps
T1157 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1954223825 May 02 04:58:49 PM PDT 24 May 02 05:03:04 PM PDT 24 3253020395 ps
T1158 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2309637639 May 02 04:58:17 PM PDT 24 May 02 05:02:26 PM PDT 24 2715449952 ps
T1159 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2339357881 May 02 04:47:13 PM PDT 24 May 02 04:51:13 PM PDT 24 2675437880 ps
T1160 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3328108930 May 02 04:54:35 PM PDT 24 May 02 05:02:14 PM PDT 24 5189664472 ps
T1161 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4285866433 May 02 04:56:46 PM PDT 24 May 02 05:27:55 PM PDT 24 8953753224 ps
T1162 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.415640867 May 02 04:40:41 PM PDT 24 May 02 04:49:10 PM PDT 24 3971499518 ps
T1163 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2076459050 May 02 04:45:26 PM PDT 24 May 02 04:52:54 PM PDT 24 6379352176 ps
T1164 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3177706516 May 02 04:52:13 PM PDT 24 May 02 04:57:31 PM PDT 24 2749640208 ps
T1165 /workspace/coverage/default/1.chip_sw_aes_enc.1727103010 May 02 04:49:37 PM PDT 24 May 02 04:54:02 PM PDT 24 2639082960 ps
T1166 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3458487691 May 02 04:55:05 PM PDT 24 May 02 05:02:15 PM PDT 24 3616157840 ps
T1167 /workspace/coverage/default/1.chip_sw_uart_smoketest.828220179 May 02 04:50:54 PM PDT 24 May 02 04:56:45 PM PDT 24 2847633228 ps
T652 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1764584776 May 02 05:08:32 PM PDT 24 May 02 05:17:55 PM PDT 24 4665675260 ps
T717 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810919048 May 02 05:06:10 PM PDT 24 May 02 05:12:31 PM PDT 24 3982029864 ps
T1168 /workspace/coverage/default/0.chip_sw_power_sleep_load.881686141 May 02 04:43:21 PM PDT 24 May 02 04:56:06 PM PDT 24 10515442420 ps
T1169 /workspace/coverage/default/70.chip_sw_all_escalation_resets.991094962 May 02 05:06:00 PM PDT 24 May 02 05:16:11 PM PDT 24 6105468744 ps
T1170 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1349337424 May 02 05:05:58 PM PDT 24 May 02 05:16:34 PM PDT 24 5228015352 ps
T1171 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4291162118 May 02 04:45:40 PM PDT 24 May 02 05:08:01 PM PDT 24 15332726067 ps
T1172 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2480886789 May 02 04:42:46 PM PDT 24 May 02 04:47:26 PM PDT 24 3125394342 ps
T1173 /workspace/coverage/default/2.chip_sw_example_manufacturer.976196671 May 02 04:52:22 PM PDT 24 May 02 04:57:15 PM PDT 24 2959643156 ps
T718 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1091107338 May 02 05:01:53 PM PDT 24 May 02 05:12:19 PM PDT 24 5376527392 ps
T1174 /workspace/coverage/default/2.chip_sw_example_flash.4114513052 May 02 04:51:32 PM PDT 24 May 02 04:55:29 PM PDT 24 2948051658 ps
T173 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2788169365 May 02 04:54:52 PM PDT 24 May 02 04:59:16 PM PDT 24 2751262828 ps
T1175 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1636884077 May 02 04:41:05 PM PDT 24 May 02 05:14:00 PM PDT 24 8329984590 ps
T1176 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1680007355 May 02 04:56:24 PM PDT 24 May 02 05:08:24 PM PDT 24 5462722776 ps
T1177 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3653906429 May 02 04:46:49 PM PDT 24 May 02 04:56:23 PM PDT 24 4536775805 ps
T1178 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3165213356 May 02 04:56:47 PM PDT 24 May 02 05:07:21 PM PDT 24 19499428740 ps
T1179 /workspace/coverage/default/0.chip_sw_example_rom.3578508731 May 02 04:39:38 PM PDT 24 May 02 04:42:01 PM PDT 24 2689714912 ps
T1180 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3394470799 May 02 04:47:01 PM PDT 24 May 02 05:03:34 PM PDT 24 8170901940 ps
T1181 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3947410496 May 02 04:49:14 PM PDT 24 May 02 04:52:19 PM PDT 24 2202180640 ps
T1182 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4054432391 May 02 04:50:37 PM PDT 24 May 02 05:00:43 PM PDT 24 3387673128 ps
T221 /workspace/coverage/default/1.chip_sw_alert_test.3986559060 May 02 04:46:00 PM PDT 24 May 02 04:50:03 PM PDT 24 3300822136 ps
T1183 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.882015010 May 02 04:46:10 PM PDT 24 May 02 04:53:08 PM PDT 24 5036412960 ps
T1184 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.549970233 May 02 04:56:00 PM PDT 24 May 02 05:04:56 PM PDT 24 7328463672 ps
T1185 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.788722328 May 02 04:45:15 PM PDT 24 May 02 05:13:40 PM PDT 24 11693503060 ps
T704 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3510278940 May 02 05:04:47 PM PDT 24 May 02 05:12:29 PM PDT 24 4518282200 ps
T653 /workspace/coverage/default/48.chip_sw_all_escalation_resets.4203345430 May 02 05:05:13 PM PDT 24 May 02 05:13:05 PM PDT 24 3910307060 ps
T1186 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3437289465 May 02 04:55:13 PM PDT 24 May 02 06:13:38 PM PDT 24 45249633828 ps
T1187 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1618882746 May 02 04:41:45 PM PDT 24 May 02 04:46:47 PM PDT 24 3365797747 ps
T1188 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.788472996 May 02 05:01:50 PM PDT 24 May 02 05:25:11 PM PDT 24 7322586848 ps
T174 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2382594216 May 02 05:05:49 PM PDT 24 May 02 05:08:40 PM PDT 24 2962159558 ps
T1189 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4010447503 May 02 04:55:23 PM PDT 24 May 02 05:52:15 PM PDT 24 16872037420 ps
T1190 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055821622 May 02 05:06:27 PM PDT 24 May 02 05:12:55 PM PDT 24 3341140774 ps
T155 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4205320357 May 02 04:39:34 PM PDT 24 May 02 04:49:53 PM PDT 24 5872057460 ps
T1191 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3990665597 May 02 04:46:07 PM PDT 24 May 02 04:51:30 PM PDT 24 3140586892 ps
T74 /workspace/coverage/cover_reg_top/60.xbar_same_source.3370849777 May 02 04:26:30 PM PDT 24 May 02 04:26:41 PM PDT 24 126588827 ps
T75 /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.480448717 May 02 04:19:48 PM PDT 24 May 02 04:21:20 PM PDT 24 8655461474 ps
T76 /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1388074470 May 02 04:23:55 PM PDT 24 May 02 04:52:09 PM PDT 24 93399246280 ps
T80 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1558752360 May 02 04:22:07 PM PDT 24 May 02 04:23:39 PM PDT 24 464892871 ps
T224 /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3942521923 May 02 04:23:43 PM PDT 24 May 02 04:37:43 PM PDT 24 43616933857 ps
T123 /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1907045808 May 02 04:18:37 PM PDT 24 May 02 04:18:50 PM PDT 24 253964297 ps
T122 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3789159198 May 02 04:18:48 PM PDT 24 May 02 04:23:07 PM PDT 24 3585454431 ps
T483 /workspace/coverage/cover_reg_top/67.xbar_smoke.748343245 May 02 04:27:31 PM PDT 24 May 02 04:27:38 PM PDT 24 54144664 ps
T406 /workspace/coverage/cover_reg_top/22.chip_tl_errors.2909644907 May 02 04:20:53 PM PDT 24 May 02 04:23:56 PM PDT 24 3003222349 ps
T387 /workspace/coverage/cover_reg_top/46.xbar_same_source.4039832434 May 02 04:24:33 PM PDT 24 May 02 04:24:50 PM PDT 24 531787407 ps
T456 /workspace/coverage/cover_reg_top/66.xbar_stress_all.3076225026 May 02 04:27:23 PM PDT 24 May 02 04:28:57 PM PDT 24 2555201576 ps
T367 /workspace/coverage/cover_reg_top/57.xbar_stress_all.1520129779 May 02 04:26:04 PM PDT 24 May 02 04:29:21 PM PDT 24 2353362630 ps
T477 /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2844097037 May 02 04:28:45 PM PDT 24 May 02 04:29:00 PM PDT 24 115570025 ps
T487 /workspace/coverage/cover_reg_top/42.xbar_smoke.2528632190 May 02 04:23:57 PM PDT 24 May 02 04:24:06 PM PDT 24 185453470 ps
T485 /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4144234354 May 02 04:21:14 PM PDT 24 May 02 04:21:22 PM PDT 24 48291108 ps
T486 /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.644381131 May 02 04:25:39 PM PDT 24 May 02 04:25:53 PM PDT 24 97148960 ps
T479 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.3277499630 May 02 04:23:38 PM PDT 24 May 02 04:24:17 PM PDT 24 418187337 ps
T531 /workspace/coverage/cover_reg_top/79.xbar_smoke.2587819852 May 02 04:29:10 PM PDT 24 May 02 04:29:16 PM PDT 24 39719361 ps
T404 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4017807898 May 02 04:19:15 PM PDT 24 May 02 04:22:14 PM PDT 24 1697453194 ps
T405 /workspace/coverage/cover_reg_top/21.xbar_error_random.1585507148 May 02 04:20:53 PM PDT 24 May 02 04:21:02 PM PDT 24 176613490 ps
T484 /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1045644351 May 02 04:30:17 PM PDT 24 May 02 04:30:30 PM PDT 24 90521962 ps
T791 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2521718061 May 02 04:22:18 PM PDT 24 May 02 04:22:46 PM PDT 24 69524521 ps
T476 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2367513723 May 02 04:27:01 PM PDT 24 May 02 04:34:14 PM PDT 24 13687700847 ps
T481 /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2408184067 May 02 04:25:37 PM PDT 24 May 02 04:25:59 PM PDT 24 419738029 ps
T1192 /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3825604660 May 02 04:29:50 PM PDT 24 May 02 04:29:57 PM PDT 24 44493541 ps
T390 /workspace/coverage/cover_reg_top/85.xbar_smoke.448765003 May 02 04:29:55 PM PDT 24 May 02 04:30:03 PM PDT 24 49406044 ps
T478 /workspace/coverage/cover_reg_top/72.xbar_error_random.3526876478 May 02 04:28:12 PM PDT 24 May 02 04:28:51 PM PDT 24 461467717 ps
T482 /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.350387421 May 02 04:20:01 PM PDT 24 May 02 04:20:09 PM PDT 24 47863394 ps
T480 /workspace/coverage/cover_reg_top/5.xbar_error_random.2575429374 May 02 04:17:51 PM PDT 24 May 02 04:18:38 PM PDT 24 579619579 ps
T475 /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2051530062 May 02 04:23:42 PM PDT 24 May 02 04:26:45 PM PDT 24 5305269837 ps
T372 /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3391995650 May 02 04:20:18 PM PDT 24 May 02 04:42:51 PM PDT 24 71513306680 ps
T373 /workspace/coverage/cover_reg_top/61.xbar_random.599363569 May 02 04:26:36 PM PDT 24 May 02 04:27:04 PM PDT 24 275893062 ps
T132 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1393285815 May 02 04:17:24 PM PDT 24 May 02 04:23:21 PM PDT 24 6142998672 ps
T530 /workspace/coverage/cover_reg_top/28.xbar_smoke.2317826045 May 02 04:21:59 PM PDT 24 May 02 04:22:06 PM PDT 24 46238053 ps
T554 /workspace/coverage/cover_reg_top/23.xbar_smoke.406331154 May 02 04:21:08 PM PDT 24 May 02 04:21:16 PM PDT 24 149409056 ps
T777 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.3070561288 May 02 04:29:52 PM PDT 24 May 02 04:35:44 PM PDT 24 20253295188 ps
T366 /workspace/coverage/cover_reg_top/73.xbar_stress_all.2450966216 May 02 04:28:24 PM PDT 24 May 02 04:31:04 PM PDT 24 2204843731 ps
T488 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1263592010 May 02 04:19:03 PM PDT 24 May 02 04:27:20 PM PDT 24 7715997834 ps
T1193 /workspace/coverage/cover_reg_top/0.xbar_smoke.3084473349 May 02 04:17:08 PM PDT 24 May 02 04:17:18 PM PDT 24 157293892 ps
T493 /workspace/coverage/cover_reg_top/19.chip_tl_errors.2031588294 May 02 04:20:24 PM PDT 24 May 02 04:23:23 PM PDT 24 3306226920 ps
T563 /workspace/coverage/cover_reg_top/2.xbar_random.1383543150 May 02 04:17:20 PM PDT 24 May 02 04:17:41 PM PDT 24 225291347 ps
T604 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.74579753 May 02 04:25:25 PM PDT 24 May 02 04:32:38 PM PDT 24 3636117768 ps
T585 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.964173374 May 02 04:17:52 PM PDT 24 May 02 04:23:42 PM PDT 24 4190131547 ps
T495 /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1036070402 May 02 04:26:32 PM PDT 24 May 02 04:27:59 PM PDT 24 5058551080 ps
T383 /workspace/coverage/cover_reg_top/53.xbar_stress_all.1685401856 May 02 04:25:36 PM PDT 24 May 02 04:29:06 PM PDT 24 2694082630 ps
T695 /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2399730582 May 02 04:17:31 PM PDT 24 May 02 04:18:38 PM PDT 24 6628709940 ps
T696 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1394828353 May 02 04:29:36 PM PDT 24 May 02 04:38:49 PM PDT 24 14282418372 ps
T821 /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3994010073 May 02 04:24:42 PM PDT 24 May 02 04:26:16 PM PDT 24 8856235428 ps
T519 /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1993991326 May 02 04:20:47 PM PDT 24 May 02 04:32:27 PM PDT 24 73347166653 ps
T1194 /workspace/coverage/cover_reg_top/62.xbar_smoke.1393687771 May 02 04:26:43 PM PDT 24 May 02 04:26:52 PM PDT 24 207928855 ps
T786 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.829228661 May 02 04:26:01 PM PDT 24 May 02 04:33:56 PM PDT 24 3473985551 ps
T467 /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2069694836 May 02 04:20:42 PM PDT 24 May 02 04:31:54 PM PDT 24 39001378702 ps
T546 /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1060055305 May 02 04:20:51 PM PDT 24 May 02 04:21:23 PM PDT 24 810612853 ps
T526 /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.4250328307 May 02 04:29:53 PM PDT 24 May 02 04:38:50 PM PDT 24 30218890770 ps
T468 /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.688369337 May 02 04:18:51 PM PDT 24 May 02 04:19:09 PM PDT 24 180331810 ps
T1195 /workspace/coverage/cover_reg_top/22.xbar_error_random.3562276337 May 02 04:20:58 PM PDT 24 May 02 04:21:30 PM PDT 24 386432145 ps
T395 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2171150263 May 02 04:25:37 PM PDT 24 May 02 04:31:55 PM PDT 24 3422023098 ps
T528 /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1544888124 May 02 04:21:58 PM PDT 24 May 02 04:22:15 PM PDT 24 153387082 ps
T1196 /workspace/coverage/cover_reg_top/65.xbar_error_random.1162887404 May 02 04:27:16 PM PDT 24 May 02 04:27:30 PM PDT 24 132197815 ps
T766 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.868070549 May 02 04:29:24 PM PDT 24 May 02 04:31:27 PM PDT 24 1862000844 ps
T1197 /workspace/coverage/cover_reg_top/59.xbar_random.4176207089 May 02 04:26:21 PM PDT 24 May 02 04:26:32 PM PDT 24 91314859 ps
T457 /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.4135907875 May 02 04:25:30 PM PDT 24 May 02 04:26:06 PM PDT 24 336093961 ps
T454 /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.741514002 May 02 04:24:04 PM PDT 24 May 02 04:25:24 PM PDT 24 4609871578 ps
T489 /workspace/coverage/cover_reg_top/25.chip_tl_errors.553977356 May 02 04:21:21 PM PDT 24 May 02 04:26:56 PM PDT 24 4660467256 ps
T503 /workspace/coverage/cover_reg_top/71.xbar_random.3644254665 May 02 04:27:56 PM PDT 24 May 02 04:29:06 PM PDT 24 2046375733 ps
T470 /workspace/coverage/cover_reg_top/82.xbar_random.1924184405 May 02 04:29:33 PM PDT 24 May 02 04:29:49 PM PDT 24 161029465 ps
T384 /workspace/coverage/cover_reg_top/90.xbar_stress_all.1570730689 May 02 04:30:47 PM PDT 24 May 02 04:36:54 PM PDT 24 4426101254 ps
T385 /workspace/coverage/cover_reg_top/18.xbar_stress_all.4195652017 May 02 04:20:18 PM PDT 24 May 02 04:25:48 PM PDT 24 8143337697 ps
T511 /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.833829983 May 02 04:22:53 PM PDT 24 May 02 04:23:01 PM PDT 24 58480787 ps
T763 /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.857352938 May 02 04:31:58 PM PDT 24 May 02 05:11:58 PM PDT 24 122121032826 ps
T1198 /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1720008132 May 02 04:17:25 PM PDT 24 May 02 04:17:55 PM PDT 24 268934915 ps
T762 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3875723829 May 02 04:28:45 PM PDT 24 May 02 04:48:23 PM PDT 24 62798790994 ps
T469 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.267227728 May 02 04:31:51 PM PDT 24 May 02 04:45:18 PM PDT 24 44603967870 ps
T514 /workspace/coverage/cover_reg_top/52.xbar_random.153465649 May 02 04:25:18 PM PDT 24 May 02 04:26:26 PM PDT 24 2147134508 ps
T551 /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1702910207 May 02 04:27:02 PM PDT 24 May 02 04:29:04 PM PDT 24 11600556142 ps
T388 /workspace/coverage/cover_reg_top/1.xbar_stress_all.3982129856 May 02 04:17:25 PM PDT 24 May 02 04:22:32 PM PDT 24 8111831949 ps
T1199 /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1011437325 May 02 04:18:22 PM PDT 24 May 02 04:18:28 PM PDT 24 39751516 ps
T433 /workspace/coverage/cover_reg_top/50.xbar_random.2890750472 May 02 04:25:00 PM PDT 24 May 02 04:25:31 PM PDT 24 779823146 ps
T408 /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2474872620 May 02 04:19:50 PM PDT 24 May 02 04:19:56 PM PDT 24 47876340 ps
T587 /workspace/coverage/cover_reg_top/45.xbar_same_source.504051003 May 02 04:24:25 PM PDT 24 May 02 04:25:07 PM PDT 24 1379853557 ps
T428 /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3575102442 May 02 04:29:42 PM PDT 24 May 02 04:29:51 PM PDT 24 36008052 ps
T516 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2554165119 May 02 04:23:58 PM PDT 24 May 02 04:27:30 PM PDT 24 5022003166 ps
T512 /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3591532902 May 02 04:27:37 PM PDT 24 May 02 04:29:26 PM PDT 24 6477840161 ps
T386 /workspace/coverage/cover_reg_top/91.xbar_stress_all.406763534 May 02 04:30:49 PM PDT 24 May 02 04:35:51 PM PDT 24 3959447115 ps
T578 /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.617302850 May 02 04:20:46 PM PDT 24 May 02 04:21:02 PM PDT 24 161022900 ps
T389 /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.556495827 May 02 04:18:01 PM PDT 24 May 02 04:28:51 PM PDT 24 56225448018 ps
T583 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.161636836 May 02 04:29:47 PM PDT 24 May 02 04:30:51 PM PDT 24 5831448015 ps
T569 /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1340643764 May 02 04:27:44 PM PDT 24 May 02 04:28:00 PM PDT 24 137667045 ps
T1200 /workspace/coverage/cover_reg_top/48.xbar_smoke.722142853 May 02 04:24:43 PM PDT 24 May 02 04:24:50 PM PDT 24 47921400 ps
T425 /workspace/coverage/cover_reg_top/81.xbar_stress_all.1201594431 May 02 04:29:25 PM PDT 24 May 02 04:36:30 PM PDT 24 10195328536 ps
T382 /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1982467581 May 02 04:21:59 PM PDT 24 May 02 04:23:22 PM PDT 24 2151889979 ps
T553 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3765893879 May 02 04:29:42 PM PDT 24 May 02 04:33:40 PM PDT 24 477205577 ps
T416 /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.772194134 May 02 04:24:16 PM PDT 24 May 02 04:24:38 PM PDT 24 242114816 ps
T782 /workspace/coverage/cover_reg_top/47.xbar_access_same_device.3517070940 May 02 04:24:40 PM PDT 24 May 02 04:25:30 PM PDT 24 585389034 ps
T1201 /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1808604626 May 02 04:27:06 PM PDT 24 May 02 04:29:36 PM PDT 24 7959760650 ps
T420 /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1887458894 May 02 04:20:16 PM PDT 24 May 02 04:40:56 PM PDT 24 66137456128 ps
T490 /workspace/coverage/cover_reg_top/10.chip_tl_errors.2881821348 May 02 04:18:42 PM PDT 24 May 02 04:23:02 PM PDT 24 3536983906 ps
T1202 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.929628407 May 02 04:23:27 PM PDT 24 May 02 04:24:43 PM PDT 24 1010556674 ps
T412 /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1801957198 May 02 04:23:08 PM PDT 24 May 02 04:54:53 PM PDT 24 102209955693 ps
T142 /workspace/coverage/cover_reg_top/0.chip_csr_rw.2166754560 May 02 04:17:10 PM PDT 24 May 02 04:22:48 PM PDT 24 3680468699 ps
T1203 /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.287378635 May 02 04:24:30 PM PDT 24 May 02 04:25:20 PM PDT 24 4285277874 ps
T773 /workspace/coverage/cover_reg_top/58.xbar_access_same_device.486056194 May 02 04:26:14 PM PDT 24 May 02 04:28:02 PM PDT 24 2161958537 ps
T501 /workspace/coverage/cover_reg_top/30.xbar_same_source.4115029503 May 02 04:22:19 PM PDT 24 May 02 04:22:38 PM PDT 24 237904527 ps
T757 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2190032166 May 02 04:22:33 PM PDT 24 May 02 04:25:27 PM PDT 24 2571211826 ps
T1204 /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.4094759953 May 02 04:22:32 PM PDT 24 May 02 04:22:40 PM PDT 24 41731420 ps
T775 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2599242990 May 02 04:23:51 PM PDT 24 May 02 04:30:55 PM PDT 24 3986786051 ps
T127 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4281250187 May 02 04:17:10 PM PDT 24 May 02 04:21:21 PM PDT 24 4937422552 ps
T1205 /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.537491080 May 02 04:20:45 PM PDT 24 May 02 04:20:51 PM PDT 24 42336764 ps
T1206 /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1281202812 May 02 04:30:42 PM PDT 24 May 02 04:30:52 PM PDT 24 143022537 ps
T1207 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2321887297 May 02 04:31:31 PM PDT 24 May 02 04:32:01 PM PDT 24 261686444 ps
T333 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1317856596 May 02 04:17:40 PM PDT 24 May 02 04:38:01 PM PDT 24 13515997450 ps
T1208 /workspace/coverage/cover_reg_top/19.xbar_error_random.3824445447 May 02 04:20:22 PM PDT 24 May 02 04:21:37 PM PDT 24 2024620677 ps
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