Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.32	94.12	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	737962676	3016	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	737962676	3016	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	3016	0	0
T1	281555	2	0	0
T2	160451	2	0	0
T3	268100	4	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	4	0	0
T35	91420	0	0	0
T44	35585	0	0	0
T59	519167	4	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	2	0	0
T110	0	1	0	0
T162	83141	4	0	0
T163	0	4	0	0
T165	0	8	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T275	0	6	0	0
T276	0	4	0	0
T277	0	10	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	3016	0	0
T1	281555	2	0	0
T2	160451	2	0	0
T3	268100	4	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	4	0	0
T35	91420	0	0	0
T44	35585	0	0	0
T59	519167	4	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	2	0	0
T110	0	1	0	0
T162	83141	4	0	0
T163	0	4	0	0
T165	0	8	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T275	0	6	0	0
T276	0	4	0	0
T277	0	10	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	368981338	36	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	368981338	36	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	36	0	0
T35	91420	0	0	0
T162	83141	4	0	0
T163	0	4	0	0
T165	0	8	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T275	0	6	0	0
T276	0	4	0	0
T277	0	10	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	36	0	0
T35	91420	0	0	0
T162	83141	4	0	0
T163	0	4	0	0
T165	0	8	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T275	0	6	0	0
T276	0	4	0	0
T277	0	10	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	368981338	2980	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	368981338	2980	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	2980	0	0
T1	281555	2	0	0
T2	160451	2	0	0
T3	268100	4	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	4	0	0
T44	35585	0	0	0
T59	519167	4	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	2	0	0
T110	0	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	2980	0	0
T1	281555	2	0	0
T2	160451	2	0	0
T3	268100	4	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	4	0	0
T44	35585	0	0	0
T59	519167	4	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	2	0	0
T110	0	1	0	0