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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.32 93.72 95.59 94.49 97.38 99.52


Total test records in report: 2762
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T899 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1270389927 May 05 04:50:12 PM PDT 24 May 05 05:10:42 PM PDT 24 7842078330 ps
T505 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3623412760 May 05 04:31:47 PM PDT 24 May 05 04:53:51 PM PDT 24 9609077820 ps
T900 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2079503959 May 05 04:22:49 PM PDT 24 May 05 04:31:27 PM PDT 24 4894958845 ps
T901 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1506046615 May 05 04:24:27 PM PDT 24 May 05 04:30:56 PM PDT 24 3470172571 ps
T350 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.952867751 May 05 04:50:42 PM PDT 24 May 05 04:56:06 PM PDT 24 2935288904 ps
T164 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2432368280 May 05 04:32:19 PM PDT 24 May 05 04:44:05 PM PDT 24 9105173881 ps
T231 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269070544 May 05 04:53:25 PM PDT 24 May 05 04:59:42 PM PDT 24 3857090774 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2824436252 May 05 04:21:04 PM PDT 24 May 05 04:26:15 PM PDT 24 3409854461 ps
T902 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3083344358 May 05 04:39:04 PM PDT 24 May 05 04:49:50 PM PDT 24 3225409452 ps
T22 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3385103662 May 05 04:23:18 PM PDT 24 May 05 05:20:51 PM PDT 24 19998133030 ps
T903 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3225404143 May 05 04:27:10 PM PDT 24 May 05 04:31:49 PM PDT 24 5358262120 ps
T55 /workspace/coverage/default/1.chip_sw_alert_test.2701784610 May 05 04:34:08 PM PDT 24 May 05 04:38:24 PM PDT 24 2678014476 ps
T791 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1441401682 May 05 04:48:26 PM PDT 24 May 05 04:57:31 PM PDT 24 4651757772 ps
T348 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1206042739 May 05 04:39:47 PM PDT 24 May 05 04:44:21 PM PDT 24 2476542554 ps
T106 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2974394277 May 05 04:35:37 PM PDT 24 May 05 05:21:43 PM PDT 24 21558970573 ps
T197 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3609949597 May 05 04:31:20 PM PDT 24 May 05 05:05:17 PM PDT 24 9864298968 ps
T904 /workspace/coverage/default/0.chip_sw_uart_tx_rx.4125273296 May 05 04:21:18 PM PDT 24 May 05 04:32:18 PM PDT 24 3555417830 ps
T905 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2336009819 May 05 04:26:14 PM PDT 24 May 05 04:32:20 PM PDT 24 3319370220 ps
T224 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2062151886 May 05 04:45:25 PM PDT 24 May 05 04:49:55 PM PDT 24 3159632556 ps
T906 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4217437813 May 05 04:30:56 PM PDT 24 May 05 04:34:42 PM PDT 24 2770043146 ps
T247 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2646903235 May 05 04:27:26 PM PDT 24 May 05 04:29:50 PM PDT 24 2842019913 ps
T371 /workspace/coverage/default/0.chip_sw_usbdev_stream.965738364 May 05 04:23:01 PM PDT 24 May 05 05:30:41 PM PDT 24 19111358908 ps
T907 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2923660907 May 05 04:24:19 PM PDT 24 May 05 04:28:22 PM PDT 24 3129583060 ps
T908 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2355246600 May 05 04:37:31 PM PDT 24 May 05 04:43:10 PM PDT 24 3324517520 ps
T909 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2463204284 May 05 04:24:58 PM PDT 24 May 05 04:30:32 PM PDT 24 2496727978 ps
T910 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1856622216 May 05 04:24:29 PM PDT 24 May 05 04:46:51 PM PDT 24 6199709996 ps
T772 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1110408908 May 05 04:56:29 PM PDT 24 May 05 05:02:10 PM PDT 24 3671420692 ps
T218 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3670082921 May 05 04:53:18 PM PDT 24 May 05 05:01:13 PM PDT 24 4226907816 ps
T267 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533954266 May 05 04:45:37 PM PDT 24 May 05 04:52:11 PM PDT 24 4015183572 ps
T165 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2436865228 May 05 04:22:50 PM PDT 24 May 05 04:27:47 PM PDT 24 2932614647 ps
T268 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1955057104 May 05 04:27:48 PM PDT 24 May 05 04:31:55 PM PDT 24 2931378360 ps
T269 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3496438694 May 05 04:40:53 PM PDT 24 May 05 04:44:18 PM PDT 24 2552539360 ps
T270 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3438891305 May 05 04:54:14 PM PDT 24 May 05 05:01:03 PM PDT 24 4484000984 ps
T271 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009708579 May 05 04:53:17 PM PDT 24 May 05 05:00:13 PM PDT 24 3561906152 ps
T272 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3902027624 May 05 04:42:46 PM PDT 24 May 05 04:52:00 PM PDT 24 3963913714 ps
T273 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.471043519 May 05 04:45:56 PM PDT 24 May 05 05:01:17 PM PDT 24 9636374610 ps
T274 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2029770885 May 05 04:38:27 PM PDT 24 May 05 04:47:41 PM PDT 24 7262958204 ps
T911 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.128442634 May 05 04:46:04 PM PDT 24 May 05 04:54:09 PM PDT 24 3644197500 ps
T199 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.321783129 May 05 04:44:09 PM PDT 24 May 05 05:11:24 PM PDT 24 8867977400 ps
T793 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3500602907 May 05 04:53:34 PM PDT 24 May 05 05:03:19 PM PDT 24 4987297400 ps
T912 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.398332873 May 05 04:32:51 PM PDT 24 May 05 04:56:15 PM PDT 24 11261045896 ps
T166 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.166707979 May 05 04:20:37 PM PDT 24 May 05 05:41:18 PM PDT 24 44076934464 ps
T913 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3764611984 May 05 04:23:06 PM PDT 24 May 05 04:27:23 PM PDT 24 3019349268 ps
T126 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.195309318 May 05 04:41:28 PM PDT 24 May 05 04:56:11 PM PDT 24 5783384490 ps
T914 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3398093877 May 05 04:44:17 PM PDT 24 May 05 04:47:29 PM PDT 24 2369377120 ps
T249 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4275146122 May 05 04:31:58 PM PDT 24 May 05 04:40:29 PM PDT 24 8274952343 ps
T763 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171983352 May 05 04:53:37 PM PDT 24 May 05 05:00:33 PM PDT 24 3640001562 ps
T364 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3598008410 May 05 04:23:02 PM PDT 24 May 05 04:41:48 PM PDT 24 5289040056 ps
T915 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2668310416 May 05 04:33:00 PM PDT 24 May 05 04:42:04 PM PDT 24 6422380933 ps
T305 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2756454729 May 05 04:28:25 PM PDT 24 May 05 04:38:36 PM PDT 24 4892768960 ps
T331 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2439081202 May 05 04:29:40 PM PDT 24 May 05 04:39:37 PM PDT 24 4413840720 ps
T916 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2848378070 May 05 04:37:47 PM PDT 24 May 05 04:43:10 PM PDT 24 2899800238 ps
T917 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3983863254 May 05 04:38:00 PM PDT 24 May 05 04:44:46 PM PDT 24 3544588376 ps
T918 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2657940328 May 05 04:39:11 PM PDT 24 May 05 05:24:27 PM PDT 24 18699559667 ps
T149 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3572638101 May 05 04:22:51 PM PDT 24 May 05 04:32:26 PM PDT 24 5215699918 ps
T919 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3717784379 May 05 04:30:10 PM PDT 24 May 05 04:51:06 PM PDT 24 5821605834 ps
T920 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3660791784 May 05 04:32:24 PM PDT 24 May 05 04:42:56 PM PDT 24 4474826578 ps
T921 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4076178280 May 05 04:41:09 PM PDT 24 May 05 04:49:49 PM PDT 24 3809090630 ps
T337 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3532799673 May 05 04:45:49 PM PDT 24 May 05 04:53:49 PM PDT 24 5009715524 ps
T324 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2722266834 May 05 04:25:45 PM PDT 24 May 05 04:29:34 PM PDT 24 2322127921 ps
T318 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2908104476 May 05 04:48:09 PM PDT 24 May 05 05:10:23 PM PDT 24 8208286272 ps
T737 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287400749 May 05 04:52:49 PM PDT 24 May 05 04:59:42 PM PDT 24 3527875432 ps
T66 /workspace/coverage/default/1.chip_tap_straps_rma.2471590480 May 05 04:34:09 PM PDT 24 May 05 04:43:04 PM PDT 24 6048635114 ps
T202 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.306235589 May 05 04:23:14 PM PDT 24 May 05 05:21:46 PM PDT 24 13300847880 ps
T338 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.12594944 May 05 04:53:24 PM PDT 24 May 05 04:58:10 PM PDT 24 3448468600 ps
T922 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2966747547 May 05 04:23:47 PM PDT 24 May 05 04:29:00 PM PDT 24 2837821324 ps
T306 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.426961157 May 05 04:26:46 PM PDT 24 May 05 04:39:37 PM PDT 24 4662360336 ps
T923 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2539529290 May 05 04:33:49 PM PDT 24 May 05 04:41:28 PM PDT 24 3404370974 ps
T63 /workspace/coverage/default/2.chip_tap_straps_rma.2127522168 May 05 04:41:06 PM PDT 24 May 05 04:57:42 PM PDT 24 9939828392 ps
T47 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3939876950 May 05 04:23:29 PM PDT 24 May 05 04:50:54 PM PDT 24 22414778912 ps
T388 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4121823461 May 05 04:32:49 PM PDT 24 May 05 04:47:06 PM PDT 24 6162231772 ps
T389 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3344202358 May 05 04:25:12 PM PDT 24 May 05 04:45:54 PM PDT 24 6268864503 ps
T390 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3680667097 May 05 04:51:48 PM PDT 24 May 05 05:03:03 PM PDT 24 5231204584 ps
T391 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2181879756 May 05 04:24:15 PM PDT 24 May 05 04:42:34 PM PDT 24 5672617040 ps
T392 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.100084581 May 05 04:39:38 PM PDT 24 May 05 04:46:09 PM PDT 24 4241290160 ps
T393 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.116554037 May 05 04:22:54 PM PDT 24 May 05 04:36:46 PM PDT 24 18518009750 ps
T394 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3961723909 May 05 04:23:29 PM PDT 24 May 05 04:32:48 PM PDT 24 5258758406 ps
T204 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3852643726 May 05 04:21:36 PM PDT 24 May 05 05:50:54 PM PDT 24 49048762812 ps
T343 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3419318232 May 05 04:54:55 PM PDT 24 May 05 05:05:10 PM PDT 24 4949375168 ps
T924 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.741320086 May 05 04:37:47 PM PDT 24 May 05 04:42:59 PM PDT 24 2929151086 ps
T48 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.857195519 May 05 04:25:32 PM PDT 24 May 05 04:32:07 PM PDT 24 7619153848 ps
T925 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4036605739 May 05 04:42:33 PM PDT 24 May 05 04:53:10 PM PDT 24 4894822792 ps
T667 /workspace/coverage/default/1.chip_sw_edn_kat.3473985642 May 05 04:30:47 PM PDT 24 May 05 04:39:56 PM PDT 24 3494419560 ps
T219 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1261801876 May 05 04:52:50 PM PDT 24 May 05 05:03:53 PM PDT 24 4878945328 ps
T926 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.627294190 May 05 04:38:21 PM PDT 24 May 05 04:45:21 PM PDT 24 6246392802 ps
T927 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2062283574 May 05 04:32:36 PM PDT 24 May 05 04:40:38 PM PDT 24 4653602344 ps
T325 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1818404183 May 05 04:37:09 PM PDT 24 May 05 04:46:35 PM PDT 24 3492345502 ps
T928 /workspace/coverage/default/1.chip_sw_example_rom.234388082 May 05 04:28:41 PM PDT 24 May 05 04:30:34 PM PDT 24 2476065720 ps
T353 /workspace/coverage/default/0.chip_sw_all_escalation_resets.4187084112 May 05 04:21:07 PM PDT 24 May 05 04:31:27 PM PDT 24 5046273168 ps
T782 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4112982840 May 05 04:50:34 PM PDT 24 May 05 04:57:33 PM PDT 24 3288482720 ps
T756 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3440854851 May 05 04:49:54 PM PDT 24 May 05 04:56:08 PM PDT 24 3452186238 ps
T259 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.563050757 May 05 04:24:48 PM PDT 24 May 05 04:33:26 PM PDT 24 6554239200 ps
T178 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3728295835 May 05 04:27:34 PM PDT 24 May 05 04:43:10 PM PDT 24 6080935050 ps
T929 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3892303402 May 05 04:28:51 PM PDT 24 May 05 04:35:37 PM PDT 24 7324375586 ps
T665 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3279559141 May 05 04:30:23 PM PDT 24 May 05 04:46:17 PM PDT 24 4392464896 ps
T930 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1415303208 May 05 04:23:34 PM PDT 24 May 05 04:33:18 PM PDT 24 4989076000 ps
T287 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1002404255 May 05 04:23:09 PM PDT 24 May 05 04:51:53 PM PDT 24 7930686348 ps
T207 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1581615320 May 05 04:37:56 PM PDT 24 May 05 06:14:57 PM PDT 24 46660591488 ps
T792 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2668252374 May 05 04:48:36 PM PDT 24 May 05 04:54:00 PM PDT 24 3175029560 ps
T931 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3662406098 May 05 04:27:34 PM PDT 24 May 05 04:30:56 PM PDT 24 2307541344 ps
T681 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1245076 May 05 04:43:22 PM PDT 24 May 05 04:54:03 PM PDT 24 5179284516 ps
T311 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2389019411 May 05 04:29:13 PM PDT 24 May 05 04:40:07 PM PDT 24 3647547954 ps
T932 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1516795277 May 05 04:44:45 PM PDT 24 May 05 04:53:46 PM PDT 24 3968674540 ps
T933 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3975967549 May 05 04:30:56 PM PDT 24 May 05 04:44:25 PM PDT 24 5373641851 ps
T934 /workspace/coverage/default/2.chip_sw_aes_smoketest.3904463677 May 05 04:43:23 PM PDT 24 May 05 04:48:01 PM PDT 24 3009306104 ps
T205 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.713767689 May 05 04:37:42 PM PDT 24 May 05 06:09:26 PM PDT 24 45300455597 ps
T935 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1699821101 May 05 04:38:04 PM PDT 24 May 05 04:52:33 PM PDT 24 11215592444 ps
T936 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2310229230 May 05 04:20:29 PM PDT 24 May 05 05:06:00 PM PDT 24 19180813946 ps
T134 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2595977201 May 05 04:45:39 PM PDT 24 May 05 04:54:37 PM PDT 24 3916287368 ps
T79 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2767043655 May 05 04:22:19 PM PDT 24 May 05 04:44:17 PM PDT 24 12056969360 ps
T85 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2075792037 May 05 04:51:03 PM PDT 24 May 05 05:03:21 PM PDT 24 6464923496 ps
T290 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.291720061 May 05 04:50:36 PM PDT 24 May 05 04:57:30 PM PDT 24 3075942280 ps
T75 /workspace/coverage/default/2.chip_jtag_csr_rw.1485769267 May 05 04:34:25 PM PDT 24 May 05 04:52:22 PM PDT 24 10196076097 ps
T323 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4057274197 May 05 04:38:23 PM PDT 24 May 05 04:50:50 PM PDT 24 4516282289 ps
T703 /workspace/coverage/default/61.chip_sw_all_escalation_resets.870322299 May 05 04:52:17 PM PDT 24 May 05 05:02:02 PM PDT 24 4410769090 ps
T248 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1847204827 May 05 04:23:23 PM PDT 24 May 05 04:25:22 PM PDT 24 2181263512 ps
T937 /workspace/coverage/default/0.chip_sw_aes_smoketest.815802419 May 05 04:26:00 PM PDT 24 May 05 04:30:19 PM PDT 24 3330264072 ps
T312 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2144310251 May 05 04:26:25 PM PDT 24 May 05 04:40:14 PM PDT 24 4419413388 ps
T938 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1552206577 May 05 04:22:15 PM PDT 24 May 05 04:33:27 PM PDT 24 6162531524 ps
T939 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4207827154 May 05 04:27:20 PM PDT 24 May 05 04:41:07 PM PDT 24 5132590864 ps
T940 /workspace/coverage/default/0.chip_sw_aes_enc.628399970 May 05 04:23:15 PM PDT 24 May 05 04:28:23 PM PDT 24 2224464124 ps
T50 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.56110619 May 05 04:37:04 PM PDT 24 May 05 04:42:27 PM PDT 24 3187600868 ps
T260 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.393660514 May 05 04:25:59 PM PDT 24 May 05 04:34:33 PM PDT 24 3905963300 ps
T381 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1208293917 May 05 04:30:14 PM PDT 24 May 05 04:36:06 PM PDT 24 4684081376 ps
T137 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4109849880 May 05 04:28:16 PM PDT 24 May 05 04:36:23 PM PDT 24 9426644959 ps
T283 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1118471231 May 05 04:40:38 PM PDT 24 May 05 04:57:02 PM PDT 24 9403746559 ps
T382 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1277182058 May 05 04:38:47 PM PDT 24 May 05 04:49:11 PM PDT 24 3844211900 ps
T383 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2323185340 May 05 04:48:33 PM PDT 24 May 05 05:12:57 PM PDT 24 8556988352 ps
T150 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1034641952 May 05 04:23:56 PM PDT 24 May 05 07:56:01 PM PDT 24 254663708578 ps
T384 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2145120593 May 05 04:39:32 PM PDT 24 May 05 05:34:48 PM PDT 24 17045293000 ps
T385 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2914380341 May 05 04:37:16 PM PDT 24 May 05 04:42:28 PM PDT 24 3301723050 ps
T761 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3894115103 May 05 04:52:18 PM PDT 24 May 05 04:58:14 PM PDT 24 3990921684 ps
T37 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.467908568 May 05 04:25:32 PM PDT 24 May 05 04:29:56 PM PDT 24 2716873702 ps
T941 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1719440320 May 05 04:48:52 PM PDT 24 May 05 05:21:24 PM PDT 24 13143265268 ps
T942 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1483890002 May 05 04:47:41 PM PDT 24 May 05 05:08:26 PM PDT 24 7697004880 ps
T185 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.5870103 May 05 04:21:21 PM PDT 24 May 05 07:52:41 PM PDT 24 77564151699 ps
T738 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426189359 May 05 04:48:01 PM PDT 24 May 05 04:55:06 PM PDT 24 4170703992 ps
T943 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.641976660 May 05 04:34:43 PM PDT 24 May 05 04:54:23 PM PDT 24 6954195004 ps
T728 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3323441134 May 05 04:53:25 PM PDT 24 May 05 05:01:01 PM PDT 24 5541368616 ps
T944 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1107488771 May 05 04:22:48 PM PDT 24 May 05 04:27:46 PM PDT 24 3066800000 ps
T945 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1006950972 May 05 04:22:46 PM PDT 24 May 05 04:26:25 PM PDT 24 2558622816 ps
T261 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.608960018 May 05 04:31:46 PM PDT 24 May 05 04:40:55 PM PDT 24 4051659046 ps
T685 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2056392831 May 05 04:27:56 PM PDT 24 May 05 04:29:53 PM PDT 24 2426115065 ps
T729 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.441934101 May 05 04:52:58 PM PDT 24 May 05 04:59:03 PM PDT 24 3552737480 ps
T946 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3537093935 May 05 04:27:51 PM PDT 24 May 05 04:31:42 PM PDT 24 3161187492 ps
T76 /workspace/coverage/default/1.chip_jtag_mem_access.1824754825 May 05 04:26:18 PM PDT 24 May 05 04:58:10 PM PDT 24 13371045934 ps
T179 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3491543422 May 05 04:38:58 PM PDT 24 May 05 04:53:02 PM PDT 24 5071389000 ps
T947 /workspace/coverage/default/1.chip_sw_aes_smoketest.1132265285 May 05 04:38:36 PM PDT 24 May 05 04:42:47 PM PDT 24 2778903122 ps
T686 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1624135364 May 05 04:38:06 PM PDT 24 May 05 04:40:08 PM PDT 24 2654543600 ps
T948 /workspace/coverage/default/1.chip_sw_aes_idle.2151993446 May 05 04:32:45 PM PDT 24 May 05 04:36:07 PM PDT 24 2454260960 ps
T949 /workspace/coverage/default/0.chip_sw_csrng_smoketest.2087387296 May 05 04:26:00 PM PDT 24 May 05 04:29:05 PM PDT 24 2738657390 ps
T950 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1912627985 May 05 04:37:23 PM PDT 24 May 05 08:26:58 PM PDT 24 77955336731 ps
T951 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1312026093 May 05 04:27:13 PM PDT 24 May 05 04:39:07 PM PDT 24 6895511369 ps
T952 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3361071313 May 05 04:30:26 PM PDT 24 May 05 04:33:49 PM PDT 24 2436533296 ps
T953 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3156900005 May 05 04:37:23 PM PDT 24 May 05 04:49:04 PM PDT 24 4114162184 ps
T954 /workspace/coverage/default/2.chip_sw_kmac_entropy.147149590 May 05 04:38:43 PM PDT 24 May 05 04:43:29 PM PDT 24 2605498732 ps
T955 /workspace/coverage/default/0.rom_keymgr_functest.1983138668 May 05 04:26:38 PM PDT 24 May 05 04:34:28 PM PDT 24 3926985430 ps
T308 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.737954743 May 05 04:41:00 PM PDT 24 May 05 05:05:28 PM PDT 24 5802695128 ps
T407 /workspace/coverage/default/37.chip_sw_all_escalation_resets.252690817 May 05 04:51:04 PM PDT 24 May 05 05:00:34 PM PDT 24 6019551364 ps
T956 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.507000921 May 05 04:39:33 PM PDT 24 May 05 04:58:46 PM PDT 24 5479490288 ps
T369 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3279974937 May 05 04:26:28 PM PDT 24 May 05 04:33:31 PM PDT 24 5000474112 ps
T957 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2713628115 May 05 04:30:14 PM PDT 24 May 05 04:45:35 PM PDT 24 5876761554 ps
T77 /workspace/coverage/default/1.chip_jtag_csr_rw.2825507622 May 05 04:26:06 PM PDT 24 May 05 04:47:10 PM PDT 24 10706464505 ps
T746 /workspace/coverage/default/36.chip_sw_all_escalation_resets.712307795 May 05 04:49:02 PM PDT 24 May 05 05:01:29 PM PDT 24 5907366840 ps
T958 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2462127649 May 05 04:47:42 PM PDT 24 May 05 04:54:54 PM PDT 24 3410182990 ps
T959 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4118584711 May 05 04:48:25 PM PDT 24 May 05 05:07:49 PM PDT 24 8423083670 ps
T960 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3926618381 May 05 04:36:00 PM PDT 24 May 05 04:55:46 PM PDT 24 5875171566 ps
T758 /workspace/coverage/default/30.chip_sw_all_escalation_resets.4161101805 May 05 04:48:18 PM PDT 24 May 05 04:59:14 PM PDT 24 5159706060 ps
T759 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3139623332 May 05 04:47:14 PM PDT 24 May 05 04:59:29 PM PDT 24 4323832728 ps
T215 /workspace/coverage/default/47.chip_sw_all_escalation_resets.1483571308 May 05 04:50:16 PM PDT 24 May 05 05:01:20 PM PDT 24 5643184932 ps
T961 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3949290967 May 05 04:37:21 PM PDT 24 May 05 04:43:45 PM PDT 24 4967018024 ps
T776 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1709031786 May 05 04:51:02 PM PDT 24 May 05 05:01:37 PM PDT 24 5994258144 ps
T962 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.281419551 May 05 04:26:51 PM PDT 24 May 05 04:53:08 PM PDT 24 8721518456 ps
T757 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3111135297 May 05 04:52:59 PM PDT 24 May 05 04:58:31 PM PDT 24 3699078554 ps
T731 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3997284240 May 05 04:41:20 PM PDT 24 May 05 04:47:39 PM PDT 24 3597755368 ps
T129 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4076447970 May 05 04:32:39 PM PDT 24 May 05 04:52:11 PM PDT 24 8731271858 ps
T704 /workspace/coverage/default/29.chip_sw_all_escalation_resets.342978917 May 05 04:48:28 PM PDT 24 May 05 04:59:13 PM PDT 24 4926461896 ps
T963 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2763994804 May 05 04:35:23 PM PDT 24 May 05 04:38:47 PM PDT 24 2732066416 ps
T964 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2603383550 May 05 04:27:43 PM PDT 24 May 05 05:02:19 PM PDT 24 8156002080 ps
T730 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223399065 May 05 04:47:43 PM PDT 24 May 05 04:55:33 PM PDT 24 3955925448 ps
T965 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.95858046 May 05 04:23:20 PM PDT 24 May 05 05:14:00 PM PDT 24 11901269960 ps
T43 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3884914862 May 05 04:23:14 PM PDT 24 May 05 04:29:38 PM PDT 24 2683513404 ps
T966 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1705105775 May 05 04:25:16 PM PDT 24 May 05 04:40:04 PM PDT 24 7561371270 ps
T967 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.86892544 May 05 04:27:56 PM PDT 24 May 05 04:40:51 PM PDT 24 4130967813 ps
T968 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.258956734 May 05 04:43:30 PM PDT 24 May 05 04:46:59 PM PDT 24 3316208067 ps
T228 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1596675354 May 05 04:43:05 PM PDT 24 May 05 04:54:30 PM PDT 24 5115655476 ps
T734 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2953085406 May 05 04:48:37 PM PDT 24 May 05 05:01:54 PM PDT 24 4478847724 ps
T298 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1827355184 May 05 04:22:22 PM PDT 24 May 05 04:45:06 PM PDT 24 11053488840 ps
T969 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1429164736 May 05 04:38:56 PM PDT 24 May 05 04:49:15 PM PDT 24 4366142344 ps
T262 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.469417840 May 05 04:41:20 PM PDT 24 May 05 04:51:17 PM PDT 24 3684507654 ps
T970 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.362662587 May 05 04:46:23 PM PDT 24 May 05 04:57:24 PM PDT 24 3905814008 ps
T971 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.903871857 May 05 04:40:09 PM PDT 24 May 05 04:53:03 PM PDT 24 6048673368 ps
T702 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1609501256 May 05 04:34:03 PM PDT 24 May 05 05:07:41 PM PDT 24 7363229000 ps
T972 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3428409292 May 05 04:47:10 PM PDT 24 May 05 04:51:18 PM PDT 24 2991846584 ps
T973 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1890375412 May 05 04:38:53 PM PDT 24 May 05 04:58:33 PM PDT 24 9945264886 ps
T974 /workspace/coverage/default/1.chip_sw_otbn_randomness.2041025306 May 05 04:29:53 PM PDT 24 May 05 04:45:11 PM PDT 24 6606450626 ps
T39 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2242203000 May 05 04:31:02 PM PDT 24 May 05 04:41:29 PM PDT 24 4732164576 ps
T193 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3940554015 May 05 04:37:34 PM PDT 24 May 05 04:52:44 PM PDT 24 7644292355 ps
T372 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1601869425 May 05 04:43:32 PM PDT 24 May 05 04:50:44 PM PDT 24 4487587640 ps
T975 /workspace/coverage/default/1.chip_tap_straps_prod.3938067834 May 05 04:34:12 PM PDT 24 May 05 04:37:19 PM PDT 24 2633548774 ps
T976 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1633486091 May 05 04:22:53 PM PDT 24 May 05 04:27:50 PM PDT 24 3053638797 ps
T977 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3075007099 May 05 04:23:46 PM PDT 24 May 05 04:34:58 PM PDT 24 8968236718 ps
T978 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3752857599 May 05 04:48:08 PM PDT 24 May 05 04:55:48 PM PDT 24 3752250830 ps
T216 /workspace/coverage/default/51.chip_sw_all_escalation_resets.4102431229 May 05 04:51:11 PM PDT 24 May 05 05:03:37 PM PDT 24 5170530018 ps
T344 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.322199241 May 05 04:51:06 PM PDT 24 May 05 04:57:51 PM PDT 24 4086765688 ps
T747 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1601517932 May 05 04:47:52 PM PDT 24 May 05 04:58:32 PM PDT 24 5442652200 ps
T410 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.850537571 May 05 04:56:03 PM PDT 24 May 05 05:01:03 PM PDT 24 3270439100 ps
T979 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1227643866 May 05 04:45:04 PM PDT 24 May 05 04:52:10 PM PDT 24 3263654858 ps
T406 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2085159326 May 05 04:45:22 PM PDT 24 May 05 04:56:37 PM PDT 24 8287242483 ps
T980 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3053139749 May 05 04:21:12 PM PDT 24 May 05 05:07:48 PM PDT 24 12669835100 ps
T330 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1003020588 May 05 04:22:49 PM PDT 24 May 05 04:49:32 PM PDT 24 12954890174 ps
T981 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3599403115 May 05 04:31:49 PM PDT 24 May 05 04:41:32 PM PDT 24 5999815854 ps
T982 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1033444458 May 05 04:28:58 PM PDT 24 May 05 04:47:49 PM PDT 24 6735525064 ps
T983 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.817531621 May 05 04:37:46 PM PDT 24 May 05 05:02:30 PM PDT 24 8118705460 ps
T984 /workspace/coverage/default/0.chip_sw_edn_sw_mode.4120655348 May 05 04:22:16 PM PDT 24 May 05 04:54:48 PM PDT 24 8458144532 ps
T764 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2144901818 May 05 04:54:56 PM PDT 24 May 05 05:02:16 PM PDT 24 4462147640 ps
T301 /workspace/coverage/default/1.chip_plic_all_irqs_0.3237802526 May 05 04:32:21 PM PDT 24 May 05 04:49:21 PM PDT 24 5456988420 ps
T49 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1326812444 May 05 04:30:54 PM PDT 24 May 05 04:37:35 PM PDT 24 4331748096 ps
T397 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3719745633 May 05 04:21:58 PM PDT 24 May 05 04:27:31 PM PDT 24 4289182296 ps
T398 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3667335491 May 05 04:48:04 PM PDT 24 May 05 04:58:17 PM PDT 24 5535454156 ps
T399 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4000628989 May 05 04:25:33 PM PDT 24 May 05 04:29:56 PM PDT 24 2510395996 ps
T400 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1095462371 May 05 04:22:49 PM PDT 24 May 05 04:26:12 PM PDT 24 2776240690 ps
T401 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3749209206 May 05 04:37:04 PM PDT 24 May 05 05:55:05 PM PDT 24 44897012716 ps
T402 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1153867688 May 05 04:33:00 PM PDT 24 May 05 04:44:28 PM PDT 24 9329966008 ps
T403 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3028288596 May 05 04:25:14 PM PDT 24 May 05 04:33:19 PM PDT 24 6500896786 ps
T404 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3710550953 May 05 04:28:28 PM PDT 24 May 05 04:45:37 PM PDT 24 9780595249 ps
T405 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.424021995 May 05 04:40:20 PM PDT 24 May 05 04:51:34 PM PDT 24 5662176808 ps
T985 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2689871191 May 05 04:23:23 PM PDT 24 May 05 04:27:35 PM PDT 24 2397995600 ps
T736 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1869309458 May 05 04:52:26 PM PDT 24 May 05 05:01:53 PM PDT 24 4933247644 ps
T986 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3687826387 May 05 04:43:46 PM PDT 24 May 05 04:50:00 PM PDT 24 3047356805 ps
T752 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3365998398 May 05 04:53:12 PM PDT 24 May 05 05:02:24 PM PDT 24 4763924296 ps
T987 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2279951453 May 05 04:42:37 PM PDT 24 May 05 04:48:18 PM PDT 24 3212689990 ps
T988 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1680242016 May 05 04:41:44 PM PDT 24 May 05 04:54:30 PM PDT 24 7728903190 ps
T795 /workspace/coverage/default/59.chip_sw_all_escalation_resets.301281863 May 05 04:51:36 PM PDT 24 May 05 05:02:28 PM PDT 24 5185673216 ps
T989 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3571004110 May 05 04:46:53 PM PDT 24 May 05 05:01:54 PM PDT 24 12046864781 ps
T232 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1717852543 May 05 04:39:53 PM PDT 24 May 05 04:48:24 PM PDT 24 6059851872 ps
T990 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3839097044 May 05 04:42:43 PM PDT 24 May 05 04:52:01 PM PDT 24 4742319760 ps
T26 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1622132447 May 05 04:27:18 PM PDT 24 May 05 04:31:54 PM PDT 24 4277616390 ps
T302 /workspace/coverage/default/0.chip_plic_all_irqs_0.585763756 May 05 04:24:23 PM PDT 24 May 05 04:44:22 PM PDT 24 6644256468 ps
T991 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2554550498 May 05 04:38:55 PM PDT 24 May 05 04:46:54 PM PDT 24 7214149928 ps
T80 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1326904256 May 05 04:23:27 PM PDT 24 May 05 04:28:19 PM PDT 24 2960265838 ps
T992 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4117029779 May 05 04:40:49 PM PDT 24 May 05 04:46:43 PM PDT 24 2964856140 ps
T797 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3513840732 May 05 04:54:25 PM PDT 24 May 05 05:01:00 PM PDT 24 3570328176 ps
T291 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3662488052 May 05 04:49:18 PM PDT 24 May 05 04:56:47 PM PDT 24 4352580800 ps
T993 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.667587978 May 05 04:43:11 PM PDT 24 May 05 04:58:10 PM PDT 24 8965686106 ps
T354 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1764514828 May 05 04:26:46 PM PDT 24 May 05 04:34:12 PM PDT 24 3865808064 ps
T994 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2139244704 May 05 04:26:56 PM PDT 24 May 05 04:45:55 PM PDT 24 12286026476 ps
T995 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2339713122 May 05 04:49:10 PM PDT 24 May 05 04:56:13 PM PDT 24 7403770598 ps
T996 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1070406116 May 05 04:37:01 PM PDT 24 May 05 07:47:27 PM PDT 24 65281004134 ps
T997 /workspace/coverage/default/0.chip_tap_straps_dev.4059866926 May 05 04:24:25 PM PDT 24 May 05 04:52:14 PM PDT 24 14657168668 ps
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