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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.32 93.72 95.59 94.49 97.38 99.52


Total test records in report: 2762
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T748 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3673296881 May 05 04:52:18 PM PDT 24 May 05 04:59:44 PM PDT 24 5345882712 ps
T743 /workspace/coverage/default/62.chip_sw_all_escalation_resets.4107329622 May 05 04:52:13 PM PDT 24 May 05 05:01:37 PM PDT 24 6177802846 ps
T769 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1735604414 May 05 04:53:25 PM PDT 24 May 05 05:02:41 PM PDT 24 4613323928 ps
T998 /workspace/coverage/default/1.chip_sw_hmac_enc.3850062725 May 05 04:35:00 PM PDT 24 May 05 04:40:37 PM PDT 24 3008493220 ps
T765 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3179292943 May 05 04:52:51 PM PDT 24 May 05 04:59:37 PM PDT 24 4424849576 ps
T680 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2278980871 May 05 04:38:54 PM PDT 24 May 05 05:26:02 PM PDT 24 45949520683 ps
T999 /workspace/coverage/default/1.chip_sw_example_flash.3368547250 May 05 04:26:10 PM PDT 24 May 05 04:29:38 PM PDT 24 3104903834 ps
T1000 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3281424759 May 05 04:22:12 PM PDT 24 May 05 04:31:49 PM PDT 24 5162957911 ps
T1001 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2404500738 May 05 04:43:39 PM PDT 24 May 05 04:58:38 PM PDT 24 5751676190 ps
T411 /workspace/coverage/default/0.chip_jtag_mem_access.3284155668 May 05 04:15:31 PM PDT 24 May 05 04:39:02 PM PDT 24 13561358166 ps
T1002 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3437373720 May 05 04:30:12 PM PDT 24 May 05 04:35:11 PM PDT 24 2984260608 ps
T412 /workspace/coverage/default/2.chip_jtag_mem_access.2740393262 May 05 04:34:27 PM PDT 24 May 05 04:58:45 PM PDT 24 12687401621 ps
T1003 /workspace/coverage/default/1.chip_sw_aes_masking_off.4193796711 May 05 04:30:19 PM PDT 24 May 05 04:35:24 PM PDT 24 2837727732 ps
T1004 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3453015046 May 05 04:42:13 PM PDT 24 May 05 04:47:28 PM PDT 24 4006015159 ps
T1005 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1229152292 May 05 04:41:25 PM PDT 24 May 05 05:09:34 PM PDT 24 7352889856 ps
T1006 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2964272776 May 05 04:26:25 PM PDT 24 May 05 04:32:23 PM PDT 24 5822737784 ps
T1007 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1797536738 May 05 04:41:08 PM PDT 24 May 05 04:45:37 PM PDT 24 2975440220 ps
T355 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2249252074 May 05 04:37:58 PM PDT 24 May 05 04:49:30 PM PDT 24 4849936954 ps
T1008 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2198860972 May 05 04:28:16 PM PDT 24 May 05 04:33:23 PM PDT 24 4401262776 ps
T1009 /workspace/coverage/default/2.chip_sw_example_concurrency.3917527715 May 05 04:37:28 PM PDT 24 May 05 04:40:59 PM PDT 24 2461449440 ps
T1010 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.702484887 May 05 04:45:52 PM PDT 24 May 05 05:12:50 PM PDT 24 8065853472 ps
T1011 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.440363473 May 05 04:40:16 PM PDT 24 May 05 05:21:02 PM PDT 24 26943300881 ps
T1012 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.916726878 May 05 04:32:07 PM PDT 24 May 05 04:37:19 PM PDT 24 3422789408 ps
T1013 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.4017852905 May 05 04:47:31 PM PDT 24 May 05 04:55:38 PM PDT 24 4068171678 ps
T1014 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3160479987 May 05 04:35:06 PM PDT 24 May 05 04:40:32 PM PDT 24 3463017004 ps
T1015 /workspace/coverage/default/1.chip_sw_example_concurrency.3435302043 May 05 04:27:18 PM PDT 24 May 05 04:32:42 PM PDT 24 2453652960 ps
T1016 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3968770321 May 05 04:24:48 PM PDT 24 May 05 04:35:11 PM PDT 24 4021264088 ps
T735 /workspace/coverage/default/92.chip_sw_all_escalation_resets.54032742 May 05 04:54:02 PM PDT 24 May 05 05:01:48 PM PDT 24 5751180304 ps
T1017 /workspace/coverage/default/2.chip_sw_example_manufacturer.1860552732 May 05 04:38:57 PM PDT 24 May 05 04:42:19 PM PDT 24 2675833468 ps
T1018 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2092522884 May 05 04:42:52 PM PDT 24 May 05 04:46:13 PM PDT 24 2411420552 ps
T720 /workspace/coverage/default/2.chip_sw_power_sleep_load.3088936391 May 05 04:44:22 PM PDT 24 May 05 04:51:03 PM PDT 24 4756268530 ps
T147 /workspace/coverage/default/2.chip_plic_all_irqs_10.3912436852 May 05 04:45:54 PM PDT 24 May 05 04:53:59 PM PDT 24 3910320860 ps
T1019 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2167762464 May 05 04:55:06 PM PDT 24 May 05 05:00:41 PM PDT 24 3673604376 ps
T744 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314234758 May 05 04:49:25 PM PDT 24 May 05 04:55:01 PM PDT 24 3521688344 ps
T1020 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1156029635 May 05 04:29:18 PM PDT 24 May 05 04:33:38 PM PDT 24 2978383669 ps
T1021 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1516082201 May 05 04:47:09 PM PDT 24 May 05 04:56:01 PM PDT 24 4056459425 ps
T1022 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.759173102 May 05 04:31:40 PM PDT 24 May 05 04:37:20 PM PDT 24 3050270650 ps
T1023 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2056731318 May 05 04:29:20 PM PDT 24 May 05 05:27:44 PM PDT 24 18220089608 ps
T1024 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1441656825 May 05 04:24:08 PM PDT 24 May 05 04:27:21 PM PDT 24 2695945573 ps
T309 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.968677831 May 05 04:25:13 PM PDT 24 May 05 04:58:48 PM PDT 24 7402017640 ps
T1025 /workspace/coverage/default/1.chip_sw_aon_timer_irq.183659765 May 05 04:28:23 PM PDT 24 May 05 04:35:24 PM PDT 24 4020964800 ps
T751 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3834997705 May 05 04:51:52 PM PDT 24 May 05 05:01:58 PM PDT 24 4630838832 ps
T40 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3001921287 May 05 04:40:05 PM PDT 24 May 05 04:51:25 PM PDT 24 4854042970 ps
T794 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2479109638 May 05 04:52:52 PM PDT 24 May 05 04:59:34 PM PDT 24 3170898496 ps
T701 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1113468984 May 05 04:40:59 PM PDT 24 May 05 04:47:25 PM PDT 24 3355326260 ps
T1026 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2895256903 May 05 04:55:44 PM PDT 24 May 05 05:05:08 PM PDT 24 5781000960 ps
T1027 /workspace/coverage/default/2.chip_sw_otbn_randomness.4292200084 May 05 04:39:30 PM PDT 24 May 05 04:55:07 PM PDT 24 5876201016 ps
T662 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.477057537 May 05 04:24:02 PM PDT 24 May 05 05:37:43 PM PDT 24 25186589443 ps
T1028 /workspace/coverage/default/2.chip_sival_flash_info_access.478478867 May 05 04:37:10 PM PDT 24 May 05 04:41:49 PM PDT 24 3325586820 ps
T1029 /workspace/coverage/default/1.chip_sw_csrng_smoketest.4044570037 May 05 04:35:29 PM PDT 24 May 05 04:38:11 PM PDT 24 2226370040 ps
T1030 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.755001157 May 05 04:27:11 PM PDT 24 May 05 05:06:34 PM PDT 24 24794163977 ps
T1031 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2684789795 May 05 04:24:02 PM PDT 24 May 05 04:31:05 PM PDT 24 3299437702 ps
T1032 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1789005477 May 05 04:43:13 PM PDT 24 May 05 04:51:48 PM PDT 24 4014146662 ps
T208 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3090912258 May 05 04:21:41 PM PDT 24 May 05 06:02:10 PM PDT 24 47177687056 ps
T1033 /workspace/coverage/default/1.rom_keymgr_functest.1216170637 May 05 04:36:20 PM PDT 24 May 05 04:44:57 PM PDT 24 4714103896 ps
T1034 /workspace/coverage/default/0.chip_sw_otbn_randomness.184479077 May 05 04:22:59 PM PDT 24 May 05 04:40:03 PM PDT 24 5392148840 ps
T1035 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1726852115 May 05 04:54:31 PM PDT 24 May 05 05:04:33 PM PDT 24 5956228446 ps
T1036 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3075313917 May 05 04:38:36 PM PDT 24 May 05 04:52:19 PM PDT 24 7874913698 ps
T52 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.200284933 May 05 04:26:31 PM PDT 24 May 05 04:50:42 PM PDT 24 18844008936 ps
T1037 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1804206441 May 05 04:32:22 PM PDT 24 May 05 04:43:54 PM PDT 24 4634450264 ps
T745 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2414151159 May 05 04:52:35 PM PDT 24 May 05 04:59:31 PM PDT 24 3179920812 ps
T1038 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3577705048 May 05 04:40:45 PM PDT 24 May 05 04:49:56 PM PDT 24 8018887648 ps
T1039 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2351212172 May 05 04:37:14 PM PDT 24 May 05 04:43:16 PM PDT 24 3244281628 ps
T1040 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1443788717 May 05 04:34:07 PM PDT 24 May 05 04:38:16 PM PDT 24 3696234579 ps
T1041 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1798357635 May 05 04:23:23 PM PDT 24 May 05 04:57:14 PM PDT 24 13507226018 ps
T81 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.233316826 May 05 04:39:31 PM PDT 24 May 05 04:44:18 PM PDT 24 2904582258 ps
T1042 /workspace/coverage/default/2.chip_sw_uart_smoketest.2093864856 May 05 04:43:59 PM PDT 24 May 05 04:48:19 PM PDT 24 2526543272 ps
T1043 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1435679580 May 05 04:24:19 PM PDT 24 May 05 04:30:27 PM PDT 24 2990892628 ps
T212 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2923613972 May 05 04:40:01 PM PDT 24 May 05 06:09:08 PM PDT 24 47473088626 ps
T1044 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3599620530 May 05 04:39:12 PM PDT 24 May 05 04:58:38 PM PDT 24 6088477810 ps
T304 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2518608982 May 05 04:34:43 PM PDT 24 May 05 04:48:19 PM PDT 24 5045234783 ps
T152 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.511381533 May 05 04:29:52 PM PDT 24 May 05 04:34:11 PM PDT 24 3109452494 ps
T1045 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3768304992 May 05 04:40:01 PM PDT 24 May 05 04:49:46 PM PDT 24 3835603200 ps
T1046 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2462996493 May 05 04:41:48 PM PDT 24 May 05 04:57:12 PM PDT 24 7138849748 ps
T784 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1670778783 May 05 04:53:38 PM PDT 24 May 05 05:05:32 PM PDT 24 5458818160 ps
T263 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4221976294 May 05 04:34:49 PM PDT 24 May 05 04:45:15 PM PDT 24 5569479978 ps
T154 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4050968201 May 05 04:39:02 PM PDT 24 May 05 04:45:22 PM PDT 24 2696566225 ps
T209 /workspace/coverage/default/2.chip_sw_flash_init.3047483723 May 05 04:38:03 PM PDT 24 May 05 05:11:03 PM PDT 24 19030131120 ps
T1047 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1139733788 May 05 04:30:04 PM PDT 24 May 05 05:01:50 PM PDT 24 23850192122 ps
T1048 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.724276159 May 05 04:38:15 PM PDT 24 May 05 05:00:23 PM PDT 24 11419766020 ps
T1049 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2730160703 May 05 04:28:39 PM PDT 24 May 05 04:56:54 PM PDT 24 12789018210 ps
T1050 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1867037987 May 05 04:29:08 PM PDT 24 May 05 04:37:22 PM PDT 24 4440724142 ps
T733 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1683174234 May 05 04:51:23 PM PDT 24 May 05 04:58:57 PM PDT 24 5170255256 ps
T351 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1800661265 May 05 04:23:18 PM PDT 24 May 05 04:37:28 PM PDT 24 4928618040 ps
T1051 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1217707151 May 05 04:31:13 PM PDT 24 May 05 04:34:58 PM PDT 24 2637936888 ps
T1052 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3525559385 May 05 04:22:58 PM PDT 24 May 05 04:33:37 PM PDT 24 4660866823 ps
T1053 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4259804622 May 05 04:36:06 PM PDT 24 May 05 04:39:44 PM PDT 24 3028706820 ps
T1054 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3076966255 May 05 04:30:59 PM PDT 24 May 05 04:47:04 PM PDT 24 5234133984 ps
T753 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3770522005 May 05 04:48:41 PM PDT 24 May 05 04:58:33 PM PDT 24 4650783792 ps
T1055 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3611501026 May 05 04:42:55 PM PDT 24 May 05 04:56:06 PM PDT 24 5050211168 ps
T1056 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3088872376 May 05 04:45:50 PM PDT 24 May 05 05:02:52 PM PDT 24 10439067752 ps
T1057 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2038030988 May 05 04:27:43 PM PDT 24 May 05 08:09:12 PM PDT 24 78400016372 ps
T1058 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2692109544 May 05 04:21:37 PM PDT 24 May 05 04:36:15 PM PDT 24 6962859096 ps
T1059 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3307083672 May 05 04:47:55 PM PDT 24 May 05 05:23:40 PM PDT 24 13262618308 ps
T1060 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.157433961 May 05 04:21:50 PM PDT 24 May 05 04:29:11 PM PDT 24 4811725706 ps
T663 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.845277299 May 05 04:35:22 PM PDT 24 May 05 05:31:40 PM PDT 24 24160742072 ps
T1061 /workspace/coverage/default/1.chip_sw_aes_entropy.2979887369 May 05 04:30:02 PM PDT 24 May 05 04:34:24 PM PDT 24 2496827126 ps
T1062 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3631027566 May 05 04:43:33 PM PDT 24 May 05 04:48:55 PM PDT 24 2752332609 ps
T724 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.818667223 May 05 04:40:50 PM PDT 24 May 05 05:03:48 PM PDT 24 23814985016 ps
T1063 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2074931010 May 05 04:32:09 PM PDT 24 May 05 04:42:06 PM PDT 24 4702700817 ps
T1064 /workspace/coverage/default/1.chip_sival_flash_info_access.1686069889 May 05 04:30:06 PM PDT 24 May 05 04:34:31 PM PDT 24 3061359320 ps
T56 /workspace/coverage/default/2.chip_sw_alert_test.1312504316 May 05 04:41:18 PM PDT 24 May 05 04:46:27 PM PDT 24 2940639664 ps
T1065 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.760747838 May 05 04:45:51 PM PDT 24 May 05 04:54:03 PM PDT 24 6406908656 ps
T233 /workspace/coverage/default/17.chip_sw_all_escalation_resets.4079592658 May 05 04:48:54 PM PDT 24 May 05 04:57:54 PM PDT 24 4886131696 ps
T1066 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3965694463 May 05 04:23:29 PM PDT 24 May 05 04:32:42 PM PDT 24 5526693620 ps
T1067 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3619016355 May 05 04:40:56 PM PDT 24 May 05 05:01:36 PM PDT 24 6871731900 ps
T1068 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2777573862 May 05 04:23:11 PM PDT 24 May 05 04:28:20 PM PDT 24 5651887072 ps
T1069 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1026457670 May 05 04:21:44 PM PDT 24 May 05 04:37:02 PM PDT 24 4695699134 ps
T86 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1640165713 May 05 04:50:39 PM PDT 24 May 05 04:55:50 PM PDT 24 3091876992 ps
T1070 /workspace/coverage/default/54.chip_sw_all_escalation_resets.156755762 May 05 04:51:41 PM PDT 24 May 05 05:01:40 PM PDT 24 4219943366 ps
T315 /workspace/coverage/default/2.chip_sw_pattgen_ios.4201884015 May 05 04:38:45 PM PDT 24 May 05 04:43:17 PM PDT 24 2742563910 ps
T310 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.557537854 May 05 04:31:28 PM PDT 24 May 05 04:58:48 PM PDT 24 8235049472 ps
T108 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3786021391 May 05 04:45:22 PM PDT 24 May 05 05:19:18 PM PDT 24 19035291143 ps
T1071 /workspace/coverage/default/0.chip_sw_hmac_enc.887976995 May 05 04:23:40 PM PDT 24 May 05 04:28:49 PM PDT 24 2682542764 ps
T138 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.856702623 May 05 04:38:35 PM PDT 24 May 05 04:45:34 PM PDT 24 7993702240 ps
T284 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1006198812 May 05 04:22:55 PM PDT 24 May 05 04:40:03 PM PDT 24 8525046130 ps
T1072 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4138598295 May 05 04:46:03 PM PDT 24 May 05 04:52:00 PM PDT 24 3352837340 ps
T1073 /workspace/coverage/default/0.chip_sw_uart_smoketest.3928425567 May 05 04:25:09 PM PDT 24 May 05 04:29:43 PM PDT 24 2807228800 ps
T1074 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1672327440 May 05 04:49:13 PM PDT 24 May 05 04:59:38 PM PDT 24 5584404696 ps
T1075 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1615184267 May 05 04:40:28 PM PDT 24 May 05 04:44:57 PM PDT 24 2737438724 ps
T1076 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2226929680 May 05 04:28:39 PM PDT 24 May 05 04:34:51 PM PDT 24 4840934600 ps
T1077 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.699279008 May 05 04:42:54 PM PDT 24 May 05 04:52:32 PM PDT 24 5243285365 ps
T299 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2386272515 May 05 04:27:19 PM PDT 24 May 05 04:57:05 PM PDT 24 13421412856 ps
T1078 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.226990894 May 05 04:37:48 PM PDT 24 May 05 04:56:03 PM PDT 24 6230488640 ps
T251 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1021066183 May 05 04:46:50 PM PDT 24 May 05 04:57:16 PM PDT 24 5549772898 ps
T1079 /workspace/coverage/default/4.chip_tap_straps_rma.2648502405 May 05 04:47:14 PM PDT 24 May 05 04:53:13 PM PDT 24 4459061713 ps
T1080 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.524813969 May 05 04:23:25 PM PDT 24 May 05 04:30:18 PM PDT 24 3303512500 ps
T779 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4042315615 May 05 04:54:25 PM PDT 24 May 05 05:01:04 PM PDT 24 4017799666 ps
T1081 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1996978258 May 05 04:33:30 PM PDT 24 May 05 04:38:28 PM PDT 24 3100158408 ps
T1082 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1737493320 May 05 04:27:12 PM PDT 24 May 05 04:31:42 PM PDT 24 3175331776 ps
T200 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3759274279 May 05 04:31:24 PM PDT 24 May 05 04:51:13 PM PDT 24 6355706760 ps
T1083 /workspace/coverage/default/4.chip_tap_straps_prod.2342516841 May 05 04:44:43 PM PDT 24 May 05 04:47:31 PM PDT 24 2829446513 ps
T1084 /workspace/coverage/default/80.chip_sw_all_escalation_resets.299606175 May 05 04:54:20 PM PDT 24 May 05 05:04:12 PM PDT 24 4585835804 ps
T1085 /workspace/coverage/default/3.chip_tap_straps_prod.1463786413 May 05 04:44:24 PM PDT 24 May 05 05:10:38 PM PDT 24 13369177793 ps
T1086 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1291290207 May 05 04:29:32 PM PDT 24 May 05 04:35:16 PM PDT 24 5371697208 ps
T322 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2104454721 May 05 04:32:16 PM PDT 24 May 05 04:36:54 PM PDT 24 2563207139 ps
T1087 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673602307 May 05 04:51:20 PM PDT 24 May 05 04:57:02 PM PDT 24 3606122214 ps
T1088 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2686576076 May 05 04:21:43 PM PDT 24 May 05 04:34:09 PM PDT 24 4386436456 ps
T682 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.715253580 May 05 04:25:16 PM PDT 24 May 05 04:33:08 PM PDT 24 5177393677 ps
T234 /workspace/coverage/default/45.chip_sw_all_escalation_resets.111494714 May 05 04:49:59 PM PDT 24 May 05 04:58:54 PM PDT 24 5102829088 ps
T1089 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3755857265 May 05 04:45:02 PM PDT 24 May 05 04:56:41 PM PDT 24 4975782804 ps
T780 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2429402886 May 05 04:54:12 PM PDT 24 May 05 05:02:59 PM PDT 24 5729174106 ps
T27 /workspace/coverage/default/2.chip_sw_gpio_smoketest.238203066 May 05 04:43:49 PM PDT 24 May 05 04:47:56 PM PDT 24 3218954502 ps
T1090 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.901164969 May 05 04:43:46 PM PDT 24 May 05 04:47:49 PM PDT 24 2311737040 ps
T229 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3888826161 May 05 04:33:28 PM PDT 24 May 05 04:41:52 PM PDT 24 4983924480 ps
T1091 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4055755599 May 05 04:43:51 PM PDT 24 May 05 04:48:10 PM PDT 24 2256598400 ps
T683 /workspace/coverage/default/3.chip_tap_straps_dev.1635499514 May 05 04:44:53 PM PDT 24 May 05 05:08:51 PM PDT 24 13016512705 ps
T356 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2817739667 May 05 04:21:14 PM PDT 24 May 05 04:37:05 PM PDT 24 4958493480 ps
T781 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801501660 May 05 04:49:39 PM PDT 24 May 05 04:58:26 PM PDT 24 3840785020 ps
T1092 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2416008275 May 05 04:34:55 PM PDT 24 May 05 05:27:08 PM PDT 24 16400489936 ps
T235 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2848080024 May 05 04:48:21 PM PDT 24 May 05 04:56:57 PM PDT 24 5487505968 ps
T742 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2033573845 May 05 04:48:31 PM PDT 24 May 05 04:54:39 PM PDT 24 3963690644 ps
T739 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1625505278 May 05 04:48:27 PM PDT 24 May 05 04:57:10 PM PDT 24 4338947728 ps
T770 /workspace/coverage/default/56.chip_sw_all_escalation_resets.4015056258 May 05 04:52:26 PM PDT 24 May 05 05:02:24 PM PDT 24 5787977804 ps
T1093 /workspace/coverage/default/0.chip_sw_power_idle_load.2630018381 May 05 04:26:06 PM PDT 24 May 05 04:37:36 PM PDT 24 4708600750 ps
T1094 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1669688557 May 05 04:29:28 PM PDT 24 May 05 04:38:32 PM PDT 24 4077531220 ps
T1095 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3005421441 May 05 04:34:44 PM PDT 24 May 05 04:39:33 PM PDT 24 3680010677 ps
T1096 /workspace/coverage/default/0.chip_sw_edn_kat.769573704 May 05 04:24:14 PM PDT 24 May 05 04:33:43 PM PDT 24 3487290344 ps
T1097 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1998592542 May 05 04:25:42 PM PDT 24 May 05 04:29:37 PM PDT 24 3172238126 ps
T1098 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2470839997 May 05 04:48:44 PM PDT 24 May 05 05:00:12 PM PDT 24 7246428414 ps
T783 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2191699338 May 05 04:46:40 PM PDT 24 May 05 04:57:11 PM PDT 24 5268018032 ps
T1099 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1560764327 May 05 04:27:32 PM PDT 24 May 05 04:38:25 PM PDT 24 4453025000 ps
T1100 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3181745977 May 05 04:22:43 PM PDT 24 May 05 04:26:58 PM PDT 24 2346450168 ps
T721 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1482275885 May 05 04:41:11 PM PDT 24 May 05 04:55:51 PM PDT 24 5181993382 ps
T189 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3325472630 May 05 04:37:40 PM PDT 24 May 05 04:42:49 PM PDT 24 2791465900 ps
T145 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3361595779 May 05 04:27:11 PM PDT 24 May 05 07:26:07 PM PDT 24 57543790616 ps
T669 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1178173785 May 05 04:40:32 PM PDT 24 May 05 04:49:42 PM PDT 24 3132466896 ps
T1101 /workspace/coverage/default/0.chip_tap_straps_rma.3419440927 May 05 04:23:22 PM PDT 24 May 05 04:25:10 PM PDT 24 1967756793 ps
T1102 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3237860013 May 05 04:31:08 PM PDT 24 May 05 04:34:16 PM PDT 24 2259944600 ps
T715 /workspace/coverage/default/0.chip_sw_plic_sw_irq.453109883 May 05 04:25:50 PM PDT 24 May 05 04:30:26 PM PDT 24 2709489730 ps
T1103 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1364551247 May 05 04:46:01 PM PDT 24 May 05 05:00:18 PM PDT 24 7933414697 ps
T1104 /workspace/coverage/default/10.chip_sw_all_escalation_resets.2818370160 May 05 04:46:39 PM PDT 24 May 05 04:55:50 PM PDT 24 4472363288 ps
T1105 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4174366754 May 05 04:24:18 PM PDT 24 May 05 04:33:10 PM PDT 24 5405419168 ps
T220 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.395029722 May 05 04:52:09 PM PDT 24 May 05 04:57:44 PM PDT 24 3578616720 ps
T1106 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1186550227 May 05 04:41:15 PM PDT 24 May 05 05:16:46 PM PDT 24 8831401410 ps
T1107 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2692498824 May 05 04:33:21 PM PDT 24 May 05 04:45:01 PM PDT 24 4511889512 ps
T206 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.316520292 May 05 04:26:24 PM PDT 24 May 05 05:49:51 PM PDT 24 50257308920 ps
T1108 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.777296082 May 05 04:21:37 PM PDT 24 May 05 04:31:45 PM PDT 24 7270482864 ps
T1109 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1249078765 May 05 04:28:55 PM PDT 24 May 05 04:43:38 PM PDT 24 6233184430 ps
T1110 /workspace/coverage/default/1.chip_sw_otbn_smoketest.3276728604 May 05 04:35:34 PM PDT 24 May 05 05:11:01 PM PDT 24 10179171192 ps
T1111 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3825936206 May 05 04:41:19 PM PDT 24 May 05 05:01:59 PM PDT 24 5654373938 ps
T1112 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1344747010 May 05 04:44:10 PM PDT 24 May 05 04:47:11 PM PDT 24 1969954964 ps
T1113 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3482048210 May 05 04:28:27 PM PDT 24 May 05 04:32:44 PM PDT 24 3287971540 ps
T762 /workspace/coverage/default/87.chip_sw_all_escalation_resets.4153737622 May 05 04:54:58 PM PDT 24 May 05 05:05:19 PM PDT 24 5182438104 ps
T87 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3537083361 May 05 04:51:12 PM PDT 24 May 05 05:00:03 PM PDT 24 3569745024 ps
T1114 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2336780426 May 05 04:49:03 PM PDT 24 May 05 04:59:20 PM PDT 24 4202559304 ps
T766 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3223445793 May 05 04:54:27 PM PDT 24 May 05 05:00:24 PM PDT 24 3119941586 ps
T1115 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.796012740 May 05 04:40:26 PM PDT 24 May 05 04:50:09 PM PDT 24 3772396960 ps
T1116 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3870847920 May 05 04:22:34 PM PDT 24 May 05 04:25:53 PM PDT 24 2411124521 ps
T1117 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.683562308 May 05 04:22:29 PM PDT 24 May 05 04:46:31 PM PDT 24 16588350339 ps
T1118 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3016873672 May 05 04:48:30 PM PDT 24 May 05 04:56:41 PM PDT 24 5964196618 ps
T190 /workspace/coverage/default/0.chip_sw_gpio_smoketest.193444129 May 05 04:27:54 PM PDT 24 May 05 04:32:48 PM PDT 24 2728247355 ps
T1119 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3301822468 May 05 04:58:20 PM PDT 24 May 05 05:06:12 PM PDT 24 5306246232 ps
T726 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3996928085 May 05 04:28:11 PM PDT 24 May 05 05:15:12 PM PDT 24 21001613407 ps
T777 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.781778813 May 05 04:48:49 PM PDT 24 May 05 04:55:15 PM PDT 24 3299949096 ps
T236 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3082104903 May 05 04:48:02 PM PDT 24 May 05 04:58:40 PM PDT 24 5103791700 ps
T1120 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3573280889 May 05 04:27:58 PM PDT 24 May 05 04:39:38 PM PDT 24 3895844680 ps
T1121 /workspace/coverage/default/2.chip_sw_example_flash.3433149756 May 05 04:36:27 PM PDT 24 May 05 04:40:03 PM PDT 24 2252736664 ps
T1122 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.208553153 May 05 04:41:51 PM PDT 24 May 05 05:00:04 PM PDT 24 7240007710 ps
T130 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1927275920 May 05 04:25:06 PM PDT 24 May 05 04:40:02 PM PDT 24 8195461814 ps
T1123 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3114112438 May 05 04:21:47 PM PDT 24 May 05 04:26:05 PM PDT 24 2243634968 ps
T1124 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3242353138 May 05 04:22:38 PM PDT 24 May 05 04:34:02 PM PDT 24 9108830600 ps
T767 /workspace/coverage/default/5.chip_sw_all_escalation_resets.326282885 May 05 04:46:12 PM PDT 24 May 05 04:55:58 PM PDT 24 5174099712 ps
T53 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2465785950 May 05 04:42:33 PM PDT 24 May 05 05:15:55 PM PDT 24 19049620160 ps
T1125 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2805476641 May 05 04:31:01 PM PDT 24 May 05 04:39:13 PM PDT 24 4485065690 ps
T1126 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.663443960 May 05 04:26:09 PM PDT 24 May 05 04:30:45 PM PDT 24 2796113484 ps
T786 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.370822243 May 05 04:51:03 PM PDT 24 May 05 04:57:43 PM PDT 24 3520669520 ps
T1127 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3993142482 May 05 04:39:52 PM PDT 24 May 05 04:51:37 PM PDT 24 6343913596 ps
T1128 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.637683033 May 05 04:29:51 PM PDT 24 May 05 07:30:55 PM PDT 24 254248699808 ps
T57 /workspace/coverage/default/0.chip_sw_alert_test.2084139373 May 05 04:22:58 PM PDT 24 May 05 04:29:34 PM PDT 24 2721885200 ps
T1129 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2328206275 May 05 04:38:40 PM PDT 24 May 05 05:02:46 PM PDT 24 14802952513 ps
T1130 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.84446318 May 05 04:47:42 PM PDT 24 May 05 05:04:03 PM PDT 24 9333307220 ps
T1131 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1875332359 May 05 04:42:05 PM PDT 24 May 05 04:45:35 PM PDT 24 2751832039 ps
T1132 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3068310396 May 05 04:21:25 PM PDT 24 May 05 04:37:30 PM PDT 24 9939767011 ps
T1133 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3350201038 May 05 04:45:20 PM PDT 24 May 05 04:49:00 PM PDT 24 2795099752 ps
T176 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2120721528 May 05 04:27:54 PM PDT 24 May 05 04:39:23 PM PDT 24 5004127699 ps
T1134 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2029127542 May 05 04:44:07 PM PDT 24 May 05 04:47:23 PM PDT 24 2758456700 ps
T1135 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4183990843 May 05 04:27:36 PM PDT 24 May 05 04:34:04 PM PDT 24 4876221384 ps
T345 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.260335374 May 05 04:51:53 PM PDT 24 May 05 05:00:30 PM PDT 24 4302780100 ps
T1136 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2075931434 May 05 04:35:53 PM PDT 24 May 05 04:38:57 PM PDT 24 2262676176 ps
T275 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4189419393 May 05 04:33:34 PM PDT 24 May 05 04:36:52 PM PDT 24 2571225105 ps
T798 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.34545406 May 05 04:55:11 PM PDT 24 May 05 04:59:30 PM PDT 24 3660844350 ps
T1137 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1094536455 May 05 04:22:15 PM PDT 24 May 05 04:31:44 PM PDT 24 5037010178 ps
T1138 /workspace/coverage/default/1.chip_sw_kmac_idle.604589115 May 05 04:32:27 PM PDT 24 May 05 04:37:11 PM PDT 24 2926962280 ps
T276 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3013448665 May 05 04:35:21 PM PDT 24 May 05 04:40:12 PM PDT 24 3249434860 ps
T54 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1214132349 May 05 04:33:25 PM PDT 24 May 05 05:04:53 PM PDT 24 21571764940 ps
T1139 /workspace/coverage/default/0.chip_sw_power_sleep_load.1889900259 May 05 04:25:23 PM PDT 24 May 05 04:34:20 PM PDT 24 11223185164 ps
T1140 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3823555771 May 05 04:44:59 PM PDT 24 May 05 04:55:56 PM PDT 24 4589917624 ps
T1141 /workspace/coverage/default/0.chip_sw_aes_idle.186514968 May 05 04:23:03 PM PDT 24 May 05 04:26:27 PM PDT 24 3317522244 ps
T1142 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3363201316 May 05 04:42:24 PM PDT 24 May 05 04:46:04 PM PDT 24 3179275551 ps
T1143 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2143813676 May 05 04:48:27 PM PDT 24 May 05 04:55:15 PM PDT 24 3767726508 ps
T768 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2560007069 May 05 04:51:17 PM PDT 24 May 05 04:57:40 PM PDT 24 3290391352 ps
T1144 /workspace/coverage/default/2.chip_sw_aes_idle.1470723882 May 05 04:40:14 PM PDT 24 May 05 04:45:24 PM PDT 24 2713588092 ps
T1145 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2832280557 May 05 04:34:07 PM PDT 24 May 05 04:44:34 PM PDT 24 4179084084 ps
T1146 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.586900349 May 05 04:50:04 PM PDT 24 May 05 04:58:53 PM PDT 24 4620390884 ps
T1147 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2725111744 May 05 04:41:35 PM PDT 24 May 05 04:49:46 PM PDT 24 5078012320 ps
T1148 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.626402635 May 05 04:41:44 PM PDT 24 May 05 04:54:50 PM PDT 24 4439102360 ps
T1149 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2438802610 May 05 04:46:03 PM PDT 24 May 05 05:00:51 PM PDT 24 10873301187 ps
T1150 /workspace/coverage/default/0.chip_sw_example_flash.2716579426 May 05 04:22:57 PM PDT 24 May 05 04:26:49 PM PDT 24 2541393186 ps
T373 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1224881470 May 05 04:42:27 PM PDT 24 May 05 05:05:49 PM PDT 24 18944460064 ps
T28 /workspace/coverage/default/1.chip_sw_gpio.618617915 May 05 04:27:27 PM PDT 24 May 05 04:34:04 PM PDT 24 3703972290 ps
T774 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.215551062 May 05 04:46:02 PM PDT 24 May 05 04:52:51 PM PDT 24 3123002168 ps
T785 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211888779 May 05 04:50:53 PM PDT 24 May 05 04:57:27 PM PDT 24 3524531138 ps
T775 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2665790993 May 05 04:54:34 PM PDT 24 May 05 05:00:26 PM PDT 24 3036955284 ps
T1151 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1831289143 May 05 04:26:19 PM PDT 24 May 05 04:40:06 PM PDT 24 8761483097 ps
T1152 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.519590918 May 05 04:26:25 PM PDT 24 May 05 07:38:56 PM PDT 24 63883191256 ps
T741 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2245013992 May 05 04:49:11 PM PDT 24 May 05 04:58:56 PM PDT 24 5461202472 ps
T1153 /workspace/coverage/default/0.chip_sw_kmac_smoketest.504040246 May 05 04:28:27 PM PDT 24 May 05 04:33:20 PM PDT 24 3241090690 ps
T1154 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.860920040 May 05 04:20:43 PM PDT 24 May 05 04:29:19 PM PDT 24 3951428872 ps
T1155 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2876160058 May 05 04:30:11 PM PDT 24 May 05 04:59:57 PM PDT 24 7987199232 ps
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