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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.32 93.72 95.59 94.49 97.38 99.52


Total test records in report: 2762
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T1156 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.465944610 May 05 04:26:41 PM PDT 24 May 05 05:46:21 PM PDT 24 47449138474 ps
T1157 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2132669998 May 05 04:52:56 PM PDT 24 May 05 05:01:44 PM PDT 24 4618959760 ps
T1158 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2008718510 May 05 04:23:01 PM PDT 24 May 05 04:27:05 PM PDT 24 3205718355 ps
T1159 /workspace/coverage/default/2.chip_sw_edn_kat.3803697692 May 05 04:40:48 PM PDT 24 May 05 04:53:02 PM PDT 24 3035544700 ps
T1160 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2387667112 May 05 04:25:35 PM PDT 24 May 05 04:59:40 PM PDT 24 24823806905 ps
T1161 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2267478322 May 05 04:33:38 PM PDT 24 May 05 04:36:34 PM PDT 24 3211652102 ps
T1162 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1351500687 May 05 04:24:55 PM PDT 24 May 05 04:46:50 PM PDT 24 6497387880 ps
T1163 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2697628573 May 05 04:43:04 PM PDT 24 May 05 04:49:16 PM PDT 24 4174009784 ps
T132 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1952285003 May 05 04:32:52 PM PDT 24 May 05 04:40:34 PM PDT 24 4645560680 ps
T1164 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3682239611 May 05 04:41:20 PM PDT 24 May 05 04:54:08 PM PDT 24 5836865400 ps
T1165 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2124774843 May 05 04:29:55 PM PDT 24 May 05 04:34:58 PM PDT 24 2711464136 ps
T342 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3721045955 May 05 04:42:35 PM PDT 24 May 05 04:46:56 PM PDT 24 2277710410 ps
T1166 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4247209939 May 05 04:38:43 PM PDT 24 May 05 04:55:55 PM PDT 24 5550460060 ps
T374 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2057320186 May 05 04:34:59 PM PDT 24 May 05 04:52:29 PM PDT 24 19075650810 ps
T799 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627961523 May 05 04:54:30 PM PDT 24 May 05 05:00:45 PM PDT 24 3997872174 ps
T1167 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.334956586 May 05 04:21:41 PM PDT 24 May 05 05:03:31 PM PDT 24 35364743672 ps
T210 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2394754925 May 05 04:28:09 PM PDT 24 May 05 05:59:57 PM PDT 24 47037114260 ps
T727 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.846099008 May 05 04:40:22 PM PDT 24 May 05 05:24:46 PM PDT 24 20799342241 ps
T1168 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3506677930 May 05 04:54:37 PM PDT 24 May 05 05:01:06 PM PDT 24 3988743800 ps
T1169 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3589004146 May 05 04:21:29 PM PDT 24 May 05 04:52:02 PM PDT 24 9276101736 ps
T1170 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2367586235 May 05 04:23:08 PM PDT 24 May 05 04:27:09 PM PDT 24 2007004746 ps
T1171 /workspace/coverage/default/2.chip_sw_aes_masking_off.560401132 May 05 04:40:16 PM PDT 24 May 05 04:44:45 PM PDT 24 3172547267 ps
T800 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392308904 May 05 04:47:44 PM PDT 24 May 05 04:53:16 PM PDT 24 3604549336 ps
T1172 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1840137903 May 05 04:28:54 PM PDT 24 May 05 04:39:42 PM PDT 24 6214786228 ps
T1173 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.379626467 May 05 04:21:49 PM PDT 24 May 05 07:36:50 PM PDT 24 65466653289 ps
T1174 /workspace/coverage/default/1.chip_sw_edn_sw_mode.3729541738 May 05 04:30:56 PM PDT 24 May 05 05:03:21 PM PDT 24 8559740652 ps
T1175 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3769030730 May 05 04:44:42 PM PDT 24 May 05 05:17:12 PM PDT 24 14007464025 ps
T1176 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1058301728 May 05 04:45:10 PM PDT 24 May 05 05:21:46 PM PDT 24 12747927131 ps
T1177 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.834169717 May 05 04:43:57 PM PDT 24 May 05 04:56:49 PM PDT 24 6356350808 ps
T1178 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3942965914 May 05 04:30:25 PM PDT 24 May 05 04:58:27 PM PDT 24 10821524130 ps
T1179 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3753993141 May 05 04:55:02 PM PDT 24 May 05 05:04:09 PM PDT 24 5774685456 ps
T1180 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.937249588 May 05 04:41:49 PM PDT 24 May 05 04:59:49 PM PDT 24 9937714122 ps
T666 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1780047499 May 05 04:41:45 PM PDT 24 May 05 04:52:21 PM PDT 24 3329046706 ps
T713 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3475079560 May 05 04:38:06 PM PDT 24 May 05 04:43:09 PM PDT 24 3108786260 ps
T1181 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1960198420 May 05 04:25:21 PM PDT 24 May 05 04:42:52 PM PDT 24 8537115350 ps
T732 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2553311649 May 05 04:50:04 PM PDT 24 May 05 05:01:06 PM PDT 24 4816283718 ps
T687 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2638316238 May 05 04:22:19 PM PDT 24 May 05 04:24:37 PM PDT 24 3497216383 ps
T51 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1809089589 May 05 04:37:36 PM PDT 24 May 05 04:42:48 PM PDT 24 3178469510 ps
T790 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.539249072 May 05 04:58:20 PM PDT 24 May 05 05:05:26 PM PDT 24 3951796254 ps
T141 /workspace/coverage/default/0.chip_jtag_csr_rw.788217331 May 05 04:15:31 PM PDT 24 May 05 04:33:05 PM PDT 24 12321694050 ps
T1182 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4108206773 May 05 04:22:03 PM PDT 24 May 05 04:25:49 PM PDT 24 3293282355 ps
T788 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1408101563 May 05 04:52:08 PM PDT 24 May 05 04:58:09 PM PDT 24 4298968620 ps
T1183 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1664559105 May 05 04:24:30 PM PDT 24 May 05 04:33:17 PM PDT 24 9684294181 ps
T29 /workspace/coverage/default/0.chip_sw_gpio.3019720796 May 05 04:22:29 PM PDT 24 May 05 04:30:18 PM PDT 24 3480283459 ps
T313 /workspace/coverage/default/1.chip_plic_all_irqs_20.3261954740 May 05 04:32:57 PM PDT 24 May 05 04:46:44 PM PDT 24 4675182152 ps
T1184 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3764635053 May 05 04:21:28 PM PDT 24 May 05 04:31:00 PM PDT 24 4426933300 ps
T760 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2508599443 May 05 04:52:34 PM PDT 24 May 05 05:02:08 PM PDT 24 5156221786 ps
T771 /workspace/coverage/default/48.chip_sw_all_escalation_resets.623540700 May 05 04:50:48 PM PDT 24 May 05 05:01:24 PM PDT 24 4684963856 ps
T1185 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2253152414 May 05 04:22:04 PM PDT 24 May 05 04:31:17 PM PDT 24 6020003168 ps
T796 /workspace/coverage/default/39.chip_sw_all_escalation_resets.660101559 May 05 04:50:44 PM PDT 24 May 05 05:00:16 PM PDT 24 4931697890 ps
T1186 /workspace/coverage/default/0.chip_sw_aes_masking_off.1289876991 May 05 04:23:11 PM PDT 24 May 05 04:28:21 PM PDT 24 3378382932 ps
T88 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3690056440 May 05 04:51:50 PM PDT 24 May 05 04:58:29 PM PDT 24 4502951492 ps
T1187 /workspace/coverage/default/0.chip_sw_example_concurrency.2169698881 May 05 04:20:15 PM PDT 24 May 05 04:23:44 PM PDT 24 2134591442 ps
T778 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1651795541 May 05 04:50:15 PM PDT 24 May 05 04:58:46 PM PDT 24 3890108168 ps
T664 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.576868567 May 05 04:43:05 PM PDT 24 May 05 05:35:08 PM PDT 24 24612865540 ps
T1188 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3744999041 May 05 04:46:01 PM PDT 24 May 05 04:54:56 PM PDT 24 3508724702 ps
T1189 /workspace/coverage/default/2.chip_sw_aes_entropy.2641968823 May 05 04:41:39 PM PDT 24 May 05 04:46:38 PM PDT 24 3306178462 ps
T1190 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3518798096 May 05 04:40:33 PM PDT 24 May 05 04:44:53 PM PDT 24 2704904726 ps
T1191 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2882613623 May 05 04:24:43 PM PDT 24 May 05 04:35:18 PM PDT 24 4303966707 ps
T1192 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1889578168 May 05 04:49:10 PM PDT 24 May 05 04:56:44 PM PDT 24 7211742865 ps
T1193 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3314007009 May 05 04:24:48 PM PDT 24 May 05 04:29:58 PM PDT 24 3363130492 ps
T1194 /workspace/coverage/default/0.chip_tap_straps_prod.1940135136 May 05 04:25:05 PM PDT 24 May 05 04:27:34 PM PDT 24 2110108465 ps
T1195 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3919325742 May 05 04:38:53 PM PDT 24 May 05 04:40:41 PM PDT 24 1785071485 ps
T1196 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1521365018 May 05 04:45:58 PM PDT 24 May 05 05:06:58 PM PDT 24 8468627472 ps
T1197 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.113406092 May 05 04:30:32 PM PDT 24 May 05 04:35:46 PM PDT 24 2825490740 ps
T1198 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2798121411 May 05 04:39:56 PM PDT 24 May 05 04:53:04 PM PDT 24 7631698272 ps
T387 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.625647787 May 05 04:34:33 PM PDT 24 May 05 04:43:50 PM PDT 24 7276537360 ps
T1199 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3533823931 May 05 04:35:23 PM PDT 24 May 05 04:39:48 PM PDT 24 3183136322 ps
T1200 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.276776510 May 05 04:34:06 PM PDT 24 May 05 04:53:10 PM PDT 24 6589754744 ps
T237 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3990289507 May 05 04:49:16 PM PDT 24 May 05 04:58:29 PM PDT 24 4788418658 ps
T1201 /workspace/coverage/default/0.chip_sw_example_manufacturer.2888428006 May 05 04:23:08 PM PDT 24 May 05 04:27:36 PM PDT 24 2653203752 ps
T1202 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4080085286 May 05 04:32:56 PM PDT 24 May 05 05:20:46 PM PDT 24 25713864632 ps
T1203 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4080739591 May 05 04:38:47 PM PDT 24 May 05 04:48:56 PM PDT 24 4364411478 ps
T1204 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3490809882 May 05 04:33:27 PM PDT 24 May 05 04:45:06 PM PDT 24 3793110030 ps
T131 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3580822446 May 05 04:45:21 PM PDT 24 May 05 04:59:46 PM PDT 24 5597487380 ps
T300 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1521083345 May 05 04:38:38 PM PDT 24 May 05 05:04:04 PM PDT 24 11943627464 ps
T773 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470597038 May 05 04:46:29 PM PDT 24 May 05 04:54:33 PM PDT 24 3788938158 ps
T1205 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2531825219 May 05 04:24:11 PM PDT 24 May 05 04:32:40 PM PDT 24 4958286780 ps
T1206 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.394175727 May 05 04:37:21 PM PDT 24 May 05 04:41:11 PM PDT 24 2017355808 ps
T30 /workspace/coverage/default/2.chip_sw_gpio.4123228258 May 05 04:39:02 PM PDT 24 May 05 04:49:16 PM PDT 24 4375992856 ps
T155 /workspace/coverage/default/43.chip_sw_all_escalation_resets.2485884940 May 05 04:54:43 PM PDT 24 May 05 05:06:09 PM PDT 24 6018500320 ps
T238 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1951242564 May 05 04:31:30 PM PDT 24 May 05 04:42:58 PM PDT 24 5031136200 ps
T1207 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3696919167 May 05 04:41:55 PM PDT 24 May 05 04:52:48 PM PDT 24 4880499636 ps
T277 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2302798864 May 05 04:44:15 PM PDT 24 May 05 04:49:40 PM PDT 24 3286661703 ps
T1208 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.321495913 May 05 04:45:25 PM PDT 24 May 05 04:58:52 PM PDT 24 10544366231 ps
T316 /workspace/coverage/default/0.chip_sw_pattgen_ios.1246822623 May 05 04:21:47 PM PDT 24 May 05 04:28:00 PM PDT 24 3771787224 ps
T1209 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444775909 May 05 04:49:31 PM PDT 24 May 05 04:56:48 PM PDT 24 3880697544 ps
T1210 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3235399295 May 05 04:42:30 PM PDT 24 May 05 04:50:54 PM PDT 24 3441957282 ps
T1211 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.872408584 May 05 04:37:49 PM PDT 24 May 05 04:42:34 PM PDT 24 3095166184 ps
T1212 /workspace/coverage/default/2.chip_sw_power_idle_load.2634767852 May 05 04:42:23 PM PDT 24 May 05 04:53:49 PM PDT 24 4754504120 ps
T787 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2527429083 May 05 04:47:47 PM PDT 24 May 05 04:56:41 PM PDT 24 5470160990 ps
T722 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.774289760 May 05 04:22:41 PM PDT 24 May 05 04:37:41 PM PDT 24 4637356090 ps
T1213 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908669635 May 05 04:50:11 PM PDT 24 May 05 04:56:05 PM PDT 24 3850693980 ps
T684 /workspace/coverage/default/2.chip_tap_straps_dev.3671471812 May 05 04:42:34 PM PDT 24 May 05 04:52:32 PM PDT 24 6082230686 ps
T211 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1251140323 May 05 04:34:22 PM PDT 24 May 05 05:09:23 PM PDT 24 24715878155 ps
T1214 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1468495442 May 05 04:52:33 PM PDT 24 May 05 05:03:52 PM PDT 24 5567299520 ps
T148 /workspace/coverage/default/1.chip_plic_all_irqs_10.1108416364 May 05 04:32:48 PM PDT 24 May 05 04:43:07 PM PDT 24 3520248400 ps
T1215 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.841372384 May 05 04:24:15 PM PDT 24 May 05 04:31:20 PM PDT 24 5030927128 ps
T1216 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2448541282 May 05 04:40:28 PM PDT 24 May 05 04:51:11 PM PDT 24 4828737624 ps
T723 /workspace/coverage/default/1.chip_sw_pattgen_ios.1942559470 May 05 04:26:35 PM PDT 24 May 05 04:30:36 PM PDT 24 2275420080 ps
T1217 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4059638893 May 05 04:24:31 PM PDT 24 May 05 04:38:18 PM PDT 24 8495826757 ps
T1218 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1739832068 May 05 04:35:23 PM PDT 24 May 05 04:48:22 PM PDT 24 4427249440 ps
T1219 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1200043012 May 05 04:23:11 PM PDT 24 May 05 04:28:35 PM PDT 24 3832870776 ps
T1220 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3695687108 May 05 04:36:49 PM PDT 24 May 05 04:49:23 PM PDT 24 5927754200 ps
T352 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3969821531 May 05 04:36:57 PM PDT 24 May 05 04:51:07 PM PDT 24 4765154856 ps
T1221 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3677715383 May 05 04:41:53 PM PDT 24 May 05 04:45:08 PM PDT 24 1877981194 ps
T1222 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3113320169 May 05 04:24:24 PM PDT 24 May 05 04:33:28 PM PDT 24 3821233250 ps
T714 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.918300179 May 05 04:22:16 PM PDT 24 May 05 04:25:30 PM PDT 24 3442339440 ps
T789 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.837618958 May 05 04:51:06 PM PDT 24 May 05 04:58:38 PM PDT 24 3766152072 ps
T1223 /workspace/coverage/default/1.chip_sw_example_manufacturer.719748429 May 05 04:29:59 PM PDT 24 May 05 04:33:49 PM PDT 24 3216478492 ps
T1224 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2356868135 May 05 04:28:18 PM PDT 24 May 05 04:40:50 PM PDT 24 5714387465 ps
T70 /workspace/coverage/cover_reg_top/94.xbar_same_source.2715398176 May 05 04:12:40 PM PDT 24 May 05 04:13:45 PM PDT 24 1960768983 ps
T71 /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1477411179 May 05 04:00:09 PM PDT 24 May 05 04:12:14 PM PDT 24 67658817746 ps
T72 /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.844434291 May 05 03:47:00 PM PDT 24 May 05 04:01:48 PM PDT 24 50151421160 ps
T221 /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1563266179 May 05 04:10:28 PM PDT 24 May 05 04:11:44 PM PDT 24 7205729172 ps
T222 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3380873971 May 05 03:54:49 PM PDT 24 May 05 04:12:26 PM PDT 24 97022395735 ps
T509 /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2881991202 May 05 03:59:51 PM PDT 24 May 05 04:02:04 PM PDT 24 11764327904 ps
T518 /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.795208633 May 05 04:01:57 PM PDT 24 May 05 04:03:18 PM PDT 24 6757030038 ps
T462 /workspace/coverage/cover_reg_top/93.xbar_same_source.302919658 May 05 04:12:34 PM PDT 24 May 05 04:13:10 PM PDT 24 1265616543 ps
T386 /workspace/coverage/cover_reg_top/9.xbar_stress_all.1863570718 May 05 03:49:14 PM PDT 24 May 05 03:55:49 PM PDT 24 10616960177 ps
T511 /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.49405652 May 05 04:09:26 PM PDT 24 May 05 04:09:55 PM PDT 24 352611285 ps
T434 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3611063472 May 05 04:13:40 PM PDT 24 May 05 04:20:31 PM PDT 24 4889458018 ps
T519 /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2293978207 May 05 04:08:36 PM PDT 24 May 05 04:10:27 PM PDT 24 6343626463 ps
T514 /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2435989317 May 05 03:54:06 PM PDT 24 May 05 03:54:16 PM PDT 24 116335597 ps
T517 /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3407483003 May 05 03:50:11 PM PDT 24 May 05 03:52:00 PM PDT 24 6221057196 ps
T516 /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.767646807 May 05 04:05:00 PM PDT 24 May 05 04:05:07 PM PDT 24 45064605 ps
T520 /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3622633299 May 05 04:00:16 PM PDT 24 May 05 04:00:24 PM PDT 24 49754138 ps
T424 /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.354053330 May 05 03:50:29 PM PDT 24 May 05 04:27:48 PM PDT 24 121549807759 ps
T451 /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.885942717 May 05 04:09:04 PM PDT 24 May 05 04:28:35 PM PDT 24 99493198664 ps
T417 /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3072342110 May 05 04:05:54 PM PDT 24 May 05 04:06:19 PM PDT 24 575453983 ps
T142 /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1900512631 May 05 03:44:54 PM PDT 24 May 05 05:18:45 PM PDT 24 35943631304 ps
T418 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3138344141 May 05 03:54:07 PM PDT 24 May 05 03:54:39 PM PDT 24 87481687 ps
T380 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2809473895 May 05 04:11:29 PM PDT 24 May 05 04:26:13 PM PDT 24 13892068940 ps
T508 /workspace/coverage/cover_reg_top/36.xbar_access_same_device.4291346704 May 05 04:00:07 PM PDT 24 May 05 04:02:17 PM PDT 24 2812420902 ps
T801 /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3712819454 May 05 03:58:45 PM PDT 24 May 05 04:12:33 PM PDT 24 47103668586 ps
T484 /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1651707872 May 05 03:59:53 PM PDT 24 May 05 04:00:00 PM PDT 24 49814097 ps
T419 /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3016180217 May 05 04:04:39 PM PDT 24 May 05 04:05:24 PM PDT 24 989169330 ps
T829 /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1247484046 May 05 04:07:08 PM PDT 24 May 05 04:07:21 PM PDT 24 127137516 ps
T1225 /workspace/coverage/cover_reg_top/56.xbar_smoke.2771629040 May 05 04:04:59 PM PDT 24 May 05 04:05:09 PM PDT 24 222510184 ps
T510 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.804079746 May 05 04:05:56 PM PDT 24 May 05 04:09:38 PM PDT 24 5489887178 ps
T513 /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.165155553 May 05 04:13:25 PM PDT 24 May 05 04:14:20 PM PDT 24 1467996970 ps
T395 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1861451306 May 05 04:09:55 PM PDT 24 May 05 04:17:17 PM PDT 24 7139872008 ps
T1226 /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3958661549 May 05 04:12:00 PM PDT 24 May 05 04:13:12 PM PDT 24 4280382249 ps
T139 /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1484975522 May 05 03:44:56 PM PDT 24 May 05 04:18:22 PM PDT 24 15846358525 ps
T558 /workspace/coverage/cover_reg_top/14.xbar_random.1564113876 May 05 03:52:00 PM PDT 24 May 05 03:52:55 PM PDT 24 1605518689 ps
T606 /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1246720850 May 05 03:57:37 PM PDT 24 May 05 03:59:11 PM PDT 24 5623151032 ps
T515 /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1893493834 May 05 04:09:59 PM PDT 24 May 05 04:10:47 PM PDT 24 478576730 ps
T626 /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3718304463 May 05 03:51:25 PM PDT 24 May 05 03:51:32 PM PDT 24 51023141 ps
T512 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2783277034 May 05 04:08:30 PM PDT 24 May 05 04:15:22 PM PDT 24 7772068935 ps
T579 /workspace/coverage/cover_reg_top/61.xbar_same_source.1065739277 May 05 04:06:24 PM PDT 24 May 05 04:07:06 PM PDT 24 1301783023 ps
T1227 /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3606193723 May 05 04:11:32 PM PDT 24 May 05 04:11:38 PM PDT 24 41502529 ps
T1228 /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2487727786 May 05 04:05:05 PM PDT 24 May 05 04:05:11 PM PDT 24 21041535 ps
T830 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3554292256 May 05 04:02:04 PM PDT 24 May 05 04:03:33 PM PDT 24 165200500 ps
T811 /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1520594612 May 05 03:43:58 PM PDT 24 May 05 03:44:24 PM PDT 24 225673481 ps
T615 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2699914627 May 05 04:06:31 PM PDT 24 May 05 04:08:05 PM PDT 24 5646387986 ps
T480 /workspace/coverage/cover_reg_top/86.xbar_stress_all.673342134 May 05 04:11:15 PM PDT 24 May 05 04:16:55 PM PDT 24 3719399586 ps
T534 /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4227258100 May 05 03:45:08 PM PDT 24 May 05 03:46:58 PM PDT 24 6305521615 ps
T820 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1145390814 May 05 04:12:50 PM PDT 24 May 05 04:54:19 PM PDT 24 130134139984 ps
T572 /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.568100968 May 05 04:05:21 PM PDT 24 May 05 04:05:32 PM PDT 24 82870598 ps
T678 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.521835538 May 05 04:09:47 PM PDT 24 May 05 04:11:23 PM PDT 24 306600303 ps
T504 /workspace/coverage/cover_reg_top/95.xbar_stress_all.833062034 May 05 04:12:54 PM PDT 24 May 05 04:14:39 PM PDT 24 3134343827 ps
T620 /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3460958617 May 05 03:59:28 PM PDT 24 May 05 04:00:28 PM PDT 24 5383441145 ps
T1229 /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3790690592 May 05 04:05:30 PM PDT 24 May 05 04:05:36 PM PDT 24 38484467 ps
T334 /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3560647922 May 05 03:44:15 PM PDT 24 May 05 06:17:52 PM PDT 24 55929878740 ps
T429 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2285812634 May 05 03:49:14 PM PDT 24 May 05 03:55:16 PM PDT 24 2189731585 ps
T596 /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.678247467 May 05 04:06:48 PM PDT 24 May 05 04:08:17 PM PDT 24 7726985146 ps
T526 /workspace/coverage/cover_reg_top/14.chip_tl_errors.2069680402 May 05 03:51:53 PM PDT 24 May 05 03:55:55 PM PDT 24 3469931935 ps
T861 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1352050547 May 05 03:52:38 PM PDT 24 May 05 03:54:04 PM PDT 24 272319279 ps
T442 /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3276566228 May 05 03:57:48 PM PDT 24 May 05 04:16:12 PM PDT 24 96405341295 ps
T812 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.654233803 May 05 04:00:23 PM PDT 24 May 05 04:12:10 PM PDT 24 41754551196 ps
T594 /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3873284228 May 05 03:55:29 PM PDT 24 May 05 03:57:29 PM PDT 24 12199010230 ps
T500 /workspace/coverage/cover_reg_top/81.xbar_stress_all.2120805654 May 05 04:10:27 PM PDT 24 May 05 04:12:39 PM PDT 24 1413848076 ps
T705 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1637367267 May 05 03:58:06 PM PDT 24 May 05 03:59:26 PM PDT 24 943970256 ps
T360 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2673903619 May 05 03:43:35 PM PDT 24 May 05 03:51:21 PM PDT 24 5008017893 ps
T584 /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.999643728 May 05 04:01:57 PM PDT 24 May 05 04:02:36 PM PDT 24 412367943 ps
T1230 /workspace/coverage/cover_reg_top/19.xbar_error_random.2923675526 May 05 03:54:30 PM PDT 24 May 05 03:54:37 PM PDT 24 47100749 ps
T679 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3687368659 May 05 03:53:20 PM PDT 24 May 05 03:58:00 PM PDT 24 4887403129 ps
T573 /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3739054207 May 05 04:08:15 PM PDT 24 May 05 04:08:27 PM PDT 24 72798575 ps
T601 /workspace/coverage/cover_reg_top/5.xbar_same_source.1164742267 May 05 03:47:04 PM PDT 24 May 05 03:47:19 PM PDT 24 471967018 ps
T597 /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1998521109 May 05 03:46:59 PM PDT 24 May 05 03:51:16 PM PDT 24 23373106777 ps
T1231 /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1101617236 May 05 04:09:55 PM PDT 24 May 05 04:10:25 PM PDT 24 266657266 ps
T624 /workspace/coverage/cover_reg_top/6.xbar_smoke.3367155679 May 05 03:47:19 PM PDT 24 May 05 03:47:26 PM PDT 24 49679857 ps
T1232 /workspace/coverage/cover_reg_top/88.xbar_smoke.506863657 May 05 04:11:37 PM PDT 24 May 05 04:11:48 PM PDT 24 249412747 ps
T649 /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.467825575 May 05 04:08:42 PM PDT 24 May 05 04:10:01 PM PDT 24 7643155150 ps
T611 /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1499762379 May 05 04:08:25 PM PDT 24 May 05 04:13:49 PM PDT 24 16712339309 ps
T863 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.994347357 May 05 04:07:54 PM PDT 24 May 05 04:08:08 PM PDT 24 9789046 ps
T443 /workspace/coverage/cover_reg_top/93.xbar_stress_all.2507513406 May 05 04:12:38 PM PDT 24 May 05 04:15:21 PM PDT 24 4635062703 ps
T629 /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2090168380 May 05 03:46:19 PM PDT 24 May 05 03:46:54 PM PDT 24 359744938 ps
T427 /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3569727821 May 05 04:02:11 PM PDT 24 May 05 04:16:14 PM PDT 24 83851401516 ps
T1233 /workspace/coverage/cover_reg_top/22.xbar_error_random.2641517673 May 05 03:55:42 PM PDT 24 May 05 03:55:52 PM PDT 24 185535069 ps
T806 /workspace/coverage/cover_reg_top/9.xbar_error_random.2387733294 May 05 03:49:14 PM PDT 24 May 05 03:49:39 PM PDT 24 571250191 ps
T1234 /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.636649409 May 05 03:59:54 PM PDT 24 May 05 04:00:32 PM PDT 24 875432802 ps
T807 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1114662649 May 05 03:51:00 PM PDT 24 May 05 04:15:19 PM PDT 24 76107617466 ps
T1235 /workspace/coverage/cover_reg_top/3.xbar_smoke.3599698010 May 05 03:45:40 PM PDT 24 May 05 03:45:51 PM PDT 24 182349452 ps
T503 /workspace/coverage/cover_reg_top/61.xbar_stress_all.3836770618 May 05 04:06:25 PM PDT 24 May 05 04:09:09 PM PDT 24 3778251334 ps
T802 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.715553952 May 05 04:04:30 PM PDT 24 May 05 04:08:18 PM PDT 24 5130963908 ps
T1236 /workspace/coverage/cover_reg_top/85.xbar_error_random.3808104633 May 05 04:11:07 PM PDT 24 May 05 04:11:52 PM PDT 24 1414495063 ps
T550 /workspace/coverage/cover_reg_top/12.xbar_random.746446208 May 05 03:50:52 PM PDT 24 May 05 03:51:30 PM PDT 24 390429061 ps
T585 /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.516600795 May 05 03:57:03 PM PDT 24 May 05 03:57:26 PM PDT 24 211378641 ps
T1237 /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2362523081 May 05 04:04:00 PM PDT 24 May 05 04:04:07 PM PDT 24 50869958 ps
T818 /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1328582727 May 05 04:06:52 PM PDT 24 May 05 04:07:19 PM PDT 24 605947843 ps
T827 /workspace/coverage/cover_reg_top/91.xbar_access_same_device.741722606 May 05 04:12:18 PM PDT 24 May 05 04:13:10 PM PDT 24 1247146098 ps
T675 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.682968836 May 05 03:46:42 PM PDT 24 May 05 03:59:32 PM PDT 24 18613666694 ps
T845 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.4008341067 May 05 04:10:51 PM PDT 24 May 05 04:16:08 PM PDT 24 806577771 ps
T852 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1981221475 May 05 03:45:27 PM PDT 24 May 05 03:47:13 PM PDT 24 205862813 ps
T1238 /workspace/coverage/cover_reg_top/26.xbar_same_source.3300131731 May 05 03:57:06 PM PDT 24 May 05 03:57:15 PM PDT 24 197029140 ps
T485 /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1783775812 May 05 04:07:20 PM PDT 24 May 05 04:11:43 PM PDT 24 1263732588 ps
T676 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2363377981 May 05 03:59:48 PM PDT 24 May 05 04:06:03 PM PDT 24 4794987649 ps
T1239 /workspace/coverage/cover_reg_top/27.xbar_error_random.1586978122 May 05 03:57:24 PM PDT 24 May 05 03:58:55 PM PDT 24 2409135616 ps
T553 /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1870202286 May 05 03:53:05 PM PDT 24 May 05 04:11:56 PM PDT 24 104581042637 ps
T595 /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2914943784 May 05 04:10:31 PM PDT 24 May 05 04:23:16 PM PDT 24 42273956912 ps
T840 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1250936024 May 05 03:49:18 PM PDT 24 May 05 03:50:47 PM PDT 24 292118916 ps
T529 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3872143474 May 05 04:12:13 PM PDT 24 May 05 04:34:06 PM PDT 24 99368112078 ps
T468 /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.843192799 May 05 04:09:48 PM PDT 24 May 05 04:20:28 PM PDT 24 38825746365 ps
T525 /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3109916352 May 05 04:07:16 PM PDT 24 May 05 04:07:38 PM PDT 24 149646577 ps
T447 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1773156475 May 05 04:09:09 PM PDT 24 May 05 04:21:06 PM PDT 24 12712456093 ps
T532 /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.704835543 May 05 03:59:20 PM PDT 24 May 05 04:15:35 PM PDT 24 57235707644 ps
T448 /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2802264897 May 05 03:50:27 PM PDT 24 May 05 03:51:01 PM PDT 24 363052388 ps
T449 /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1393403214 May 05 04:02:35 PM PDT 24 May 05 04:03:47 PM PDT 24 3929278999 ps
T564 /workspace/coverage/cover_reg_top/29.xbar_random.1404631653 May 05 03:58:02 PM PDT 24 May 05 03:58:19 PM PDT 24 168438796 ps
T1240 /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2491778090 May 05 04:11:05 PM PDT 24 May 05 04:12:28 PM PDT 24 7548649551 ps
T488 /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.710939234 May 05 04:11:25 PM PDT 24 May 05 04:12:12 PM PDT 24 630524118 ps
T565 /workspace/coverage/cover_reg_top/23.xbar_same_source.236611589 May 05 03:55:58 PM PDT 24 May 05 03:57:06 PM PDT 24 1893699650 ps
T476 /workspace/coverage/cover_reg_top/2.xbar_random.2000325888 May 05 03:45:10 PM PDT 24 May 05 03:45:50 PM PDT 24 842454687 ps
T1241 /workspace/coverage/cover_reg_top/89.xbar_error_random.2929161677 May 05 04:12:01 PM PDT 24 May 05 04:12:30 PM PDT 24 813303437 ps
T823 /workspace/coverage/cover_reg_top/77.xbar_access_same_device.3254777415 May 05 04:09:38 PM PDT 24 May 05 04:10:35 PM PDT 24 702658916 ps
T591 /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2777636686 May 05 04:11:37 PM PDT 24 May 05 04:29:58 PM PDT 24 63108725635 ps
T598 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.491299114 May 05 04:11:09 PM PDT 24 May 05 04:12:43 PM PDT 24 5698101743 ps
T1242 /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.832263224 May 05 04:11:09 PM PDT 24 May 05 04:11:16 PM PDT 24 48114225 ps
T810 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.442023607 May 05 04:09:29 PM PDT 24 May 05 04:45:16 PM PDT 24 107687428027 ps
T848 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2624319345 May 05 04:05:56 PM PDT 24 May 05 04:08:55 PM PDT 24 896254597 ps
T470 /workspace/coverage/cover_reg_top/45.xbar_smoke.1047444057 May 05 04:02:18 PM PDT 24 May 05 04:02:24 PM PDT 24 40432712 ps
T1243 /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4227164458 May 05 03:59:55 PM PDT 24 May 05 04:01:38 PM PDT 24 5755364296 ps
T1244 /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.612750463 May 05 04:05:44 PM PDT 24 May 05 04:05:50 PM PDT 24 43436068 ps
T613 /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.441016378 May 05 03:49:37 PM PDT 24 May 05 03:49:44 PM PDT 24 51705172 ps
T437 /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.2270264978 May 05 04:11:15 PM PDT 24 May 05 04:22:47 PM PDT 24 58556456001 ps
T1245 /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.464802923 May 05 03:43:46 PM PDT 24 May 05 03:45:40 PM PDT 24 6246048668 ps
T1246 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3673241669 May 05 03:48:47 PM PDT 24 May 05 03:49:57 PM PDT 24 171243772 ps
T127 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2147059048 May 05 03:44:52 PM PDT 24 May 05 03:50:27 PM PDT 24 7295793036 ps
T1247 /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.478449402 May 05 04:02:41 PM PDT 24 May 05 04:04:51 PM PDT 24 1956358761 ps
T1248 /workspace/coverage/cover_reg_top/64.xbar_error_random.3345252848 May 05 04:06:59 PM PDT 24 May 05 04:07:35 PM PDT 24 445686693 ps
T552 /workspace/coverage/cover_reg_top/37.xbar_same_source.3808439677 May 05 04:00:28 PM PDT 24 May 05 04:00:44 PM PDT 24 476634966 ps
T1249 /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2426408497 May 05 04:01:51 PM PDT 24 May 05 04:01:58 PM PDT 24 50769995 ps
T1250 /workspace/coverage/cover_reg_top/27.xbar_smoke.3030803318 May 05 03:57:14 PM PDT 24 May 05 03:57:21 PM PDT 24 50401737 ps
T1251 /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1306431195 May 05 03:48:22 PM PDT 24 May 05 03:49:47 PM PDT 24 7651247346 ps
T1252 /workspace/coverage/cover_reg_top/63.xbar_error_random.508870732 May 05 04:06:47 PM PDT 24 May 05 04:06:58 PM PDT 24 102220543 ps
T815 /workspace/coverage/cover_reg_top/55.xbar_access_same_device.101146492 May 05 04:04:50 PM PDT 24 May 05 04:05:57 PM PDT 24 1732708794 ps
T826 /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.218522542 May 05 04:01:30 PM PDT 24 May 05 04:11:21 PM PDT 24 35054030611 ps
T556 /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1972264133 May 05 04:11:32 PM PDT 24 May 05 04:13:20 PM PDT 24 10080620964 ps
T1253 /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1535655772 May 05 03:49:14 PM PDT 24 May 05 03:49:32 PM PDT 24 151893546 ps
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