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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.29 95.41 94.46 95.56 95.36 97.38 99.57


Total test records in report: 2771
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T187 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1001988200 May 07 04:39:36 PM PDT 24 May 07 04:57:37 PM PDT 24 7563688520 ps
T397 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2690491115 May 07 04:28:30 PM PDT 24 May 07 05:00:55 PM PDT 24 8739265110 ps
T151 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406733191 May 07 04:49:03 PM PDT 24 May 07 04:57:15 PM PDT 24 3784940216 ps
T24 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.421875176 May 07 04:39:23 PM PDT 24 May 07 04:43:27 PM PDT 24 3119945090 ps
T739 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1988805147 May 07 04:53:15 PM PDT 24 May 07 05:03:55 PM PDT 24 5566199320 ps
T744 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3645892021 May 07 04:52:34 PM PDT 24 May 07 05:03:54 PM PDT 24 4649351728 ps
T219 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4114715725 May 07 04:41:26 PM PDT 24 May 07 05:01:33 PM PDT 24 11164206352 ps
T248 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3887955587 May 07 04:25:07 PM PDT 24 May 07 04:33:08 PM PDT 24 4050561553 ps
T929 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2683124263 May 07 04:33:11 PM PDT 24 May 07 04:36:08 PM PDT 24 2251436202 ps
T210 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1085915257 May 07 04:35:53 PM PDT 24 May 07 04:46:27 PM PDT 24 4806369504 ps
T261 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3566864064 May 07 04:27:30 PM PDT 24 May 07 04:35:16 PM PDT 24 5596540759 ps
T930 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4039179327 May 07 04:35:09 PM PDT 24 May 07 04:45:58 PM PDT 24 4275386792 ps
T931 /workspace/coverage/default/3.chip_tap_straps_prod.522032574 May 07 04:49:59 PM PDT 24 May 07 05:03:46 PM PDT 24 10134269821 ps
T152 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.691341937 May 07 04:24:28 PM PDT 24 May 07 07:47:17 PM PDT 24 255558353432 ps
T79 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2123380331 May 07 04:25:04 PM PDT 24 May 07 04:49:11 PM PDT 24 10539475836 ps
T932 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1336560545 May 07 04:28:59 PM PDT 24 May 07 04:32:14 PM PDT 24 2392974080 ps
T676 /workspace/coverage/default/0.chip_tap_straps_dev.2374826946 May 07 04:25:24 PM PDT 24 May 07 04:53:32 PM PDT 24 14162791581 ps
T812 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3283408369 May 07 04:53:36 PM PDT 24 May 07 04:58:40 PM PDT 24 3630822360 ps
T933 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3595352473 May 07 04:43:04 PM PDT 24 May 07 04:47:53 PM PDT 24 2772684872 ps
T684 /workspace/coverage/default/80.chip_sw_all_escalation_resets.307208489 May 07 04:54:53 PM PDT 24 May 07 05:02:50 PM PDT 24 4669475304 ps
T262 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1122149376 May 07 04:46:50 PM PDT 24 May 07 04:57:07 PM PDT 24 5382887800 ps
T934 /workspace/coverage/default/1.chip_sw_example_manufacturer.2367604873 May 07 04:30:57 PM PDT 24 May 07 04:34:52 PM PDT 24 3352469354 ps
T935 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1589583014 May 07 04:30:25 PM PDT 24 May 07 04:37:27 PM PDT 24 3190336276 ps
T331 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2584998753 May 07 04:51:55 PM PDT 24 May 07 05:01:31 PM PDT 24 5641746328 ps
T936 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.224351778 May 07 04:30:34 PM PDT 24 May 07 04:35:36 PM PDT 24 2946215370 ps
T328 /workspace/coverage/default/0.chip_sw_hmac_enc.3008511651 May 07 04:26:08 PM PDT 24 May 07 04:29:30 PM PDT 24 2523099832 ps
T294 /workspace/coverage/default/2.chip_plic_all_irqs_0.3060623558 May 07 04:44:41 PM PDT 24 May 07 05:03:25 PM PDT 24 6588564898 ps
T937 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2124583989 May 07 04:31:16 PM PDT 24 May 07 04:36:32 PM PDT 24 3211190712 ps
T938 /workspace/coverage/default/1.chip_sw_hmac_enc.3585026618 May 07 04:34:28 PM PDT 24 May 07 04:39:27 PM PDT 24 3159485224 ps
T811 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3257327450 May 07 04:56:29 PM PDT 24 May 07 05:07:26 PM PDT 24 5310014424 ps
T939 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3071775163 May 07 04:45:43 PM PDT 24 May 07 05:00:55 PM PDT 24 7608355166 ps
T722 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2467493822 May 07 04:54:13 PM PDT 24 May 07 05:00:10 PM PDT 24 4194923844 ps
T200 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2732873249 May 07 04:40:47 PM PDT 24 May 07 06:13:53 PM PDT 24 48665416392 ps
T940 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.684613448 May 07 04:27:30 PM PDT 24 May 07 04:44:46 PM PDT 24 6222300110 ps
T720 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.687518033 May 07 04:54:59 PM PDT 24 May 07 05:02:03 PM PDT 24 4162298816 ps
T737 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3027283359 May 07 04:37:32 PM PDT 24 May 07 04:45:14 PM PDT 24 3662334752 ps
T20 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2641670186 May 07 04:41:52 PM PDT 24 May 07 05:07:35 PM PDT 24 21729895384 ps
T105 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.962658372 May 07 04:45:55 PM PDT 24 May 07 05:38:36 PM PDT 24 23357734619 ps
T173 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1877570258 May 07 04:36:50 PM PDT 24 May 07 04:40:33 PM PDT 24 2888515883 ps
T268 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2886357882 May 07 04:52:58 PM PDT 24 May 07 05:01:05 PM PDT 24 5052042684 ps
T941 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2556943298 May 07 04:43:23 PM PDT 24 May 07 04:57:26 PM PDT 24 6813992156 ps
T22 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.460513492 May 07 04:22:47 PM PDT 24 May 07 06:09:28 PM PDT 24 31105982618 ps
T942 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3994318949 May 07 04:40:27 PM PDT 24 May 07 04:58:17 PM PDT 24 6513905679 ps
T53 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.398026564 May 07 04:23:04 PM PDT 24 May 07 04:29:32 PM PDT 24 4339250002 ps
T943 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1856565289 May 07 04:25:19 PM PDT 24 May 07 04:57:16 PM PDT 24 19040738276 ps
T944 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1690328825 May 07 04:24:09 PM PDT 24 May 07 04:32:00 PM PDT 24 6821176412 ps
T134 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2561652162 May 07 04:25:09 PM PDT 24 May 07 04:28:54 PM PDT 24 2945774409 ps
T63 /workspace/coverage/default/0.chip_tap_straps_rma.3812618136 May 07 04:32:49 PM PDT 24 May 07 04:40:12 PM PDT 24 4976474314 ps
T945 /workspace/coverage/default/1.chip_sw_power_idle_load.3546128707 May 07 04:36:21 PM PDT 24 May 07 04:46:34 PM PDT 24 4555130360 ps
T203 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2272118876 May 07 04:46:06 PM PDT 24 May 07 06:11:56 PM PDT 24 47668342025 ps
T733 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3469485388 May 07 04:57:30 PM PDT 24 May 07 05:02:27 PM PDT 24 3142933432 ps
T329 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.262431241 May 07 04:44:04 PM PDT 24 May 07 04:58:32 PM PDT 24 4539064224 ps
T946 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.433299153 May 07 04:33:46 PM PDT 24 May 07 04:43:41 PM PDT 24 4841947168 ps
T947 /workspace/coverage/default/2.chip_sw_uart_smoketest.1281080869 May 07 04:49:32 PM PDT 24 May 07 04:53:06 PM PDT 24 2716983032 ps
T21 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.566426257 May 07 04:31:50 PM PDT 24 May 07 05:30:59 PM PDT 24 20926525200 ps
T235 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2698380945 May 07 04:33:16 PM PDT 24 May 07 04:39:09 PM PDT 24 3670206327 ps
T154 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3800547140 May 07 04:41:10 PM PDT 24 May 07 04:42:43 PM PDT 24 2005580397 ps
T948 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4044263999 May 07 04:37:53 PM PDT 24 May 07 04:42:48 PM PDT 24 2973853769 ps
T322 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1110592762 May 07 04:43:08 PM PDT 24 May 07 04:55:33 PM PDT 24 18358138696 ps
T148 /workspace/coverage/default/1.chip_plic_all_irqs_10.581050454 May 07 04:35:36 PM PDT 24 May 07 04:45:32 PM PDT 24 4112866160 ps
T949 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3915769055 May 07 04:24:29 PM PDT 24 May 07 04:34:50 PM PDT 24 7529602938 ps
T950 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3197937852 May 07 04:34:12 PM PDT 24 May 07 04:43:34 PM PDT 24 7715740460 ps
T951 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1460478808 May 07 04:34:53 PM PDT 24 May 07 04:39:55 PM PDT 24 2487852180 ps
T119 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1658965856 May 07 04:39:25 PM PDT 24 May 07 04:46:58 PM PDT 24 4859349272 ps
T952 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2333628928 May 07 04:47:17 PM PDT 24 May 07 05:10:12 PM PDT 24 13971300039 ps
T953 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4216669613 May 07 04:40:35 PM PDT 24 May 07 04:45:17 PM PDT 24 3550947322 ps
T954 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4289079075 May 07 04:33:15 PM PDT 24 May 07 04:42:43 PM PDT 24 4254246228 ps
T955 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2165268256 May 07 04:34:25 PM PDT 24 May 07 08:02:48 PM PDT 24 256323880600 ps
T805 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261687112 May 07 04:54:42 PM PDT 24 May 07 05:00:59 PM PDT 24 3749781868 ps
T783 /workspace/coverage/default/10.chip_sw_all_escalation_resets.2710093928 May 07 04:50:31 PM PDT 24 May 07 05:02:24 PM PDT 24 6315255840 ps
T956 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2295788591 May 07 04:27:34 PM PDT 24 May 07 04:36:44 PM PDT 24 4260727720 ps
T957 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1280004457 May 07 04:37:37 PM PDT 24 May 07 04:56:45 PM PDT 24 7392219078 ps
T958 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1333177843 May 07 04:26:17 PM PDT 24 May 07 04:54:46 PM PDT 24 9097352620 ps
T155 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3332943991 May 07 04:24:19 PM PDT 24 May 07 04:27:43 PM PDT 24 2903680626 ps
T181 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3927344294 May 07 04:29:33 PM PDT 24 May 07 04:37:16 PM PDT 24 4518989762 ps
T713 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439013110 May 07 04:54:31 PM PDT 24 May 07 04:59:44 PM PDT 24 3502101590 ps
T771 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3124773009 May 07 04:55:28 PM PDT 24 May 07 05:01:46 PM PDT 24 3586692556 ps
T959 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2004660617 May 07 04:42:07 PM PDT 24 May 07 04:51:39 PM PDT 24 5088941316 ps
T960 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.559774931 May 07 04:48:10 PM PDT 24 May 07 04:53:21 PM PDT 24 3136769836 ps
T961 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4063528967 May 07 04:25:57 PM PDT 24 May 07 04:35:27 PM PDT 24 4779094130 ps
T962 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3232787436 May 07 04:48:14 PM PDT 24 May 07 04:55:18 PM PDT 24 4051694920 ps
T963 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1775656009 May 07 04:42:15 PM PDT 24 May 07 05:04:23 PM PDT 24 7352247048 ps
T718 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3922785563 May 07 04:53:39 PM PDT 24 May 07 04:58:54 PM PDT 24 3694209910 ps
T135 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3486971811 May 07 04:24:34 PM PDT 24 May 07 04:32:41 PM PDT 24 9678236100 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_dpi.702432525 May 07 04:22:44 PM PDT 24 May 07 05:08:30 PM PDT 24 12627463338 ps
T752 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.371076407 May 07 04:57:09 PM PDT 24 May 07 05:04:10 PM PDT 24 3645561760 ps
T197 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.746988195 May 07 04:34:11 PM PDT 24 May 07 05:32:26 PM PDT 24 15490744904 ps
T964 /workspace/coverage/default/0.chip_sw_example_rom.2924858325 May 07 04:22:45 PM PDT 24 May 07 04:24:42 PM PDT 24 3045710812 ps
T965 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.259237702 May 07 04:42:48 PM PDT 24 May 07 04:48:15 PM PDT 24 4557311400 ps
T966 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2938163892 May 07 04:34:56 PM PDT 24 May 07 04:45:06 PM PDT 24 4580660200 ps
T349 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3450158097 May 07 04:25:07 PM PDT 24 May 07 04:39:36 PM PDT 24 6956236004 ps
T967 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.705926403 May 07 04:45:45 PM PDT 24 May 07 04:56:22 PM PDT 24 4317001640 ps
T307 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3848886679 May 07 04:31:16 PM PDT 24 May 07 04:43:57 PM PDT 24 4989624538 ps
T796 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1156141231 May 07 04:49:09 PM PDT 24 May 07 04:56:07 PM PDT 24 3219524180 ps
T25 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2735520595 May 07 04:38:20 PM PDT 24 May 07 04:43:36 PM PDT 24 2594137748 ps
T968 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1412982872 May 07 04:37:37 PM PDT 24 May 07 04:47:31 PM PDT 24 4616946858 ps
T765 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736842789 May 07 04:52:52 PM PDT 24 May 07 04:58:29 PM PDT 24 3439980532 ps
T969 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1821711559 May 07 04:50:37 PM PDT 24 May 07 04:57:42 PM PDT 24 6673355680 ps
T136 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1341537333 May 07 04:41:04 PM PDT 24 May 07 04:48:20 PM PDT 24 7792497700 ps
T970 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1406878272 May 07 04:23:19 PM PDT 24 May 07 04:34:15 PM PDT 24 4305473500 ps
T108 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.350484829 May 07 04:27:30 PM PDT 24 May 07 05:47:29 PM PDT 24 24881881543 ps
T204 /workspace/coverage/default/1.chip_sw_flash_init.2464003421 May 07 04:33:35 PM PDT 24 May 07 05:08:05 PM PDT 24 26099663960 ps
T971 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4210338092 May 07 04:34:16 PM PDT 24 May 07 05:40:52 PM PDT 24 17696374850 ps
T972 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2257448989 May 07 04:44:31 PM PDT 24 May 07 04:47:17 PM PDT 24 2125459816 ps
T731 /workspace/coverage/default/33.chip_sw_all_escalation_resets.4159202078 May 07 04:52:28 PM PDT 24 May 07 04:59:58 PM PDT 24 4228417288 ps
T973 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1961362755 May 07 04:29:17 PM PDT 24 May 07 04:39:40 PM PDT 24 5399217790 ps
T974 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3783923991 May 07 04:31:35 PM PDT 24 May 07 04:45:14 PM PDT 24 7650235162 ps
T768 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3718974016 May 07 04:54:55 PM PDT 24 May 07 05:03:14 PM PDT 24 4700532400 ps
T782 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2694472515 May 07 04:53:42 PM PDT 24 May 07 05:02:36 PM PDT 24 3942110910 ps
T975 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.390080887 May 07 04:53:22 PM PDT 24 May 07 05:02:33 PM PDT 24 3859895572 ps
T188 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1271527345 May 07 04:30:42 PM PDT 24 May 07 07:47:49 PM PDT 24 64916015293 ps
T976 /workspace/coverage/default/1.chip_sw_kmac_smoketest.4040625691 May 07 04:40:02 PM PDT 24 May 07 04:45:10 PM PDT 24 3218452590 ps
T977 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2906413149 May 07 04:27:33 PM PDT 24 May 07 04:31:26 PM PDT 24 2682155806 ps
T332 /workspace/coverage/default/40.chip_sw_all_escalation_resets.3486145087 May 07 04:56:50 PM PDT 24 May 07 05:09:15 PM PDT 24 5100093184 ps
T308 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.494606952 May 07 04:24:24 PM PDT 24 May 07 04:38:37 PM PDT 24 5026309060 ps
T125 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.604832056 May 07 04:26:50 PM PDT 24 May 07 04:41:43 PM PDT 24 6570391496 ps
T978 /workspace/coverage/default/1.chip_sw_otbn_randomness.3406151060 May 07 04:33:57 PM PDT 24 May 07 04:51:08 PM PDT 24 5888537590 ps
T727 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3205682001 May 07 04:56:17 PM PDT 24 May 07 05:05:42 PM PDT 24 6118193320 ps
T979 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2917251017 May 07 04:40:56 PM PDT 24 May 07 04:52:29 PM PDT 24 7031657976 ps
T980 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.189443886 May 07 04:35:23 PM PDT 24 May 07 04:45:50 PM PDT 24 5068171850 ps
T304 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1515669518 May 07 04:34:31 PM PDT 24 May 07 04:55:19 PM PDT 24 5367879884 ps
T813 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2834850607 May 07 04:56:54 PM PDT 24 May 07 05:04:42 PM PDT 24 3550514268 ps
T981 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1485485636 May 07 04:32:48 PM PDT 24 May 07 04:36:26 PM PDT 24 3278633580 ps
T789 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1752736133 May 07 04:56:50 PM PDT 24 May 07 05:03:54 PM PDT 24 5487088410 ps
T709 /workspace/coverage/default/22.chip_sw_all_escalation_resets.43533404 May 07 04:51:29 PM PDT 24 May 07 05:00:58 PM PDT 24 5365551112 ps
T982 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2366351343 May 07 04:24:50 PM PDT 24 May 07 04:45:54 PM PDT 24 14653412819 ps
T983 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.73461838 May 07 04:39:33 PM PDT 24 May 07 04:51:00 PM PDT 24 4491117082 ps
T984 /workspace/coverage/default/4.chip_tap_straps_rma.2097108915 May 07 04:49:26 PM PDT 24 May 07 04:54:40 PM PDT 24 4252589062 ps
T228 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1875505066 May 07 04:26:37 PM PDT 24 May 07 04:30:36 PM PDT 24 2569951640 ps
T763 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.287238359 May 07 04:57:04 PM PDT 24 May 07 05:03:15 PM PDT 24 4020786690 ps
T985 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1816327903 May 07 04:51:22 PM PDT 24 May 07 05:02:55 PM PDT 24 4891985608 ps
T299 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3394078294 May 07 04:45:31 PM PDT 24 May 07 04:56:57 PM PDT 24 5001358846 ps
T734 /workspace/coverage/default/47.chip_sw_all_escalation_resets.2015356088 May 07 04:54:34 PM PDT 24 May 07 05:05:52 PM PDT 24 6204092696 ps
T986 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.499913546 May 07 04:40:53 PM PDT 24 May 07 05:33:44 PM PDT 24 40379245512 ps
T263 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.890878897 May 07 04:24:12 PM PDT 24 May 07 04:31:57 PM PDT 24 3460065600 ps
T987 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.326255004 May 07 04:41:46 PM PDT 24 May 07 04:48:50 PM PDT 24 5821899262 ps
T205 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2515541029 May 07 04:22:59 PM PDT 24 May 07 05:41:30 PM PDT 24 51079532550 ps
T206 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2086918150 May 07 04:41:27 PM PDT 24 May 07 06:03:50 PM PDT 24 47916791895 ps
T295 /workspace/coverage/default/1.chip_plic_all_irqs_20.1932495556 May 07 04:35:28 PM PDT 24 May 07 04:48:48 PM PDT 24 4414476496 ps
T988 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3007738264 May 07 04:35:33 PM PDT 24 May 07 05:35:11 PM PDT 24 18525933733 ps
T740 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1110055656 May 07 04:52:04 PM PDT 24 May 07 05:00:37 PM PDT 24 5653913108 ps
T174 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4149842176 May 07 04:30:55 PM PDT 24 May 07 04:35:35 PM PDT 24 3122178196 ps
T363 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3148549099 May 07 04:29:40 PM PDT 24 May 07 04:50:04 PM PDT 24 8210218040 ps
T364 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2162081432 May 07 04:26:06 PM PDT 24 May 07 04:29:16 PM PDT 24 2569605094 ps
T365 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3655316813 May 07 04:49:33 PM PDT 24 May 07 05:13:14 PM PDT 24 8209931544 ps
T366 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3186793273 May 07 04:39:37 PM PDT 24 May 07 04:43:30 PM PDT 24 2811397584 ps
T367 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3709843851 May 07 04:32:10 PM PDT 24 May 07 05:02:38 PM PDT 24 25042390880 ps
T368 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1912218727 May 07 04:32:23 PM PDT 24 May 07 04:50:08 PM PDT 24 5039997312 ps
T369 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2273158929 May 07 04:50:52 PM PDT 24 May 07 05:00:45 PM PDT 24 5348349964 ps
T351 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1878350921 May 07 04:36:20 PM PDT 24 May 07 04:38:53 PM PDT 24 2010635000 ps
T370 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1815308463 May 07 04:49:42 PM PDT 24 May 07 04:59:48 PM PDT 24 5345670500 ps
T735 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.105563442 May 07 04:54:20 PM PDT 24 May 07 05:00:22 PM PDT 24 3251174940 ps
T989 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1972971283 May 07 04:32:06 PM PDT 24 May 07 04:50:27 PM PDT 24 5744466394 ps
T990 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3687257643 May 07 04:34:56 PM PDT 24 May 07 04:47:08 PM PDT 24 4636201500 ps
T26 /workspace/coverage/default/0.chip_sw_gpio.3740348192 May 07 04:24:48 PM PDT 24 May 07 04:33:37 PM PDT 24 4392714060 ps
T106 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3576552153 May 07 04:36:36 PM PDT 24 May 07 05:26:48 PM PDT 24 20775016914 ps
T300 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3713286575 May 07 04:27:44 PM PDT 24 May 07 04:39:00 PM PDT 24 4175132280 ps
T991 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2737161332 May 07 04:24:46 PM PDT 24 May 07 04:43:20 PM PDT 24 5564232180 ps
T764 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303520074 May 07 04:54:29 PM PDT 24 May 07 04:59:49 PM PDT 24 3209574960 ps
T992 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2355134513 May 07 04:43:58 PM PDT 24 May 07 04:53:30 PM PDT 24 4121633306 ps
T993 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.324697567 May 07 04:44:07 PM PDT 24 May 07 05:34:58 PM PDT 24 18363717451 ps
T994 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3749943247 May 07 04:43:24 PM PDT 24 May 07 04:56:52 PM PDT 24 6928810360 ps
T56 /workspace/coverage/default/0.chip_sw_alert_test.1794307188 May 07 04:30:09 PM PDT 24 May 07 04:36:22 PM PDT 24 3566143898 ps
T995 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3379104677 May 07 04:36:10 PM PDT 24 May 07 04:39:28 PM PDT 24 2247626625 ps
T996 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1382662183 May 07 04:47:53 PM PDT 24 May 07 04:53:41 PM PDT 24 3130898060 ps
T337 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2572884444 May 07 04:26:30 PM PDT 24 May 07 04:30:54 PM PDT 24 3496694574 ps
T997 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3112098484 May 07 04:41:41 PM PDT 24 May 07 04:47:26 PM PDT 24 2953341764 ps
T998 /workspace/coverage/default/0.chip_sw_kmac_entropy.292878900 May 07 04:23:53 PM PDT 24 May 07 04:27:16 PM PDT 24 2572327040 ps
T773 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.251076235 May 07 04:48:57 PM PDT 24 May 07 04:56:03 PM PDT 24 3921165168 ps
T708 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3712052295 May 07 04:41:54 PM PDT 24 May 07 05:25:52 PM PDT 24 21175842256 ps
T343 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1112024643 May 07 04:27:03 PM PDT 24 May 07 04:32:53 PM PDT 24 6093693116 ps
T126 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2352060340 May 07 04:44:06 PM PDT 24 May 07 04:59:28 PM PDT 24 8490554052 ps
T999 /workspace/coverage/default/2.chip_sw_aes_smoketest.2651644945 May 07 04:46:41 PM PDT 24 May 07 04:50:39 PM PDT 24 2505376320 ps
T1000 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1824326940 May 07 04:25:55 PM PDT 24 May 07 04:31:59 PM PDT 24 2619177966 ps
T305 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2953069418 May 07 04:43:19 PM PDT 24 May 07 05:04:38 PM PDT 24 8250724040 ps
T1001 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.411644771 May 07 04:24:24 PM PDT 24 May 07 04:35:39 PM PDT 24 6406893240 ps
T1002 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3676242266 May 07 04:24:37 PM PDT 24 May 07 04:36:38 PM PDT 24 9010216928 ps
T1003 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2621979351 May 07 04:39:16 PM PDT 24 May 07 05:15:37 PM PDT 24 10839895386 ps
T663 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4154328297 May 07 04:35:48 PM PDT 24 May 07 05:36:51 PM PDT 24 24178796127 ps
T284 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942119282 May 07 04:54:20 PM PDT 24 May 07 04:59:17 PM PDT 24 3463669534 ps
T757 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.910395558 May 07 04:52:18 PM PDT 24 May 07 04:58:25 PM PDT 24 3500029032 ps
T1004 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3928505921 May 07 04:27:24 PM PDT 24 May 07 04:34:23 PM PDT 24 3557357850 ps
T710 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568675851 May 07 04:53:31 PM PDT 24 May 07 04:59:42 PM PDT 24 4110763950 ps
T746 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2895492021 May 07 04:56:16 PM PDT 24 May 07 05:00:53 PM PDT 24 3708548738 ps
T1005 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3849456165 May 07 04:44:39 PM PDT 24 May 07 05:18:50 PM PDT 24 19482898484 ps
T719 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3354354417 May 07 04:51:34 PM PDT 24 May 07 04:56:30 PM PDT 24 4063273250 ps
T1006 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3804683430 May 07 04:39:01 PM PDT 24 May 07 04:42:52 PM PDT 24 2315574820 ps
T674 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1961008679 May 07 04:27:08 PM PDT 24 May 07 04:35:19 PM PDT 24 5636989677 ps
T177 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2487361765 May 07 04:27:09 PM PDT 24 May 07 04:35:57 PM PDT 24 4383029808 ps
T207 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2715148646 May 07 04:23:34 PM PDT 24 May 07 05:48:10 PM PDT 24 49455133143 ps
T314 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2461180712 May 07 04:34:16 PM PDT 24 May 07 04:49:36 PM PDT 24 4870996610 ps
T1007 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4004913329 May 07 04:27:05 PM PDT 24 May 07 04:31:27 PM PDT 24 3051499560 ps
T264 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3140719465 May 07 04:32:54 PM PDT 24 May 07 04:42:30 PM PDT 24 3665341496 ps
T192 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1016030262 May 07 04:23:15 PM PDT 24 May 07 04:31:15 PM PDT 24 4905300217 ps
T721 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068988628 May 07 04:54:43 PM PDT 24 May 07 05:01:51 PM PDT 24 3342487400 ps
T318 /workspace/coverage/default/2.chip_sw_pattgen_ios.4219284181 May 07 04:38:48 PM PDT 24 May 07 04:43:02 PM PDT 24 2388001642 ps
T775 /workspace/coverage/default/31.chip_sw_all_escalation_resets.978953616 May 07 04:51:46 PM PDT 24 May 07 05:00:56 PM PDT 24 5840199520 ps
T1008 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3542522568 May 07 04:48:06 PM PDT 24 May 07 05:16:06 PM PDT 24 8154890588 ps
T1009 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1191064751 May 07 04:26:09 PM PDT 24 May 07 04:33:58 PM PDT 24 6328544076 ps
T724 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3971863040 May 07 04:56:38 PM PDT 24 May 07 05:03:58 PM PDT 24 4765792466 ps
T1010 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1364915520 May 07 04:29:24 PM PDT 24 May 07 04:57:56 PM PDT 24 9326850592 ps
T1011 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.229622181 May 07 04:44:46 PM PDT 24 May 07 04:48:29 PM PDT 24 2773727217 ps
T1012 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3313677036 May 07 04:40:07 PM PDT 24 May 07 05:54:19 PM PDT 24 44471645795 ps
T736 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3636984014 May 07 04:43:12 PM PDT 24 May 07 04:53:00 PM PDT 24 4663982560 ps
T728 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3755887075 May 07 04:56:33 PM PDT 24 May 07 05:04:18 PM PDT 24 5684988196 ps
T1013 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1756198333 May 07 04:43:46 PM PDT 24 May 07 04:52:26 PM PDT 24 4339790246 ps
T1014 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4264194949 May 07 04:24:18 PM PDT 24 May 07 04:33:48 PM PDT 24 4248196560 ps
T1015 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1866871526 May 07 04:31:00 PM PDT 24 May 07 04:43:51 PM PDT 24 7008838761 ps
T352 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.838392992 May 07 04:45:54 PM PDT 24 May 07 04:51:33 PM PDT 24 2691813776 ps
T251 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2369397054 May 07 04:44:13 PM PDT 24 May 07 04:52:56 PM PDT 24 9339784734 ps
T324 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2744269049 May 07 04:46:14 PM PDT 24 May 07 04:50:00 PM PDT 24 3105998236 ps
T1016 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3756094411 May 07 04:24:31 PM PDT 24 May 07 04:29:20 PM PDT 24 2976112260 ps
T1017 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2065040519 May 07 04:30:32 PM PDT 24 May 07 04:35:49 PM PDT 24 2624169632 ps
T49 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2550853882 May 07 04:30:53 PM PDT 24 May 07 04:38:53 PM PDT 24 3723935476 ps
T309 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2547462844 May 07 04:39:54 PM PDT 24 May 07 04:55:39 PM PDT 24 4911196572 ps
T1018 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1972229259 May 07 04:34:31 PM PDT 24 May 07 04:37:47 PM PDT 24 3286220920 ps
T799 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305316911 May 07 04:52:27 PM PDT 24 May 07 04:57:45 PM PDT 24 3096510600 ps
T1019 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2160233648 May 07 04:27:06 PM PDT 24 May 07 04:31:15 PM PDT 24 2269659915 ps
T1020 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3584415650 May 07 04:45:02 PM PDT 24 May 07 04:53:59 PM PDT 24 5443620192 ps
T98 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2173168923 May 07 04:34:40 PM PDT 24 May 07 05:04:11 PM PDT 24 22932559090 ps
T760 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.925500034 May 07 04:51:28 PM PDT 24 May 07 04:56:42 PM PDT 24 3684408760 ps
T1021 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3820973978 May 07 04:33:45 PM PDT 24 May 07 04:37:08 PM PDT 24 2573209076 ps
T1022 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1013042319 May 07 04:35:21 PM PDT 24 May 07 04:38:59 PM PDT 24 2795567043 ps
T1023 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.839516997 May 07 04:31:47 PM PDT 24 May 07 04:53:03 PM PDT 24 9367549926 ps
T1024 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2380574638 May 07 04:36:17 PM PDT 24 May 07 04:45:41 PM PDT 24 6033424403 ps
T1025 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.183374238 May 07 04:48:48 PM PDT 24 May 07 05:07:53 PM PDT 24 11245808773 ps
T723 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1305572112 May 07 04:53:14 PM PDT 24 May 07 05:01:17 PM PDT 24 4125612724 ps
T1026 /workspace/coverage/default/0.chip_sw_otbn_randomness.1928351998 May 07 04:26:38 PM PDT 24 May 07 04:41:36 PM PDT 24 5962664800 ps
T208 /workspace/coverage/default/2.chip_sw_flash_init.1029799719 May 07 04:39:15 PM PDT 24 May 07 05:11:46 PM PDT 24 23011651466 ps
T1027 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3771760983 May 07 04:44:45 PM PDT 24 May 07 04:53:54 PM PDT 24 4889864340 ps
T1028 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1678022624 May 07 04:45:32 PM PDT 24 May 07 04:55:23 PM PDT 24 5111496506 ps
T1029 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1540880006 May 07 04:25:46 PM PDT 24 May 07 04:30:44 PM PDT 24 2839724252 ps
T315 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2228808926 May 07 04:42:27 PM PDT 24 May 07 04:58:29 PM PDT 24 5457284270 ps
T214 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2756445503 May 07 04:24:32 PM PDT 24 May 07 04:33:48 PM PDT 24 6708012616 ps
T1030 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2509901223 May 07 04:36:04 PM PDT 24 May 07 04:48:08 PM PDT 24 4491434284 ps
T1031 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4242516712 May 07 04:24:43 PM PDT 24 May 07 04:35:21 PM PDT 24 5071871832 ps
T1032 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2324214955 May 07 04:39:19 PM PDT 24 May 07 04:46:03 PM PDT 24 4875881178 ps
T758 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012231088 May 07 04:50:09 PM PDT 24 May 07 04:55:51 PM PDT 24 4322040744 ps
T1033 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1192998516 May 07 04:46:51 PM PDT 24 May 07 04:50:09 PM PDT 24 2350510924 ps
T1034 /workspace/coverage/default/0.chip_sw_otbn_smoketest.201915367 May 07 04:29:49 PM PDT 24 May 07 05:01:37 PM PDT 24 8413976420 ps
T249 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2873358921 May 07 04:30:33 PM PDT 24 May 07 04:32:15 PM PDT 24 2746698582 ps
T1035 /workspace/coverage/default/2.chip_sw_aes_idle.2595776765 May 07 04:44:00 PM PDT 24 May 07 04:51:00 PM PDT 24 2903751840 ps
T693 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1305841061 May 07 04:28:19 PM PDT 24 May 07 04:33:00 PM PDT 24 3381531854 ps
T1036 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2926894331 May 07 04:44:21 PM PDT 24 May 07 05:06:15 PM PDT 24 12090928660 ps
T153 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.743124415 May 07 04:30:23 PM PDT 24 May 07 04:33:52 PM PDT 24 1982844679 ps
T808 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3436349636 May 07 04:52:54 PM PDT 24 May 07 04:59:43 PM PDT 24 4028102336 ps
T784 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3939847643 May 07 04:51:54 PM PDT 24 May 07 05:00:57 PM PDT 24 5618555764 ps
T1037 /workspace/coverage/default/0.chip_tap_straps_prod.4219007786 May 07 04:26:14 PM PDT 24 May 07 04:43:16 PM PDT 24 8110262755 ps
T316 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4048766617 May 07 04:31:06 PM PDT 24 May 07 04:43:04 PM PDT 24 3825987080 ps
T1038 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3222829059 May 07 04:33:41 PM PDT 24 May 07 05:02:15 PM PDT 24 8065040896 ps
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