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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.29 95.41 94.46 95.56 95.36 97.38 99.57


Total test records in report: 2771
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T750 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.232735943 May 07 04:55:09 PM PDT 24 May 07 05:00:12 PM PDT 24 3318213960 ps
T1188 /workspace/coverage/default/1.chip_sw_example_flash.160216838 May 07 04:33:03 PM PDT 24 May 07 04:38:06 PM PDT 24 2987193456 ps
T272 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3275942735 May 07 04:45:18 PM PDT 24 May 07 04:48:46 PM PDT 24 2147653404 ps
T64 /workspace/coverage/default/2.chip_tap_straps_testunlock0.827146713 May 07 04:45:09 PM PDT 24 May 07 04:48:16 PM PDT 24 3380065666 ps
T279 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3901890493 May 07 04:46:18 PM PDT 24 May 07 04:58:30 PM PDT 24 8600546412 ps
T1189 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.862756711 May 07 04:25:26 PM PDT 24 May 07 04:38:48 PM PDT 24 6626278180 ps
T57 /workspace/coverage/default/1.chip_sw_alert_test.4182902876 May 07 04:33:15 PM PDT 24 May 07 04:37:40 PM PDT 24 3061852312 ps
T1190 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.264819131 May 07 04:45:32 PM PDT 24 May 07 05:02:21 PM PDT 24 5273364680 ps
T1191 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2158887237 May 07 04:54:20 PM PDT 24 May 07 05:03:02 PM PDT 24 6265184528 ps
T1192 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2111669181 May 07 04:39:43 PM PDT 24 May 07 04:45:47 PM PDT 24 3099094092 ps
T1193 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2213387928 May 07 04:24:13 PM PDT 24 May 07 04:36:23 PM PDT 24 5123300950 ps
T751 /workspace/coverage/default/76.chip_sw_all_escalation_resets.246991169 May 07 04:56:01 PM PDT 24 May 07 05:05:12 PM PDT 24 5277708200 ps
T1194 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1463656267 May 07 04:49:50 PM PDT 24 May 07 04:58:06 PM PDT 24 4655703782 ps
T355 /workspace/coverage/default/81.chip_sw_all_escalation_resets.1757351820 May 07 04:55:44 PM PDT 24 May 07 05:05:05 PM PDT 24 4796389150 ps
T795 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1135032801 May 07 04:54:32 PM PDT 24 May 07 05:01:15 PM PDT 24 4329649938 ps
T1195 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.317190198 May 07 04:25:00 PM PDT 24 May 07 05:35:03 PM PDT 24 19037576243 ps
T1196 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2606313529 May 07 04:25:00 PM PDT 24 May 07 04:34:27 PM PDT 24 6692291219 ps
T120 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.576176889 May 07 04:45:41 PM PDT 24 May 07 04:54:54 PM PDT 24 5323223880 ps
T34 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.368525893 May 07 04:29:26 PM PDT 24 May 07 04:33:18 PM PDT 24 2923857352 ps
T1197 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3363124072 May 07 04:24:04 PM PDT 24 May 07 04:36:51 PM PDT 24 7037989743 ps
T767 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630443776 May 07 04:55:15 PM PDT 24 May 07 05:01:52 PM PDT 24 4153443524 ps
T239 /workspace/coverage/default/20.chip_sw_all_escalation_resets.982842248 May 07 04:50:19 PM PDT 24 May 07 04:57:53 PM PDT 24 5409693970 ps
T685 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1157403943 May 07 04:53:55 PM PDT 24 May 07 05:04:00 PM PDT 24 4264600516 ps
T1198 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.695255788 May 07 04:44:27 PM PDT 24 May 07 04:48:53 PM PDT 24 2596007925 ps
T1199 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3675209353 May 07 04:27:21 PM PDT 24 May 07 04:45:34 PM PDT 24 5856374200 ps
T1200 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2970235628 May 07 04:24:27 PM PDT 24 May 07 04:30:43 PM PDT 24 4270315240 ps
T1201 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2647104696 May 07 04:35:57 PM PDT 24 May 07 04:47:25 PM PDT 24 5225612160 ps
T1202 /workspace/coverage/default/1.chip_sw_edn_kat.2332432238 May 07 04:33:09 PM PDT 24 May 07 04:43:01 PM PDT 24 3361483652 ps
T1203 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3686818580 May 07 04:38:20 PM PDT 24 May 07 04:43:33 PM PDT 24 2999297860 ps
T753 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.663556878 May 07 04:54:08 PM PDT 24 May 07 05:00:09 PM PDT 24 3990749690 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2986931786 May 07 04:23:15 PM PDT 24 May 07 04:28:04 PM PDT 24 2660937920 ps
T754 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2781901597 May 07 04:54:10 PM PDT 24 May 07 05:02:11 PM PDT 24 5009506980 ps
T149 /workspace/coverage/default/0.chip_plic_all_irqs_10.2684608333 May 07 04:27:40 PM PDT 24 May 07 04:36:39 PM PDT 24 3499805400 ps
T1204 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3036059318 May 07 04:29:51 PM PDT 24 May 07 04:33:23 PM PDT 24 2862479224 ps
T1205 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2944154541 May 07 04:30:27 PM PDT 24 May 07 04:36:55 PM PDT 24 4688584788 ps
T319 /workspace/coverage/default/1.chip_sw_pattgen_ios.2195620628 May 07 04:30:03 PM PDT 24 May 07 04:34:37 PM PDT 24 3240579578 ps
T131 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2885467198 May 07 04:47:18 PM PDT 24 May 07 05:13:22 PM PDT 24 15929647742 ps
T286 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2295703267 May 07 04:54:58 PM PDT 24 May 07 05:04:06 PM PDT 24 4569165520 ps
T1206 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.263528791 May 07 04:24:51 PM PDT 24 May 07 04:41:24 PM PDT 24 7524049308 ps
T353 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2370690775 May 07 04:31:10 PM PDT 24 May 07 04:34:49 PM PDT 24 2255625510 ps
T679 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1644110010 May 07 04:41:40 PM PDT 24 May 07 04:43:33 PM PDT 24 2337643869 ps
T121 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3071028528 May 07 04:46:49 PM PDT 24 May 07 04:57:50 PM PDT 24 6861229564 ps
T1207 /workspace/coverage/default/1.chip_sw_uart_tx_rx.36035738 May 07 04:29:12 PM PDT 24 May 07 04:38:46 PM PDT 24 4338671134 ps
T1208 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2174829114 May 07 04:48:48 PM PDT 24 May 07 04:57:40 PM PDT 24 4110885616 ps
T1209 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.268757451 May 07 04:32:48 PM PDT 24 May 07 05:03:23 PM PDT 24 16606733918 ps
T1210 /workspace/coverage/default/1.rom_keymgr_functest.3666021236 May 07 04:38:21 PM PDT 24 May 07 04:45:21 PM PDT 24 3732130234 ps
T1211 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.903613057 May 07 04:33:33 PM PDT 24 May 07 04:49:13 PM PDT 24 5831266581 ps
T1212 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3864529525 May 07 04:53:39 PM PDT 24 May 07 04:59:56 PM PDT 24 3890215634 ps
T502 /workspace/coverage/default/2.chip_jtag_csr_rw.2677787259 May 07 04:37:44 PM PDT 24 May 07 04:56:44 PM PDT 24 10938159160 ps
T1213 /workspace/coverage/default/3.chip_tap_straps_dev.2627616844 May 07 04:48:16 PM PDT 24 May 07 04:51:39 PM PDT 24 3563718108 ps
T1214 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.311820686 May 07 04:35:05 PM PDT 24 May 07 04:38:31 PM PDT 24 2336377599 ps
T58 /workspace/coverage/default/2.chip_sw_alert_test.3357284546 May 07 04:42:51 PM PDT 24 May 07 04:47:00 PM PDT 24 3204276408 ps
T1215 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1589647136 May 07 04:51:13 PM PDT 24 May 07 04:56:48 PM PDT 24 3596439544 ps
T122 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3050907368 May 07 04:33:58 PM PDT 24 May 07 04:41:59 PM PDT 24 4906248640 ps
T1216 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2755237435 May 07 04:25:04 PM PDT 24 May 07 04:39:25 PM PDT 24 6022968238 ps
T1217 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3562068614 May 07 04:29:28 PM PDT 24 May 07 04:37:46 PM PDT 24 3258541104 ps
T1218 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4083050117 May 07 04:37:35 PM PDT 24 May 07 04:46:11 PM PDT 24 4341064478 ps
T1219 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1201983310 May 07 04:31:30 PM PDT 24 May 07 04:41:44 PM PDT 24 4373981278 ps
T389 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3459949741 May 07 04:26:12 PM PDT 24 May 07 04:56:18 PM PDT 24 17782202578 ps
T145 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3659513253 May 07 04:39:43 PM PDT 24 May 07 07:29:20 PM PDT 24 58807326188 ps
T1220 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1754287960 May 07 04:39:12 PM PDT 24 May 07 04:42:35 PM PDT 24 3187565144 ps
T1221 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1987382561 May 07 04:42:32 PM PDT 24 May 07 04:52:53 PM PDT 24 5126859736 ps
T37 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.235993288 May 07 04:42:35 PM PDT 24 May 07 04:51:04 PM PDT 24 4549236776 ps
T1222 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3495244857 May 07 04:48:12 PM PDT 24 May 07 04:55:57 PM PDT 24 3923874387 ps
T1223 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.915661500 May 07 04:24:17 PM PDT 24 May 07 04:29:42 PM PDT 24 3421063864 ps
T303 /workspace/coverage/default/1.chip_plic_all_irqs_0.1668940397 May 07 04:34:28 PM PDT 24 May 07 04:57:17 PM PDT 24 5969176904 ps
T694 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2634056986 May 07 04:31:56 PM PDT 24 May 07 04:34:50 PM PDT 24 2756515460 ps
T780 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2961009448 May 07 04:50:54 PM PDT 24 May 07 05:00:32 PM PDT 24 5327283240 ps
T50 /workspace/coverage/default/0.chip_jtag_csr_rw.373361550 May 07 04:18:15 PM PDT 24 May 07 04:59:05 PM PDT 24 22026199415 ps
T1224 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2408120880 May 07 04:29:37 PM PDT 24 May 07 04:40:01 PM PDT 24 3666472312 ps
T1225 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3068563273 May 07 04:45:01 PM PDT 24 May 07 04:51:48 PM PDT 24 5779252344 ps
T1226 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.752197261 May 07 04:51:34 PM PDT 24 May 07 05:01:45 PM PDT 24 6928913398 ps
T1227 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1159820936 May 07 04:32:01 PM PDT 24 May 07 04:42:09 PM PDT 24 6395832436 ps
T1228 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3839940450 May 07 04:43:07 PM PDT 24 May 07 05:57:40 PM PDT 24 23776813312 ps
T1229 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1174897246 May 07 04:25:29 PM PDT 24 May 07 05:05:45 PM PDT 24 23226064380 ps
T306 /workspace/coverage/default/0.chip_plic_all_irqs_20.2548627288 May 07 04:25:12 PM PDT 24 May 07 04:36:28 PM PDT 24 5017645360 ps
T1230 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.185028600 May 07 04:34:18 PM PDT 24 May 07 04:41:28 PM PDT 24 4499775928 ps
T1231 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1447385247 May 07 04:38:26 PM PDT 24 May 07 04:42:49 PM PDT 24 2892932352 ps
T1232 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.124284652 May 07 04:47:46 PM PDT 24 May 07 04:57:11 PM PDT 24 3602546110 ps
T1233 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3459853899 May 07 04:32:36 PM PDT 24 May 07 04:56:09 PM PDT 24 12104975720 ps
T1234 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4275602735 May 07 04:28:27 PM PDT 24 May 07 04:32:26 PM PDT 24 2674441154 ps
T1235 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.292653054 May 07 04:26:00 PM PDT 24 May 07 05:22:19 PM PDT 24 38926959228 ps
T1236 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3393804838 May 07 04:32:32 PM PDT 24 May 07 04:36:25 PM PDT 24 2421583186 ps
T1237 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2231891399 May 07 04:25:02 PM PDT 24 May 07 04:37:21 PM PDT 24 4162971672 ps
T1238 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1835547969 May 07 04:25:50 PM PDT 24 May 07 04:37:57 PM PDT 24 5517003280 ps
T1239 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1330577581 May 07 04:24:46 PM PDT 24 May 07 04:28:12 PM PDT 24 2652727312 ps
T714 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1631195288 May 07 04:54:39 PM PDT 24 May 07 05:01:49 PM PDT 24 5513977600 ps
T1240 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3498246824 May 07 04:44:12 PM PDT 24 May 07 05:04:33 PM PDT 24 6350867569 ps
T129 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3669056822 May 07 04:31:32 PM PDT 24 May 07 04:39:25 PM PDT 24 5205157114 ps
T393 /workspace/coverage/default/2.chip_jtag_mem_access.1081501077 May 07 04:37:29 PM PDT 24 May 07 05:02:43 PM PDT 24 13968772832 ps
T1241 /workspace/coverage/default/0.chip_sw_edn_kat.3772063615 May 07 04:24:46 PM PDT 24 May 07 04:35:55 PM PDT 24 3392914674 ps
T1242 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4162196987 May 07 04:40:18 PM PDT 24 May 07 04:58:17 PM PDT 24 5947350212 ps
T1243 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3942344886 May 07 04:31:40 PM PDT 24 May 07 04:38:16 PM PDT 24 4792007474 ps
T809 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3868513672 May 07 04:55:45 PM PDT 24 May 07 05:03:26 PM PDT 24 3279630280 ps
T1244 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.168119118 May 07 04:45:18 PM PDT 24 May 07 04:50:44 PM PDT 24 2886368435 ps
T786 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2532004798 May 07 04:51:21 PM PDT 24 May 07 05:01:18 PM PDT 24 6384338198 ps
T1245 /workspace/coverage/default/0.chip_sw_example_flash.1648736687 May 07 04:23:58 PM PDT 24 May 07 04:27:57 PM PDT 24 2817064100 ps
T1246 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2330125179 May 07 04:48:45 PM PDT 24 May 07 05:03:18 PM PDT 24 4252189400 ps
T51 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1755877612 May 07 04:26:01 PM PDT 24 May 07 04:30:53 PM PDT 24 3316855868 ps
T1247 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.564793365 May 07 04:40:14 PM PDT 24 May 07 04:45:29 PM PDT 24 2485638948 ps
T1248 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1390343347 May 07 04:40:25 PM PDT 24 May 07 04:49:25 PM PDT 24 3397017106 ps
T1249 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3471307584 May 07 04:26:03 PM PDT 24 May 07 04:32:20 PM PDT 24 4085987800 ps
T1250 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2079884885 May 07 04:49:02 PM PDT 24 May 07 04:55:27 PM PDT 24 3801431992 ps
T810 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3977862668 May 07 04:54:47 PM PDT 24 May 07 05:00:31 PM PDT 24 4010095496 ps
T1251 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1922543284 May 07 04:25:27 PM PDT 24 May 07 04:28:23 PM PDT 24 3030060558 ps
T749 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931389771 May 07 04:56:25 PM PDT 24 May 07 05:02:11 PM PDT 24 4333290736 ps
T159 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3040239347 May 07 04:25:37 PM PDT 24 May 07 04:34:51 PM PDT 24 4359752368 ps
T269 /workspace/coverage/default/5.chip_sw_all_escalation_resets.2372630487 May 07 04:48:16 PM PDT 24 May 07 05:00:37 PM PDT 24 5893509944 ps
T1252 /workspace/coverage/default/27.chip_sw_all_escalation_resets.906774835 May 07 04:51:49 PM PDT 24 May 07 05:03:40 PM PDT 24 5057739996 ps
T1253 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3879542478 May 07 04:32:12 PM PDT 24 May 07 04:46:37 PM PDT 24 6079184688 ps
T1254 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1710886897 May 07 04:38:37 PM PDT 24 May 07 04:49:59 PM PDT 24 4657257702 ps
T1255 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2186832553 May 07 04:33:48 PM PDT 24 May 07 04:45:42 PM PDT 24 7652135290 ps
T787 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2020219261 May 07 04:55:10 PM PDT 24 May 07 05:02:39 PM PDT 24 5654233380 ps
T762 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1502083044 May 07 04:51:58 PM PDT 24 May 07 04:57:57 PM PDT 24 3578514860 ps
T705 /workspace/coverage/default/0.chip_sw_pattgen_ios.492015450 May 07 04:23:51 PM PDT 24 May 07 04:29:11 PM PDT 24 2896002748 ps
T43 /workspace/coverage/default/2.rom_e2e_smoke.2567031575 May 07 04:52:29 PM PDT 24 May 07 05:52:39 PM PDT 24 17943775848 ps
T356 /workspace/coverage/default/72.chip_sw_all_escalation_resets.453394061 May 07 04:56:03 PM PDT 24 May 07 05:03:58 PM PDT 24 4778673144 ps
T1256 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2604001644 May 07 04:50:15 PM PDT 24 May 07 05:13:23 PM PDT 24 8181068580 ps
T1257 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3389634772 May 07 04:33:03 PM PDT 24 May 07 04:38:25 PM PDT 24 3206033391 ps
T1258 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3453582095 May 07 04:51:52 PM PDT 24 May 07 05:02:16 PM PDT 24 5447680652 ps
T40 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2343249093 May 07 04:39:58 PM PDT 24 May 07 04:46:47 PM PDT 24 3297472368 ps
T71 /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2419749820 May 07 04:07:03 PM PDT 24 May 07 04:07:41 PM PDT 24 465757702 ps
T72 /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.926172084 May 07 04:11:22 PM PDT 24 May 07 04:11:30 PM PDT 24 53336087 ps
T73 /workspace/coverage/cover_reg_top/51.xbar_random.1258392559 May 07 04:07:04 PM PDT 24 May 07 04:07:21 PM PDT 24 147112201 ps
T146 /workspace/coverage/cover_reg_top/55.xbar_stress_all.2359219815 May 07 04:07:48 PM PDT 24 May 07 04:12:21 PM PDT 24 7166186938 ps
T222 /workspace/coverage/cover_reg_top/22.xbar_stress_all.2405731347 May 07 04:00:27 PM PDT 24 May 07 04:03:32 PM PDT 24 5031895554 ps
T223 /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2418387084 May 07 04:03:06 PM PDT 24 May 07 04:04:21 PM PDT 24 4107903978 ps
T224 /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3251058183 May 07 04:04:21 PM PDT 24 May 07 04:04:28 PM PDT 24 41677141 ps
T225 /workspace/coverage/cover_reg_top/35.xbar_error_random.2171398739 May 07 04:04:18 PM PDT 24 May 07 04:04:25 PM PDT 24 36598708 ps
T429 /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.900734023 May 07 03:55:46 PM PDT 24 May 07 03:56:28 PM PDT 24 465150163 ps
T510 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.57142804 May 07 04:11:32 PM PDT 24 May 07 04:16:13 PM PDT 24 1844517783 ps
T512 /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3537472863 May 07 04:09:18 PM PDT 24 May 07 04:09:26 PM PDT 24 52541008 ps
T226 /workspace/coverage/cover_reg_top/37.xbar_random.2691553956 May 07 04:04:26 PM PDT 24 May 07 04:05:11 PM PDT 24 1358030125 ps
T438 /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1795809173 May 07 04:09:53 PM PDT 24 May 07 04:10:11 PM PDT 24 364870189 ps
T499 /workspace/coverage/cover_reg_top/50.xbar_random.4004378763 May 07 04:06:54 PM PDT 24 May 07 04:07:33 PM PDT 24 1027010277 ps
T504 /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3231591918 May 07 04:12:40 PM PDT 24 May 07 04:20:29 PM PDT 24 25324110014 ps
T138 /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3519406592 May 07 03:50:45 PM PDT 24 May 07 05:32:22 PM PDT 24 38891779680 ps
T399 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2208090332 May 07 03:58:41 PM PDT 24 May 07 04:00:34 PM PDT 24 746069818 ps
T400 /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3048576470 May 07 04:14:24 PM PDT 24 May 07 04:14:39 PM PDT 24 322836126 ps
T514 /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3874963185 May 07 04:03:18 PM PDT 24 May 07 04:04:31 PM PDT 24 1786139668 ps
T506 /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2835066289 May 07 04:15:01 PM PDT 24 May 07 04:15:42 PM PDT 24 477509904 ps
T508 /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.412860210 May 07 04:14:45 PM PDT 24 May 07 04:15:12 PM PDT 24 618793350 ps
T513 /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1677451490 May 07 03:54:08 PM PDT 24 May 07 03:55:29 PM PDT 24 4693414834 ps
T472 /workspace/coverage/cover_reg_top/23.xbar_same_source.3248952386 May 07 04:00:34 PM PDT 24 May 07 04:01:34 PM PDT 24 2097363637 ps
T511 /workspace/coverage/cover_reg_top/11.xbar_random.4045366799 May 07 03:56:35 PM PDT 24 May 07 03:57:34 PM PDT 24 611244504 ps
T466 /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.989772417 May 07 04:11:28 PM PDT 24 May 07 04:27:13 PM PDT 24 80956349294 ps
T507 /workspace/coverage/cover_reg_top/74.xbar_smoke.2791890112 May 07 04:11:07 PM PDT 24 May 07 04:11:15 PM PDT 24 52585121 ps
T505 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3429276548 May 07 04:13:23 PM PDT 24 May 07 04:18:50 PM PDT 24 9320537433 ps
T437 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.594459368 May 07 04:07:44 PM PDT 24 May 07 04:16:25 PM PDT 24 8854984226 ps
T605 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.711076698 May 07 04:15:13 PM PDT 24 May 07 04:17:06 PM PDT 24 233987299 ps
T139 /workspace/coverage/cover_reg_top/11.chip_csr_rw.4031881752 May 07 03:56:50 PM PDT 24 May 07 04:01:25 PM PDT 24 4231965484 ps
T1259 /workspace/coverage/cover_reg_top/22.xbar_smoke.911115421 May 07 04:00:13 PM PDT 24 May 07 04:00:21 PM PDT 24 51225693 ps
T406 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.138680205 May 07 04:13:16 PM PDT 24 May 07 04:23:32 PM PDT 24 4426394481 ps
T670 /workspace/coverage/cover_reg_top/37.xbar_error_random.3057322011 May 07 04:04:33 PM PDT 24 May 07 04:05:23 PM PDT 24 584017097 ps
T509 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3677703853 May 07 04:10:05 PM PDT 24 May 07 04:15:50 PM PDT 24 10868897538 ps
T615 /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1304116749 May 07 03:53:56 PM PDT 24 May 07 03:54:04 PM PDT 24 55230950 ps
T408 /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1313802421 May 07 03:51:29 PM PDT 24 May 07 03:52:25 PM PDT 24 1577867372 ps
T815 /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3686973167 May 07 03:57:16 PM PDT 24 May 07 03:58:18 PM PDT 24 712726768 ps
T473 /workspace/coverage/cover_reg_top/58.xbar_random.2913699592 May 07 04:08:14 PM PDT 24 May 07 04:09:37 PM PDT 24 2340922678 ps
T556 /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.4287302653 May 07 04:03:08 PM PDT 24 May 07 04:04:48 PM PDT 24 9184980650 ps
T422 /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.495346785 May 07 03:59:05 PM PDT 24 May 07 04:38:47 PM PDT 24 123941454380 ps
T450 /workspace/coverage/cover_reg_top/47.xbar_stress_all.1211162054 May 07 04:06:26 PM PDT 24 May 07 04:11:48 PM PDT 24 8469530993 ps
T447 /workspace/coverage/cover_reg_top/44.xbar_stress_all.2587056320 May 07 04:05:46 PM PDT 24 May 07 04:07:38 PM PDT 24 3488411210 ps
T140 /workspace/coverage/cover_reg_top/3.chip_csr_rw.453862975 May 07 03:54:02 PM PDT 24 May 07 04:03:13 PM PDT 24 6026342280 ps
T1260 /workspace/coverage/cover_reg_top/12.xbar_error_random.452511384 May 07 03:57:06 PM PDT 24 May 07 03:58:19 PM PDT 24 2059284877 ps
T468 /workspace/coverage/cover_reg_top/98.xbar_stress_all.3919823112 May 07 04:15:46 PM PDT 24 May 07 04:18:31 PM PDT 24 1900048128 ps
T414 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2613398733 May 07 04:10:45 PM PDT 24 May 07 04:16:12 PM PDT 24 3010104260 ps
T672 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2707753227 May 07 04:03:00 PM PDT 24 May 07 04:09:54 PM PDT 24 3524224655 ps
T819 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1924497672 May 07 04:09:26 PM PDT 24 May 07 04:11:48 PM PDT 24 3941891892 ps
T857 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3670716534 May 07 04:08:57 PM PDT 24 May 07 04:09:41 PM PDT 24 2611546964 ps
T522 /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.297502244 May 07 04:14:40 PM PDT 24 May 07 04:15:03 PM PDT 24 264490479 ps
T1261 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3022754132 May 07 04:08:50 PM PDT 24 May 07 04:10:10 PM PDT 24 2765094923 ps
T1262 /workspace/coverage/cover_reg_top/91.xbar_error_random.3600265182 May 07 04:14:24 PM PDT 24 May 07 04:15:05 PM PDT 24 1133878130 ps
T820 /workspace/coverage/cover_reg_top/0.xbar_access_same_device.3890776903 May 07 03:50:57 PM PDT 24 May 07 03:53:07 PM PDT 24 3251747514 ps
T141 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3922030334 May 07 03:56:30 PM PDT 24 May 07 04:21:25 PM PDT 24 14515964550 ps
T1263 /workspace/coverage/cover_reg_top/33.xbar_error_random.1965746420 May 07 04:03:23 PM PDT 24 May 07 04:03:58 PM PDT 24 1025689398 ps
T446 /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1876037073 May 07 04:07:22 PM PDT 24 May 07 04:08:03 PM PDT 24 483841839 ps
T608 /workspace/coverage/cover_reg_top/94.xbar_random.749010630 May 07 04:14:45 PM PDT 24 May 07 04:16:11 PM PDT 24 2309420336 ps
T482 /workspace/coverage/cover_reg_top/13.xbar_same_source.3502549656 May 07 03:57:16 PM PDT 24 May 07 03:57:31 PM PDT 24 178076804 ps
T637 /workspace/coverage/cover_reg_top/1.xbar_same_source.225535685 May 07 03:51:34 PM PDT 24 May 07 03:51:56 PM PDT 24 594434058 ps
T517 /workspace/coverage/cover_reg_top/28.chip_tl_errors.2910253758 May 07 04:03:01 PM PDT 24 May 07 04:05:42 PM PDT 24 2828636166 ps
T1264 /workspace/coverage/cover_reg_top/89.xbar_error_random.3406234891 May 07 04:14:05 PM PDT 24 May 07 04:14:29 PM PDT 24 266931303 ps
T634 /workspace/coverage/cover_reg_top/78.xbar_same_source.2596941928 May 07 04:11:54 PM PDT 24 May 07 04:12:25 PM PDT 24 1025506399 ps
T606 /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.170789422 May 07 04:06:02 PM PDT 24 May 07 04:14:44 PM PDT 24 11378465380 ps
T823 /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2516572636 May 07 03:56:41 PM PDT 24 May 07 04:22:21 PM PDT 24 86786112170 ps
T432 /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1485121401 May 07 04:09:08 PM PDT 24 May 07 04:37:04 PM PDT 24 98158076157 ps
T583 /workspace/coverage/cover_reg_top/16.xbar_same_source.4089921578 May 07 03:58:31 PM PDT 24 May 07 03:58:53 PM PDT 24 610944340 ps
T518 /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3366396299 May 07 04:12:27 PM PDT 24 May 07 04:20:17 PM PDT 24 26596374422 ps
T834 /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1396298723 May 07 03:58:31 PM PDT 24 May 07 04:26:23 PM PDT 24 91771152728 ps
T1265 /workspace/coverage/cover_reg_top/58.xbar_error_random.2570248734 May 07 04:08:14 PM PDT 24 May 07 04:08:31 PM PDT 24 172943204 ps
T1266 /workspace/coverage/cover_reg_top/38.xbar_error_random.1827950533 May 07 04:04:35 PM PDT 24 May 07 04:06:08 PM PDT 24 2390089665 ps
T848 /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.4154418853 May 07 03:53:55 PM PDT 24 May 07 03:57:58 PM PDT 24 13187712355 ps
T576 /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3414502976 May 07 04:08:06 PM PDT 24 May 07 04:08:19 PM PDT 24 207378270 ps
T571 /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1763950500 May 07 04:10:59 PM PDT 24 May 07 04:11:17 PM PDT 24 178374240 ps
T610 /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2219557225 May 07 04:04:35 PM PDT 24 May 07 04:06:07 PM PDT 24 5344763587 ps
T707 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3713009706 May 07 04:03:11 PM PDT 24 May 07 04:06:25 PM PDT 24 645926352 ps
T411 /workspace/coverage/cover_reg_top/35.xbar_stress_all.2983469312 May 07 04:04:17 PM PDT 24 May 07 04:12:09 PM PDT 24 12913115495 ps
T590 /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1594416964 May 07 04:03:01 PM PDT 24 May 07 04:10:11 PM PDT 24 41665143226 ps
T621 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1448436999 May 07 03:53:58 PM PDT 24 May 07 03:57:02 PM PDT 24 1099398238 ps
T591 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.258437116 May 07 04:09:26 PM PDT 24 May 07 04:12:14 PM PDT 24 2578935227 ps
T469 /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3066182384 May 07 04:08:34 PM PDT 24 May 07 04:09:02 PM PDT 24 288711025 ps
T1267 /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2063445999 May 07 04:03:47 PM PDT 24 May 07 04:04:34 PM PDT 24 4406001119 ps
T1268 /workspace/coverage/cover_reg_top/21.xbar_error_random.3403378251 May 07 04:00:05 PM PDT 24 May 07 04:00:52 PM PDT 24 1169917632 ps
T1269 /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3962613363 May 07 04:05:00 PM PDT 24 May 07 04:05:07 PM PDT 24 43846146 ps
T860 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.419491010 May 07 03:55:51 PM PDT 24 May 07 03:58:32 PM PDT 24 315598863 ps
T419 /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1551191115 May 07 04:06:54 PM PDT 24 May 07 04:15:35 PM PDT 24 29082345149 ps
T443 /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3873222843 May 07 04:04:42 PM PDT 24 May 07 04:04:50 PM PDT 24 48221195 ps
T625 /workspace/coverage/cover_reg_top/38.xbar_same_source.4247334594 May 07 04:04:44 PM PDT 24 May 07 04:05:38 PM PDT 24 1822498164 ps
T582 /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.45274400 May 07 04:13:46 PM PDT 24 May 07 04:15:23 PM PDT 24 5660234157 ps
T1270 /workspace/coverage/cover_reg_top/60.xbar_smoke.3850286976 May 07 04:08:25 PM PDT 24 May 07 04:08:34 PM PDT 24 198649204 ps
T612 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2261267796 May 07 04:05:28 PM PDT 24 May 07 04:08:55 PM PDT 24 670121391 ps
T420 /workspace/coverage/cover_reg_top/13.xbar_stress_all.966990047 May 07 03:57:26 PM PDT 24 May 07 04:01:11 PM PDT 24 6137735920 ps
T640 /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2604745536 May 07 03:59:58 PM PDT 24 May 07 04:00:57 PM PDT 24 3372898319 ps
T555 /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.4148320679 May 07 04:04:32 PM PDT 24 May 07 04:20:50 PM PDT 24 54890624133 ps
T1271 /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1929806833 May 07 04:13:07 PM PDT 24 May 07 04:14:32 PM PDT 24 5187671396 ps
T578 /workspace/coverage/cover_reg_top/77.xbar_random.1362740049 May 07 04:11:40 PM PDT 24 May 07 04:12:11 PM PDT 24 401348483 ps
T523 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.39895434 May 07 04:15:38 PM PDT 24 May 07 04:35:47 PM PDT 24 100504914076 ps
T835 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.967550207 May 07 04:11:53 PM PDT 24 May 07 04:18:02 PM PDT 24 20786460506 ps
T828 /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1021940602 May 07 04:12:19 PM PDT 24 May 07 04:13:11 PM PDT 24 761051471 ps
T377 /workspace/coverage/cover_reg_top/4.chip_csr_rw.1387618153 May 07 03:54:05 PM PDT 24 May 07 04:03:18 PM PDT 24 5075311525 ps
T559 /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2131914487 May 07 04:09:43 PM PDT 24 May 07 04:09:59 PM PDT 24 281093200 ps
T588 /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.267876946 May 07 04:07:06 PM PDT 24 May 07 04:07:35 PM PDT 24 559643943 ps
T1272 /workspace/coverage/cover_reg_top/95.xbar_error_random.336896311 May 07 04:15:01 PM PDT 24 May 07 04:15:29 PM PDT 24 939163818 ps
T1273 /workspace/coverage/cover_reg_top/28.xbar_error_random.3547530069 May 07 04:03:03 PM PDT 24 May 07 04:04:09 PM PDT 24 1830189062 ps
T622 /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.918805063 May 07 03:56:40 PM PDT 24 May 07 03:57:48 PM PDT 24 3978999157 ps
T587 /workspace/coverage/cover_reg_top/65.xbar_random.2376638856 May 07 04:09:34 PM PDT 24 May 07 04:10:03 PM PDT 24 793407381 ps
T1274 /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.109746238 May 07 04:07:03 PM PDT 24 May 07 04:13:50 PM PDT 24 37652636299 ps
T1275 /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1890867279 May 07 03:53:54 PM PDT 24 May 07 03:54:02 PM PDT 24 38056974 ps
T570 /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3215313464 May 07 04:14:38 PM PDT 24 May 07 04:22:58 PM PDT 24 46140554293 ps
T841 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.4110829138 May 07 04:12:32 PM PDT 24 May 07 04:14:48 PM PDT 24 521471775 ps
T1276 /workspace/coverage/cover_reg_top/51.xbar_error_random.1617783015 May 07 04:07:04 PM PDT 24 May 07 04:07:24 PM PDT 24 424949888 ps
T597 /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.571331722 May 07 04:08:55 PM PDT 24 May 07 04:15:54 PM PDT 24 23275378111 ps
T1277 /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3139567818 May 07 04:11:19 PM PDT 24 May 07 04:12:24 PM PDT 24 3581354115 ps
T636 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2423618791 May 07 04:13:51 PM PDT 24 May 07 04:18:06 PM PDT 24 776910716 ps
T673 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.876524302 May 07 04:08:32 PM PDT 24 May 07 04:15:47 PM PDT 24 12240073500 ps
T533 /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3116156800 May 07 03:55:52 PM PDT 24 May 07 03:56:02 PM PDT 24 74626851 ps
T845 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.4269688494 May 07 04:11:02 PM PDT 24 May 07 04:13:34 PM PDT 24 4238485690 ps
T1278 /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1859069963 May 07 03:54:15 PM PDT 24 May 07 03:54:22 PM PDT 24 41767854 ps
T1279 /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1102931720 May 07 04:01:11 PM PDT 24 May 07 04:01:36 PM PDT 24 554560541 ps
T630 /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.88769434 May 07 04:14:28 PM PDT 24 May 07 04:14:43 PM PDT 24 131821593 ps
T609 /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3884582683 May 07 04:14:50 PM PDT 24 May 07 04:15:15 PM PDT 24 299505256 ps
T415 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2840239957 May 07 04:10:32 PM PDT 24 May 07 04:10:47 PM PDT 24 158192178 ps
T1280 /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3919548978 May 07 04:12:21 PM PDT 24 May 07 04:13:39 PM PDT 24 7334500428 ps
T423 /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1916594066 May 07 04:15:28 PM PDT 24 May 07 04:25:48 PM PDT 24 33843586750 ps
T1281 /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3766801808 May 07 04:07:52 PM PDT 24 May 07 04:09:19 PM PDT 24 5060754001 ps
T1282 /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1825206314 May 07 03:53:53 PM PDT 24 May 07 03:54:04 PM PDT 24 70055553 ps
T519 /workspace/coverage/cover_reg_top/56.xbar_random.3666948485 May 07 04:07:54 PM PDT 24 May 07 04:08:14 PM PDT 24 446381185 ps
T643 /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3737008648 May 07 04:03:05 PM PDT 24 May 07 04:03:14 PM PDT 24 54562745 ps
T550 /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1859781834 May 07 04:04:27 PM PDT 24 May 07 04:05:01 PM PDT 24 388709625 ps
T455 /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3777064786 May 07 04:05:06 PM PDT 24 May 07 04:06:00 PM PDT 24 1332433478 ps
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