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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.29 95.41 94.46 95.56 95.36 97.38 99.57


Total test records in report: 2771
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T1039 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.370253174 May 07 04:43:59 PM PDT 24 May 07 04:55:35 PM PDT 24 5849651432 ps
T788 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2471476060 May 07 04:52:48 PM PDT 24 May 07 05:01:48 PM PDT 24 5456007080 ps
T250 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1319577936 May 07 04:24:05 PM PDT 24 May 07 04:25:56 PM PDT 24 2005416852 ps
T1040 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.192625737 May 07 04:49:24 PM PDT 24 May 07 04:58:57 PM PDT 24 4085102250 ps
T1041 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3635549993 May 07 04:32:10 PM PDT 24 May 07 04:43:36 PM PDT 24 9197595462 ps
T747 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1232428971 May 07 04:51:47 PM PDT 24 May 07 05:00:50 PM PDT 24 5248858220 ps
T323 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2918967256 May 07 04:25:15 PM PDT 24 May 07 04:35:11 PM PDT 24 4805146007 ps
T1042 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.76164944 May 07 04:45:23 PM PDT 24 May 07 04:55:37 PM PDT 24 6104235097 ps
T1043 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3636341886 May 07 04:42:22 PM PDT 24 May 07 04:48:23 PM PDT 24 4082712600 ps
T326 /workspace/coverage/default/1.chip_sival_flash_info_access.1646720035 May 07 04:33:55 PM PDT 24 May 07 04:39:05 PM PDT 24 2719850560 ps
T501 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1821199503 May 07 04:32:44 PM PDT 24 May 07 04:47:40 PM PDT 24 4648823620 ps
T1044 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1948034569 May 07 04:35:57 PM PDT 24 May 07 04:49:20 PM PDT 24 5826083330 ps
T706 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.243247442 May 07 04:28:33 PM PDT 24 May 07 04:57:26 PM PDT 24 21769325246 ps
T1045 /workspace/coverage/default/2.chip_sw_example_flash.1660359072 May 07 04:39:16 PM PDT 24 May 07 04:43:26 PM PDT 24 2642389224 ps
T144 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3957244231 May 07 04:24:13 PM PDT 24 May 07 07:16:58 PM PDT 24 57272690458 ps
T1046 /workspace/coverage/default/2.chip_sw_power_idle_load.1881088499 May 07 04:45:24 PM PDT 24 May 07 04:54:47 PM PDT 24 4371824328 ps
T317 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1286101752 May 07 04:24:48 PM PDT 24 May 07 04:33:42 PM PDT 24 3855706572 ps
T1047 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2436388483 May 07 04:40:31 PM PDT 24 May 07 04:53:51 PM PDT 24 5789790940 ps
T1048 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3972576741 May 07 04:23:29 PM PDT 24 May 07 04:27:40 PM PDT 24 2647289840 ps
T503 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3186424972 May 07 04:24:33 PM PDT 24 May 07 04:32:06 PM PDT 24 3762090308 ps
T1049 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3578003931 May 07 04:35:03 PM PDT 24 May 07 04:44:40 PM PDT 24 4924364408 ps
T333 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3203503235 May 07 04:23:45 PM PDT 24 May 07 04:30:39 PM PDT 24 18145855652 ps
T1050 /workspace/coverage/default/0.chip_sival_flash_info_access.1739063357 May 07 04:23:49 PM PDT 24 May 07 04:29:45 PM PDT 24 2924023230 ps
T107 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.153332877 May 07 04:27:50 PM PDT 24 May 07 04:58:36 PM PDT 24 10662585506 ps
T748 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3580638545 May 07 04:51:34 PM PDT 24 May 07 05:02:15 PM PDT 24 5988263338 ps
T793 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3595125344 May 07 04:56:52 PM PDT 24 May 07 05:02:36 PM PDT 24 3729945752 ps
T1051 /workspace/coverage/default/2.chip_sw_kmac_app_rom.889267813 May 07 04:42:33 PM PDT 24 May 07 04:46:12 PM PDT 24 2197521740 ps
T1052 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3975721877 May 07 04:30:05 PM PDT 24 May 07 05:03:49 PM PDT 24 8759753520 ps
T1053 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2041434968 May 07 04:30:44 PM PDT 24 May 07 04:45:21 PM PDT 24 5065076730 ps
T1054 /workspace/coverage/default/2.chip_sw_kmac_idle.3155986973 May 07 04:43:10 PM PDT 24 May 07 04:48:00 PM PDT 24 2876844184 ps
T755 /workspace/coverage/default/42.chip_sw_all_escalation_resets.4073147737 May 07 04:56:52 PM PDT 24 May 07 05:05:41 PM PDT 24 5073980744 ps
T1055 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2277437966 May 07 04:47:28 PM PDT 24 May 07 04:55:45 PM PDT 24 4749273240 ps
T1056 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3440688961 May 07 04:43:39 PM PDT 24 May 07 04:52:37 PM PDT 24 7617070870 ps
T1057 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1696927944 May 07 04:39:03 PM PDT 24 May 07 07:43:35 PM PDT 24 64057564295 ps
T285 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522329817 May 07 04:52:53 PM PDT 24 May 07 05:00:47 PM PDT 24 3736387088 ps
T215 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1982617561 May 07 04:35:34 PM PDT 24 May 07 04:46:07 PM PDT 24 6609399528 ps
T1058 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.586686917 May 07 04:40:40 PM PDT 24 May 07 05:06:16 PM PDT 24 16278028265 ps
T802 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4212677847 May 07 04:56:05 PM PDT 24 May 07 05:02:04 PM PDT 24 3511376872 ps
T76 /workspace/coverage/default/0.chip_jtag_mem_access.1765794915 May 07 04:18:19 PM PDT 24 May 07 04:40:12 PM PDT 24 13601120222 ps
T1059 /workspace/coverage/default/1.chip_sw_rv_timer_irq.4156251342 May 07 04:31:54 PM PDT 24 May 07 04:36:36 PM PDT 24 3370214034 ps
T1060 /workspace/coverage/default/2.chip_sw_otbn_smoketest.474532267 May 07 04:49:26 PM PDT 24 May 07 05:02:38 PM PDT 24 5526017662 ps
T1061 /workspace/coverage/default/1.chip_sw_example_concurrency.229730278 May 07 04:30:08 PM PDT 24 May 07 04:34:58 PM PDT 24 2479648400 ps
T1062 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1363868726 May 07 04:48:13 PM PDT 24 May 07 04:52:22 PM PDT 24 2657187030 ps
T1063 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.665084157 May 07 04:33:50 PM PDT 24 May 07 05:00:03 PM PDT 24 7216575278 ps
T380 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.779291412 May 07 04:27:21 PM PDT 24 May 07 04:34:14 PM PDT 24 2938568225 ps
T1064 /workspace/coverage/default/1.chip_sw_aes_masking_off.1957716169 May 07 04:32:57 PM PDT 24 May 07 04:36:43 PM PDT 24 2821544143 ps
T209 /workspace/coverage/default/0.chip_sw_flash_init.765792241 May 07 04:23:56 PM PDT 24 May 07 05:03:47 PM PDT 24 25005692311 ps
T797 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.955557949 May 07 04:50:52 PM PDT 24 May 07 04:56:24 PM PDT 24 3491536708 ps
T1065 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.772624117 May 07 04:41:36 PM PDT 24 May 07 04:50:26 PM PDT 24 5147151025 ps
T301 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3176557408 May 07 04:39:00 PM PDT 24 May 07 04:46:34 PM PDT 24 3821097850 ps
T1066 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1167405142 May 07 04:38:41 PM PDT 24 May 07 04:49:00 PM PDT 24 4023814210 ps
T296 /workspace/coverage/default/0.chip_plic_all_irqs_0.2701309509 May 07 04:28:31 PM PDT 24 May 07 04:48:03 PM PDT 24 5986652264 ps
T336 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1534659303 May 07 04:36:36 PM PDT 24 May 07 04:46:55 PM PDT 24 4729858295 ps
T1067 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1189605863 May 07 04:50:36 PM PDT 24 May 07 05:01:39 PM PDT 24 3689225016 ps
T1068 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4211112047 May 07 04:39:42 PM PDT 24 May 07 04:45:06 PM PDT 24 3124285804 ps
T1069 /workspace/coverage/default/2.chip_sw_aes_masking_off.3633575812 May 07 04:42:55 PM PDT 24 May 07 04:48:21 PM PDT 24 2966943364 ps
T1070 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2537985992 May 07 04:33:10 PM PDT 24 May 07 05:49:34 PM PDT 24 42784184648 ps
T1071 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2534646826 May 07 04:40:07 PM PDT 24 May 07 04:50:32 PM PDT 24 3943130352 ps
T1072 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3104793424 May 07 04:49:42 PM PDT 24 May 07 05:12:29 PM PDT 24 8121849220 ps
T1073 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1867659413 May 07 04:29:35 PM PDT 24 May 07 04:32:50 PM PDT 24 2637612560 ps
T1074 /workspace/coverage/default/1.chip_sw_aes_entropy.1995570455 May 07 04:34:16 PM PDT 24 May 07 04:38:42 PM PDT 24 2763827718 ps
T86 /workspace/coverage/default/7.chip_sw_all_escalation_resets.260493436 May 07 04:49:25 PM PDT 24 May 07 04:59:33 PM PDT 24 4169523080 ps
T88 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3357601186 May 07 04:56:20 PM PDT 24 May 07 05:03:10 PM PDT 24 5643424972 ps
T89 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2614926842 May 07 04:26:42 PM PDT 24 May 07 04:51:37 PM PDT 24 18199937164 ps
T90 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3042559382 May 07 04:44:52 PM PDT 24 May 07 04:52:24 PM PDT 24 3026478448 ps
T91 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3840208454 May 07 04:55:14 PM PDT 24 May 07 05:01:46 PM PDT 24 3718901012 ps
T92 /workspace/coverage/default/62.chip_sw_all_escalation_resets.172112668 May 07 04:54:07 PM PDT 24 May 07 05:03:01 PM PDT 24 5515113376 ps
T93 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.484727180 May 07 04:33:57 PM PDT 24 May 07 04:44:03 PM PDT 24 8465063059 ps
T94 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1871011621 May 07 04:30:08 PM PDT 24 May 07 04:41:39 PM PDT 24 4404032660 ps
T95 /workspace/coverage/default/2.chip_sw_kmac_entropy.2197452026 May 07 04:40:34 PM PDT 24 May 07 04:44:31 PM PDT 24 2591399010 ps
T96 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074080361 May 07 04:50:56 PM PDT 24 May 07 04:57:18 PM PDT 24 3847584008 ps
T1075 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1222776894 May 07 04:25:15 PM PDT 24 May 07 04:33:44 PM PDT 24 4029898432 ps
T1076 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1842740497 May 07 04:50:55 PM PDT 24 May 07 04:54:12 PM PDT 24 2574251848 ps
T1077 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3555404695 May 07 04:51:24 PM PDT 24 May 07 04:57:09 PM PDT 24 3792991086 ps
T167 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4114719082 May 07 04:26:30 PM PDT 24 May 07 04:29:07 PM PDT 24 2618990202 ps
T1078 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1909135724 May 07 04:25:15 PM PDT 24 May 07 04:29:22 PM PDT 24 2334561908 ps
T677 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3576735844 May 07 04:41:12 PM PDT 24 May 07 04:43:04 PM PDT 24 2069212528 ps
T1079 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3000336336 May 07 04:51:49 PM PDT 24 May 07 05:03:24 PM PDT 24 6052485910 ps
T1080 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.624549696 May 07 04:45:25 PM PDT 24 May 07 04:54:41 PM PDT 24 5337998760 ps
T1081 /workspace/coverage/default/1.chip_sw_aes_enc.833443995 May 07 04:32:29 PM PDT 24 May 07 04:37:13 PM PDT 24 3265315624 ps
T1082 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2360094200 May 07 04:47:03 PM PDT 24 May 07 04:57:06 PM PDT 24 4599063558 ps
T342 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1100150005 May 07 04:33:01 PM PDT 24 May 07 04:39:46 PM PDT 24 3422686924 ps
T1083 /workspace/coverage/default/4.chip_tap_straps_testunlock0.383842924 May 07 04:49:03 PM PDT 24 May 07 04:57:10 PM PDT 24 5778172855 ps
T1084 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2701304926 May 07 04:38:42 PM PDT 24 May 07 04:42:43 PM PDT 24 2901676744 ps
T1085 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1130543983 May 07 04:44:27 PM PDT 24 May 07 04:48:53 PM PDT 24 2560244940 ps
T715 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699622808 May 07 04:52:58 PM PDT 24 May 07 04:58:39 PM PDT 24 3695260712 ps
T806 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854205411 May 07 04:55:06 PM PDT 24 May 07 05:00:11 PM PDT 24 3046214664 ps
T1086 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2185180744 May 07 04:51:55 PM PDT 24 May 07 05:03:31 PM PDT 24 4768897264 ps
T1087 /workspace/coverage/default/2.chip_tap_straps_prod.3932554507 May 07 04:44:57 PM PDT 24 May 07 04:58:08 PM PDT 24 7535909878 ps
T665 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2364473558 May 07 04:43:08 PM PDT 24 May 07 04:51:41 PM PDT 24 2928890088 ps
T1088 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1436364862 May 07 04:34:35 PM PDT 24 May 07 04:39:12 PM PDT 24 2660413573 ps
T1089 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1743434094 May 07 04:46:07 PM PDT 24 May 07 04:50:23 PM PDT 24 3083065802 ps
T761 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3939465401 May 07 04:53:53 PM PDT 24 May 07 05:03:39 PM PDT 24 4737211250 ps
T80 /workspace/coverage/default/2.chip_sw_gpio_smoketest.600939259 May 07 04:47:39 PM PDT 24 May 07 04:52:30 PM PDT 24 3097408351 ps
T778 /workspace/coverage/default/43.chip_sw_all_escalation_resets.4108865108 May 07 04:56:45 PM PDT 24 May 07 05:10:17 PM PDT 24 5198365290 ps
T1090 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.977844435 May 07 04:24:12 PM PDT 24 May 07 04:29:54 PM PDT 24 3464321876 ps
T1091 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.146606539 May 07 04:26:44 PM PDT 24 May 07 04:31:24 PM PDT 24 3393911041 ps
T1092 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.791785134 May 07 04:42:21 PM PDT 24 May 07 05:34:22 PM PDT 24 16585182196 ps
T1093 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1894567767 May 07 04:25:15 PM PDT 24 May 07 05:00:36 PM PDT 24 7927969920 ps
T1094 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.880594415 May 07 04:33:11 PM PDT 24 May 07 04:37:49 PM PDT 24 2505120120 ps
T236 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2916185806 May 07 04:40:44 PM PDT 24 May 07 04:51:22 PM PDT 24 6671666782 ps
T801 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.48120866 May 07 04:48:58 PM PDT 24 May 07 04:55:04 PM PDT 24 3694854368 ps
T38 /workspace/coverage/default/0.chip_sw_spi_device_tpm.540625574 May 07 04:24:36 PM PDT 24 May 07 04:31:52 PM PDT 24 3797726004 ps
T198 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1252469776 May 07 04:26:28 PM PDT 24 May 07 05:38:22 PM PDT 24 15205248860 ps
T756 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2652330874 May 07 04:47:52 PM PDT 24 May 07 04:57:24 PM PDT 24 5524256244 ps
T7 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.879916654 May 07 04:40:10 PM PDT 24 May 07 04:45:19 PM PDT 24 3171569819 ps
T769 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2417771581 May 07 04:55:03 PM PDT 24 May 07 05:05:05 PM PDT 24 5010203280 ps
T1095 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4158531409 May 07 04:40:42 PM PDT 24 May 07 04:43:54 PM PDT 24 3051835032 ps
T1096 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3425121697 May 07 04:49:57 PM PDT 24 May 07 04:56:48 PM PDT 24 6353660160 ps
T1097 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2358174575 May 07 04:55:01 PM PDT 24 May 07 05:01:23 PM PDT 24 3680480940 ps
T711 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399989976 May 07 04:54:44 PM PDT 24 May 07 05:01:49 PM PDT 24 4530542380 ps
T168 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.659484047 May 07 04:42:56 PM PDT 24 May 07 04:45:38 PM PDT 24 2758134514 ps
T1098 /workspace/coverage/default/0.chip_sw_power_idle_load.42421425 May 07 04:27:52 PM PDT 24 May 07 04:38:34 PM PDT 24 3835891280 ps
T1099 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3360129875 May 07 04:29:00 PM PDT 24 May 07 04:33:21 PM PDT 24 5151933700 ps
T1100 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.640884714 May 07 04:47:08 PM PDT 24 May 07 04:56:13 PM PDT 24 4087561520 ps
T1101 /workspace/coverage/default/1.chip_tap_straps_rma.3915225068 May 07 04:35:00 PM PDT 24 May 07 04:37:44 PM PDT 24 3281879623 ps
T1102 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1400935664 May 07 04:40:39 PM PDT 24 May 07 04:46:44 PM PDT 24 5954630046 ps
T325 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.488139510 May 07 04:39:54 PM PDT 24 May 07 04:49:42 PM PDT 24 3681867772 ps
T381 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2513420286 May 07 04:47:01 PM PDT 24 May 07 04:55:00 PM PDT 24 6768276990 ps
T1103 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1500133108 May 07 04:32:42 PM PDT 24 May 07 04:41:54 PM PDT 24 4727892928 ps
T36 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1608489528 May 07 04:33:36 PM PDT 24 May 07 04:44:23 PM PDT 24 6333690350 ps
T1104 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3184534490 May 07 04:25:52 PM PDT 24 May 07 04:36:30 PM PDT 24 4275526900 ps
T1105 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4203551515 May 07 04:49:04 PM PDT 24 May 07 04:53:09 PM PDT 24 3016844180 ps
T803 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3860472900 May 07 04:50:12 PM PDT 24 May 07 05:00:39 PM PDT 24 5465996824 ps
T1106 /workspace/coverage/default/1.chip_sw_rv_timer_systick_test.1987196128 May 07 04:31:13 PM PDT 24 May 07 06:21:37 PM PDT 24 37854611288 ps
T776 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.153409270 May 07 04:43:30 PM PDT 24 May 07 04:51:49 PM PDT 24 3816156120 ps
T1107 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3334822881 May 07 04:43:52 PM PDT 24 May 07 04:53:12 PM PDT 24 3417298464 ps
T1108 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2723594639 May 07 04:46:23 PM PDT 24 May 07 04:49:57 PM PDT 24 2022911300 ps
T1109 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.865708180 May 07 04:32:52 PM PDT 24 May 07 04:48:32 PM PDT 24 8411389674 ps
T1110 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1068438913 May 07 04:50:22 PM PDT 24 May 07 05:25:30 PM PDT 24 12685653792 ps
T1111 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2490817274 May 07 04:24:31 PM PDT 24 May 07 04:42:24 PM PDT 24 7483200000 ps
T1112 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.884145386 May 07 04:45:37 PM PDT 24 May 07 04:55:06 PM PDT 24 5961434966 ps
T664 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2628657747 May 07 04:44:46 PM PDT 24 May 07 05:45:58 PM PDT 24 25314095186 ps
T390 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3447397509 May 07 04:45:11 PM PDT 24 May 07 04:52:08 PM PDT 24 3865027940 ps
T814 /workspace/coverage/default/9.chip_sw_all_escalation_resets.293536726 May 07 04:48:48 PM PDT 24 May 07 04:58:43 PM PDT 24 5652975084 ps
T1113 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3965395089 May 07 04:34:04 PM PDT 24 May 07 04:44:25 PM PDT 24 5755103736 ps
T1114 /workspace/coverage/default/1.chip_sw_aes_idle.621236844 May 07 04:31:53 PM PDT 24 May 07 04:36:30 PM PDT 24 2690475460 ps
T807 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082223701 May 07 04:54:34 PM PDT 24 May 07 05:00:25 PM PDT 24 3664673272 ps
T298 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.260179228 May 07 04:28:38 PM PDT 24 May 07 04:39:29 PM PDT 24 4864520565 ps
T738 /workspace/coverage/default/54.chip_sw_all_escalation_resets.780447498 May 07 04:59:57 PM PDT 24 May 07 05:10:06 PM PDT 24 5796879320 ps
T1115 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2456665238 May 07 04:48:04 PM PDT 24 May 07 04:58:33 PM PDT 24 4145576896 ps
T1116 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1865081213 May 07 04:29:55 PM PDT 24 May 07 04:38:06 PM PDT 24 4221650728 ps
T237 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3653071790 May 07 04:48:17 PM PDT 24 May 07 04:57:38 PM PDT 24 5997742614 ps
T1117 /workspace/coverage/default/0.chip_sw_power_sleep_load.1259880944 May 07 04:26:35 PM PDT 24 May 07 04:36:53 PM PDT 24 10899289000 ps
T1118 /workspace/coverage/default/70.chip_sw_all_escalation_resets.4166468874 May 07 04:54:21 PM PDT 24 May 07 05:04:43 PM PDT 24 6043897632 ps
T777 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3974448051 May 07 04:53:28 PM PDT 24 May 07 05:02:16 PM PDT 24 4135887888 ps
T800 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626467225 May 07 04:50:48 PM PDT 24 May 07 04:57:49 PM PDT 24 4105576648 ps
T1119 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1885937406 May 07 04:49:10 PM PDT 24 May 07 04:59:23 PM PDT 24 3904150358 ps
T39 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1913938798 May 07 04:30:04 PM PDT 24 May 07 04:36:53 PM PDT 24 4069102234 ps
T794 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1685230742 May 07 04:52:37 PM PDT 24 May 07 04:59:24 PM PDT 24 5437067828 ps
T770 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3448827522 May 07 04:53:55 PM PDT 24 May 07 05:03:23 PM PDT 24 5375166732 ps
T252 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4105039164 May 07 04:24:48 PM PDT 24 May 07 04:34:14 PM PDT 24 7899360491 ps
T54 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3378156886 May 07 04:40:43 PM PDT 24 May 07 04:46:47 PM PDT 24 5360214814 ps
T354 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.617317786 May 07 04:54:18 PM PDT 24 May 07 05:00:32 PM PDT 24 3591843788 ps
T1120 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2163646234 May 07 04:56:20 PM PDT 24 May 07 05:06:00 PM PDT 24 4959309010 ps
T1121 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1020640152 May 07 04:30:25 PM PDT 24 May 07 04:33:27 PM PDT 24 2764816812 ps
T1122 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3237143345 May 07 04:26:19 PM PDT 24 May 07 04:32:24 PM PDT 24 4443524706 ps
T1123 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3098721434 May 07 04:41:14 PM PDT 24 May 07 04:45:47 PM PDT 24 2577631951 ps
T1124 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3993339810 May 07 04:36:01 PM PDT 24 May 07 04:42:57 PM PDT 24 3424903010 ps
T334 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3295675922 May 07 04:33:05 PM PDT 24 May 07 04:43:38 PM PDT 24 19520275880 ps
T1125 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3108647710 May 07 04:25:40 PM PDT 24 May 07 04:36:56 PM PDT 24 7373166252 ps
T1126 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.483466156 May 07 04:42:00 PM PDT 24 May 07 04:51:25 PM PDT 24 7043771334 ps
T1127 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1842373868 May 07 04:33:01 PM PDT 24 May 07 04:37:28 PM PDT 24 2403612684 ps
T1128 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1880681573 May 07 04:47:07 PM PDT 24 May 07 04:58:25 PM PDT 24 4362365576 ps
T716 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1269496171 May 07 04:52:53 PM PDT 24 May 07 05:03:34 PM PDT 24 5374680660 ps
T1129 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2087161088 May 07 04:41:25 PM PDT 24 May 07 05:18:04 PM PDT 24 24553516964 ps
T1130 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1700655933 May 07 04:41:25 PM PDT 24 May 07 04:45:11 PM PDT 24 2623145580 ps
T232 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.838003225 May 07 04:26:42 PM PDT 24 May 07 04:36:26 PM PDT 24 4274027144 ps
T1131 /workspace/coverage/default/0.chip_sw_aes_smoketest.2550509124 May 07 04:27:43 PM PDT 24 May 07 04:32:47 PM PDT 24 2561975380 ps
T1132 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1180581889 May 07 04:49:20 PM PDT 24 May 07 04:58:45 PM PDT 24 8378573889 ps
T1133 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2298562517 May 07 04:29:48 PM PDT 24 May 07 04:33:21 PM PDT 24 2698282192 ps
T1134 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1566278137 May 07 04:49:47 PM PDT 24 May 07 04:54:01 PM PDT 24 3183708182 ps
T1135 /workspace/coverage/default/0.chip_sw_usbdev_stream.913664963 May 07 04:23:38 PM PDT 24 May 07 05:32:43 PM PDT 24 18852871680 ps
T27 /workspace/coverage/default/2.chip_sw_gpio.2730157705 May 07 04:40:24 PM PDT 24 May 07 04:49:17 PM PDT 24 4132400038 ps
T804 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1631521208 May 07 04:51:33 PM PDT 24 May 07 05:00:36 PM PDT 24 4878921532 ps
T1136 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.710200234 May 07 04:46:51 PM PDT 24 May 07 04:56:58 PM PDT 24 4307902216 ps
T790 /workspace/coverage/default/84.chip_sw_all_escalation_resets.1318590892 May 07 04:56:00 PM PDT 24 May 07 05:05:39 PM PDT 24 5040746880 ps
T1137 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3858974787 May 07 04:30:38 PM PDT 24 May 07 06:03:49 PM PDT 24 47653198456 ps
T1138 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2811597253 May 07 04:48:07 PM PDT 24 May 07 04:58:16 PM PDT 24 5319371696 ps
T1139 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2593982141 May 07 04:28:53 PM PDT 24 May 07 04:31:31 PM PDT 24 2073049042 ps
T270 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3131524469 May 07 04:37:49 PM PDT 24 May 07 04:42:27 PM PDT 24 2805770200 ps
T1140 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4157604851 May 07 04:36:52 PM PDT 24 May 07 05:06:57 PM PDT 24 27014142095 ps
T675 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3293723508 May 07 04:45:04 PM PDT 24 May 07 04:56:27 PM PDT 24 5932257893 ps
T238 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1740013157 May 07 04:55:01 PM PDT 24 May 07 05:05:29 PM PDT 24 5269510436 ps
T1141 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3154931631 May 07 04:25:38 PM PDT 24 May 07 04:33:57 PM PDT 24 4117901638 ps
T666 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1824421333 May 07 04:33:24 PM PDT 24 May 07 04:43:15 PM PDT 24 3018392840 ps
T42 /workspace/coverage/default/0.rom_e2e_smoke.2383418682 May 07 04:32:10 PM PDT 24 May 07 05:38:01 PM PDT 24 17279755768 ps
T1142 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4026477674 May 07 04:32:20 PM PDT 24 May 07 04:44:55 PM PDT 24 8510862262 ps
T1143 /workspace/coverage/default/17.chip_sw_all_escalation_resets.2619630655 May 07 04:51:45 PM PDT 24 May 07 05:03:32 PM PDT 24 5736805420 ps
T1144 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3966889345 May 07 04:26:03 PM PDT 24 May 07 04:57:58 PM PDT 24 21625423121 ps
T233 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.67447176 May 07 04:44:12 PM PDT 24 May 07 04:53:22 PM PDT 24 3926834324 ps
T1145 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4031642104 May 07 04:50:13 PM PDT 24 May 07 05:06:32 PM PDT 24 10439361129 ps
T1146 /workspace/coverage/default/0.rom_keymgr_functest.2982836199 May 07 04:28:47 PM PDT 24 May 07 04:39:52 PM PDT 24 5099443096 ps
T766 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1579475202 May 07 04:49:47 PM PDT 24 May 07 05:01:08 PM PDT 24 5456808436 ps
T1147 /workspace/coverage/default/0.chip_sw_gpio_smoketest.1492911405 May 07 04:28:25 PM PDT 24 May 07 04:33:05 PM PDT 24 2867094563 ps
T1148 /workspace/coverage/default/2.chip_sw_hmac_enc.1121107951 May 07 04:43:09 PM PDT 24 May 07 04:46:52 PM PDT 24 3056502960 ps
T1149 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1136863564 May 07 04:43:27 PM PDT 24 May 07 04:53:41 PM PDT 24 6307316170 ps
T1150 /workspace/coverage/default/2.chip_sw_otbn_randomness.2118960168 May 07 04:41:37 PM PDT 24 May 07 04:56:48 PM PDT 24 5876115414 ps
T1151 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4173362643 May 07 04:26:34 PM PDT 24 May 07 04:37:21 PM PDT 24 3210203246 ps
T791 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2369062238 May 07 04:52:01 PM PDT 24 May 07 05:03:36 PM PDT 24 4495201848 ps
T127 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1789004212 May 07 04:48:52 PM PDT 24 May 07 05:07:22 PM PDT 24 8937000862 ps
T1152 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1513192962 May 07 04:23:50 PM PDT 24 May 07 04:42:24 PM PDT 24 9012298157 ps
T1153 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.953506575 May 07 04:23:28 PM PDT 24 May 07 04:31:00 PM PDT 24 4353886160 ps
T1154 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3423030418 May 07 04:23:46 PM PDT 24 May 07 04:28:17 PM PDT 24 2876362383 ps
T774 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3987803260 May 07 04:53:05 PM PDT 24 May 07 04:58:49 PM PDT 24 3600100728 ps
T1155 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.118995062 May 07 04:32:05 PM PDT 24 May 07 04:43:26 PM PDT 24 3963168876 ps
T1156 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1480840577 May 07 04:32:56 PM PDT 24 May 07 04:40:37 PM PDT 24 4122218488 ps
T1157 /workspace/coverage/default/1.chip_sw_aes_smoketest.1105315706 May 07 04:38:25 PM PDT 24 May 07 04:44:24 PM PDT 24 3359406248 ps
T1158 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3401508567 May 07 04:30:32 PM PDT 24 May 07 04:37:14 PM PDT 24 5327602260 ps
T785 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3871106850 May 07 04:53:51 PM PDT 24 May 07 04:59:48 PM PDT 24 3513483250 ps
T28 /workspace/coverage/default/1.chip_sw_gpio.501495346 May 07 04:31:51 PM PDT 24 May 07 04:39:50 PM PDT 24 3669954100 ps
T1159 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1870648706 May 07 04:51:47 PM PDT 24 May 07 05:02:02 PM PDT 24 6310480952 ps
T271 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1673280735 May 07 04:45:14 PM PDT 24 May 07 04:49:14 PM PDT 24 2109406698 ps
T87 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1660388267 May 07 04:51:44 PM PDT 24 May 07 04:57:39 PM PDT 24 3176316734 ps
T1160 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4076833600 May 07 04:48:15 PM PDT 24 May 07 04:57:01 PM PDT 24 7028593080 ps
T1161 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1457739384 May 07 04:25:56 PM PDT 24 May 07 04:30:18 PM PDT 24 2458073912 ps
T1162 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3709734216 May 07 04:49:11 PM PDT 24 May 07 05:03:40 PM PDT 24 11295602845 ps
T779 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.912764450 May 07 04:59:38 PM PDT 24 May 07 05:05:52 PM PDT 24 3156694726 ps
T1163 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3663945722 May 07 04:47:49 PM PDT 24 May 07 04:57:14 PM PDT 24 4858272050 ps
T1164 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2880017925 May 07 04:26:16 PM PDT 24 May 07 04:32:18 PM PDT 24 4731843864 ps
T1165 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2306555645 May 07 04:50:00 PM PDT 24 May 07 04:59:43 PM PDT 24 7074756969 ps
T1166 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3996369175 May 07 04:42:03 PM PDT 24 May 07 05:05:07 PM PDT 24 9106117048 ps
T759 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403211371 May 07 04:54:19 PM PDT 24 May 07 05:01:02 PM PDT 24 3982469272 ps
T1167 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1615715807 May 07 04:24:51 PM PDT 24 May 07 04:28:07 PM PDT 24 2675006200 ps
T1168 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1819403248 May 07 04:40:43 PM PDT 24 May 07 04:55:41 PM PDT 24 10711685933 ps
T1169 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3287024588 May 07 04:42:44 PM PDT 24 May 07 04:46:45 PM PDT 24 3115671360 ps
T8 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2914046209 May 07 04:23:19 PM PDT 24 May 07 04:27:27 PM PDT 24 2445213915 ps
T1170 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4102917020 May 07 04:47:48 PM PDT 24 May 07 04:58:46 PM PDT 24 4391234350 ps
T1171 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1293357658 May 07 04:43:36 PM PDT 24 May 07 04:56:19 PM PDT 24 6895258540 ps
T1172 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3900165748 May 07 04:44:01 PM PDT 24 May 07 05:08:54 PM PDT 24 13251851748 ps
T1173 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4262708122 May 07 04:29:57 PM PDT 24 May 07 04:40:47 PM PDT 24 3534598340 ps
T1174 /workspace/coverage/default/2.chip_tap_straps_rma.1069474815 May 07 04:44:15 PM PDT 24 May 07 04:56:49 PM PDT 24 8253241567 ps
T1175 /workspace/coverage/default/0.chip_sw_example_concurrency.85101349 May 07 04:23:39 PM PDT 24 May 07 04:28:18 PM PDT 24 3202360760 ps
T695 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2410160357 May 07 04:44:29 PM PDT 24 May 07 04:49:56 PM PDT 24 3189845600 ps
T199 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.935329571 May 07 04:44:13 PM PDT 24 May 07 05:49:46 PM PDT 24 15677184936 ps
T1176 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3057467739 May 07 04:33:45 PM PDT 24 May 07 04:42:30 PM PDT 24 6369938750 ps
T1177 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2221654296 May 07 04:44:55 PM PDT 24 May 07 04:52:09 PM PDT 24 3526551736 ps
T1178 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2953258651 May 07 04:24:12 PM PDT 24 May 07 04:33:10 PM PDT 24 4654812118 ps
T678 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2531699299 May 07 04:30:47 PM PDT 24 May 07 04:33:05 PM PDT 24 2760466328 ps
T1179 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2847223396 May 07 04:56:31 PM PDT 24 May 07 05:02:56 PM PDT 24 3522399464 ps
T1180 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4131695445 May 07 04:48:18 PM PDT 24 May 07 04:52:34 PM PDT 24 3035141736 ps
T1181 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1296129626 May 07 04:31:10 PM PDT 24 May 07 04:40:35 PM PDT 24 4153968673 ps
T798 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1541060273 May 07 04:55:08 PM PDT 24 May 07 05:03:36 PM PDT 24 4739809992 ps
T792 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1148750336 May 07 04:54:00 PM PDT 24 May 07 05:04:18 PM PDT 24 4854700420 ps
T1182 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.891587906 May 07 04:33:30 PM PDT 24 May 07 04:57:13 PM PDT 24 12500972636 ps
T1183 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.786803203 May 07 04:44:48 PM PDT 24 May 07 04:56:14 PM PDT 24 3205326188 ps
T1184 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1535400112 May 07 04:53:46 PM PDT 24 May 07 05:00:04 PM PDT 24 3543098040 ps
T1185 /workspace/coverage/default/86.chip_sw_all_escalation_resets.34124937 May 07 04:55:32 PM PDT 24 May 07 05:06:18 PM PDT 24 6404792120 ps
T1186 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3936762195 May 07 04:36:19 PM PDT 24 May 07 04:44:28 PM PDT 24 3459321540 ps
T1187 /workspace/coverage/default/0.chip_sw_aes_masking_off.4006525664 May 07 04:29:34 PM PDT 24 May 07 04:35:51 PM PDT 24 2730109955 ps
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