| T906 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.605773879 |
|
|
May 09 04:15:34 PM PDT 24 |
May 09 04:22:59 PM PDT 24 |
4135595512 ps |
| T356 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2739483923 |
|
|
May 09 04:38:11 PM PDT 24 |
May 09 04:52:13 PM PDT 24 |
5410746943 ps |
| T727 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1801604161 |
|
|
May 09 04:17:54 PM PDT 24 |
May 09 04:25:32 PM PDT 24 |
6041246000 ps |
| T907 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.4224440794 |
|
|
May 09 04:21:29 PM PDT 24 |
May 09 04:25:45 PM PDT 24 |
3011023075 ps |
| T908 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1866227738 |
|
|
May 09 04:39:58 PM PDT 24 |
May 09 04:48:47 PM PDT 24 |
5122727728 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3752909944 |
|
|
May 09 04:40:26 PM PDT 24 |
May 09 04:49:45 PM PDT 24 |
4437459600 ps |
| T696 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1800809850 |
|
|
May 09 04:07:40 PM PDT 24 |
May 09 04:29:14 PM PDT 24 |
7973074460 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2454749791 |
|
|
May 09 04:17:43 PM PDT 24 |
May 09 04:26:31 PM PDT 24 |
5460734928 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1583446417 |
|
|
May 09 04:19:19 PM PDT 24 |
May 09 04:25:08 PM PDT 24 |
5106484810 ps |
| T761 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3851501570 |
|
|
May 09 04:38:24 PM PDT 24 |
May 09 04:46:18 PM PDT 24 |
6035355074 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3957509057 |
|
|
May 09 04:12:08 PM PDT 24 |
May 09 04:19:54 PM PDT 24 |
4468543302 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.518501225 |
|
|
May 09 04:19:28 PM PDT 24 |
May 09 04:33:59 PM PDT 24 |
5811703352 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.138114867 |
|
|
May 09 04:38:22 PM PDT 24 |
May 09 07:29:30 PM PDT 24 |
58630128712 ps |
| T911 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.788817850 |
|
|
May 09 04:43:59 PM PDT 24 |
May 09 04:52:44 PM PDT 24 |
6138669000 ps |
| T912 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3277009156 |
|
|
May 09 04:07:17 PM PDT 24 |
May 09 04:10:26 PM PDT 24 |
2943090436 ps |
| T308 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4239936890 |
|
|
May 09 04:09:19 PM PDT 24 |
May 09 04:20:44 PM PDT 24 |
5430318260 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3804501856 |
|
|
May 09 04:21:48 PM PDT 24 |
May 09 04:29:28 PM PDT 24 |
5867667376 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.450981740 |
|
|
May 09 04:13:25 PM PDT 24 |
May 09 04:21:54 PM PDT 24 |
3470177890 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3217609666 |
|
|
May 09 04:08:18 PM PDT 24 |
May 09 05:02:52 PM PDT 24 |
11810586448 ps |
| T914 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3825036064 |
|
|
May 09 04:40:55 PM PDT 24 |
May 09 05:07:39 PM PDT 24 |
28983565796 ps |
| T915 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2812044933 |
|
|
May 09 04:11:36 PM PDT 24 |
May 09 04:15:46 PM PDT 24 |
2929867458 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2413534187 |
|
|
May 09 04:17:53 PM PDT 24 |
May 09 04:20:27 PM PDT 24 |
2019322706 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1668410683 |
|
|
May 09 04:40:33 PM PDT 24 |
May 09 04:51:31 PM PDT 24 |
4398302598 ps |
| T917 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1552786513 |
|
|
May 09 04:40:06 PM PDT 24 |
May 09 04:49:34 PM PDT 24 |
6441744461 ps |
| T357 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1003065053 |
|
|
May 09 04:39:01 PM PDT 24 |
May 09 04:54:24 PM PDT 24 |
5376669050 ps |
| T733 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.158955734 |
|
|
May 09 04:51:39 PM PDT 24 |
May 09 04:57:08 PM PDT 24 |
3051304916 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3545061645 |
|
|
May 09 04:39:16 PM PDT 24 |
May 09 04:42:45 PM PDT 24 |
3183574796 ps |
| T52 |
/workspace/coverage/default/1.chip_jtag_csr_rw.2946122205 |
|
|
May 09 04:11:19 PM PDT 24 |
May 09 04:39:34 PM PDT 24 |
18311911298 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3330240982 |
|
|
May 09 04:40:26 PM PDT 24 |
May 09 04:45:43 PM PDT 24 |
3673634160 ps |
| T364 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3494617743 |
|
|
May 09 04:51:47 PM PDT 24 |
May 09 05:02:46 PM PDT 24 |
5093993470 ps |
| T365 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.926943996 |
|
|
May 09 04:18:52 PM PDT 24 |
May 09 04:48:08 PM PDT 24 |
13196004332 ps |
| T366 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3780488632 |
|
|
May 09 04:40:51 PM PDT 24 |
May 09 04:45:49 PM PDT 24 |
2527095282 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3186774238 |
|
|
May 09 04:40:55 PM PDT 24 |
May 09 04:45:34 PM PDT 24 |
3199131360 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3956411157 |
|
|
May 09 04:38:16 PM PDT 24 |
May 09 04:56:40 PM PDT 24 |
6250811629 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2122993558 |
|
|
May 09 04:35:51 PM PDT 24 |
May 09 04:40:59 PM PDT 24 |
3220979250 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2128399217 |
|
|
May 09 04:14:09 PM PDT 24 |
May 09 04:24:53 PM PDT 24 |
4162137445 ps |
| T370 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2235539621 |
|
|
May 09 04:42:58 PM PDT 24 |
May 09 04:50:18 PM PDT 24 |
6030836425 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3498106212 |
|
|
May 09 04:13:41 PM PDT 24 |
May 09 04:52:59 PM PDT 24 |
12743975323 ps |
| T726 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044505054 |
|
|
May 09 04:47:22 PM PDT 24 |
May 09 04:55:55 PM PDT 24 |
3320133384 ps |
| T107 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3305348579 |
|
|
May 09 04:22:58 PM PDT 24 |
May 09 05:17:14 PM PDT 24 |
24648981430 ps |
| T332 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.645538084 |
|
|
May 09 04:51:06 PM PDT 24 |
May 09 04:59:14 PM PDT 24 |
5007833870 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.108565650 |
|
|
May 09 04:18:01 PM PDT 24 |
May 09 04:25:34 PM PDT 24 |
3746152479 ps |
| T647 |
/workspace/coverage/default/2.chip_sw_edn_kat.4266519883 |
|
|
May 09 04:39:07 PM PDT 24 |
May 09 04:49:54 PM PDT 24 |
3592276712 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3235429366 |
|
|
May 09 04:09:10 PM PDT 24 |
May 09 04:19:22 PM PDT 24 |
8898385124 ps |
| T67 |
/workspace/coverage/default/0.chip_tap_straps_rma.934943375 |
|
|
May 09 04:08:32 PM PDT 24 |
May 09 04:10:35 PM PDT 24 |
2545988800 ps |
| T920 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2988057225 |
|
|
May 09 04:42:06 PM PDT 24 |
May 09 04:46:13 PM PDT 24 |
2816256424 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1551658228 |
|
|
May 09 04:09:19 PM PDT 24 |
May 09 04:18:42 PM PDT 24 |
4301659272 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2987953733 |
|
|
May 09 04:21:35 PM PDT 24 |
May 09 05:10:13 PM PDT 24 |
21687053199 ps |
| T725 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3385920300 |
|
|
May 09 04:42:38 PM PDT 24 |
May 09 04:50:32 PM PDT 24 |
4199839350 ps |
| T763 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2174897738 |
|
|
May 09 04:43:10 PM PDT 24 |
May 09 04:54:48 PM PDT 24 |
5485406260 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.719150664 |
|
|
May 09 04:20:55 PM PDT 24 |
May 09 04:23:53 PM PDT 24 |
2507978704 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1061673862 |
|
|
May 09 04:22:19 PM PDT 24 |
May 09 04:45:49 PM PDT 24 |
7720835862 ps |
| T923 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2991252195 |
|
|
May 09 04:21:50 PM PDT 24 |
May 09 04:41:48 PM PDT 24 |
5257948520 ps |
| T44 |
/workspace/coverage/default/2.rom_e2e_smoke.3954361239 |
|
|
May 09 04:47:04 PM PDT 24 |
May 09 05:44:43 PM PDT 24 |
17361000352 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3908631305 |
|
|
May 09 04:39:19 PM PDT 24 |
May 09 04:47:50 PM PDT 24 |
4380360700 ps |
| T924 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.260950487 |
|
|
May 09 04:38:10 PM PDT 24 |
May 09 04:47:53 PM PDT 24 |
4125546142 ps |
| T925 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3791791335 |
|
|
May 09 04:38:12 PM PDT 24 |
May 09 04:45:40 PM PDT 24 |
3290899698 ps |
| T926 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2808642698 |
|
|
May 09 04:23:57 PM PDT 24 |
May 09 04:27:52 PM PDT 24 |
3031850908 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1938807639 |
|
|
May 09 04:08:41 PM PDT 24 |
May 09 04:14:16 PM PDT 24 |
4892060600 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.951374518 |
|
|
May 09 04:41:39 PM PDT 24 |
May 09 05:01:32 PM PDT 24 |
7507136800 ps |
| T749 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3869485886 |
|
|
May 09 04:45:01 PM PDT 24 |
May 09 04:56:56 PM PDT 24 |
5429849568 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1471598437 |
|
|
May 09 04:08:43 PM PDT 24 |
May 09 04:16:27 PM PDT 24 |
4347593488 ps |
| T928 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2522117884 |
|
|
May 09 04:11:59 PM PDT 24 |
May 09 04:15:55 PM PDT 24 |
2506469785 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3502980458 |
|
|
May 09 04:19:12 PM PDT 24 |
May 09 04:27:27 PM PDT 24 |
4461248976 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4196988686 |
|
|
May 09 04:12:08 PM PDT 24 |
May 09 04:20:25 PM PDT 24 |
5289545884 ps |
| T930 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1997832184 |
|
|
May 09 04:39:22 PM PDT 24 |
May 09 04:59:46 PM PDT 24 |
5740627656 ps |
| T734 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3714303148 |
|
|
May 09 04:19:29 PM PDT 24 |
May 09 04:23:26 PM PDT 24 |
2463117451 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.121068837 |
|
|
May 09 04:40:27 PM PDT 24 |
May 09 05:39:41 PM PDT 24 |
18274023152 ps |
| T712 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2264681546 |
|
|
May 09 04:37:48 PM PDT 24 |
May 09 04:46:37 PM PDT 24 |
4573320468 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1939455991 |
|
|
May 09 04:38:08 PM PDT 24 |
May 09 04:47:19 PM PDT 24 |
4415972352 ps |
| T931 |
/workspace/coverage/default/1.chip_tap_straps_rma.1988931871 |
|
|
May 09 04:21:19 PM PDT 24 |
May 09 04:26:07 PM PDT 24 |
4086063156 ps |
| T716 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1049394031 |
|
|
May 09 04:46:01 PM PDT 24 |
May 09 04:57:48 PM PDT 24 |
5778678914 ps |
| T730 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.613646413 |
|
|
May 09 04:49:30 PM PDT 24 |
May 09 04:56:25 PM PDT 24 |
3733124504 ps |
| T781 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3807365531 |
|
|
May 09 04:49:18 PM PDT 24 |
May 09 04:55:45 PM PDT 24 |
3832476572 ps |
| T24 |
/workspace/coverage/default/2.chip_jtag_csr_rw.551430844 |
|
|
May 09 04:29:18 PM PDT 24 |
May 09 04:46:22 PM PDT 24 |
10582530906 ps |
| T766 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1292267614 |
|
|
May 09 04:46:44 PM PDT 24 |
May 09 04:55:30 PM PDT 24 |
5116399130 ps |
| T767 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1415757819 |
|
|
May 09 04:46:50 PM PDT 24 |
May 09 04:51:46 PM PDT 24 |
3387179756 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.3282054760 |
|
|
May 09 04:38:08 PM PDT 24 |
May 09 04:45:47 PM PDT 24 |
3620160372 ps |
| T799 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.473496977 |
|
|
May 09 04:42:10 PM PDT 24 |
May 09 04:49:06 PM PDT 24 |
4237037876 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3607861304 |
|
|
May 09 04:21:27 PM PDT 24 |
May 09 04:29:45 PM PDT 24 |
9475688384 ps |
| T648 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3515022981 |
|
|
May 09 04:38:55 PM PDT 24 |
May 09 04:47:33 PM PDT 24 |
2991275700 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2310835234 |
|
|
May 09 04:08:54 PM PDT 24 |
May 09 04:13:52 PM PDT 24 |
3064160340 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3286812086 |
|
|
May 09 04:41:31 PM PDT 24 |
May 09 04:47:57 PM PDT 24 |
5575704884 ps |
| T932 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.427265180 |
|
|
May 09 04:39:53 PM PDT 24 |
May 09 04:50:27 PM PDT 24 |
4628798820 ps |
| T933 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.448455377 |
|
|
May 09 04:45:41 PM PDT 24 |
May 09 04:57:02 PM PDT 24 |
4547314920 ps |
| T669 |
/workspace/coverage/default/2.chip_sw_power_idle_load.494053679 |
|
|
May 09 04:42:22 PM PDT 24 |
May 09 04:53:25 PM PDT 24 |
4156389430 ps |
| T681 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2712586984 |
|
|
May 09 04:49:30 PM PDT 24 |
May 09 04:58:39 PM PDT 24 |
5470248926 ps |
| T934 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2689653843 |
|
|
May 09 04:24:20 PM PDT 24 |
May 09 04:27:33 PM PDT 24 |
2631776939 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.562669990 |
|
|
May 09 04:09:07 PM PDT 24 |
May 09 04:15:24 PM PDT 24 |
3177454164 ps |
| T936 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3974529988 |
|
|
May 09 04:09:44 PM PDT 24 |
May 09 04:14:16 PM PDT 24 |
3481535269 ps |
| T86 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4189588906 |
|
|
May 09 04:40:41 PM PDT 24 |
May 09 04:46:15 PM PDT 24 |
3444449382 ps |
| T41 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.2922586450 |
|
|
May 09 04:17:20 PM PDT 24 |
May 09 04:21:46 PM PDT 24 |
3306428396 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3003974677 |
|
|
May 09 04:38:07 PM PDT 24 |
May 09 04:46:33 PM PDT 24 |
5878756360 ps |
| T58 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2883041726 |
|
|
May 09 04:22:31 PM PDT 24 |
May 09 04:50:24 PM PDT 24 |
18359152616 ps |
| T407 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3149965867 |
|
|
May 09 04:41:48 PM PDT 24 |
May 09 05:06:48 PM PDT 24 |
7488705672 ps |
| T154 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1515047157 |
|
|
May 09 04:09:34 PM PDT 24 |
May 09 04:47:06 PM PDT 24 |
25637136647 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2291453602 |
|
|
May 09 04:09:33 PM PDT 24 |
May 09 04:18:14 PM PDT 24 |
5952610424 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.551486303 |
|
|
May 09 04:10:38 PM PDT 24 |
May 09 04:21:02 PM PDT 24 |
4774144890 ps |
| T782 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3889681593 |
|
|
May 09 04:44:16 PM PDT 24 |
May 09 04:54:02 PM PDT 24 |
6295909848 ps |
| T735 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.400855163 |
|
|
May 09 04:49:09 PM PDT 24 |
May 09 04:56:46 PM PDT 24 |
3762515354 ps |
| T791 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4204659815 |
|
|
May 09 04:52:38 PM PDT 24 |
May 09 04:59:31 PM PDT 24 |
4900390780 ps |
| T939 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2523905564 |
|
|
May 09 04:18:34 PM PDT 24 |
May 09 07:31:03 PM PDT 24 |
64010259880 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2021942899 |
|
|
May 09 04:42:25 PM PDT 24 |
May 09 04:46:00 PM PDT 24 |
2729761604 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.208828430 |
|
|
May 09 04:39:31 PM PDT 24 |
May 09 06:10:30 PM PDT 24 |
49106193084 ps |
| T940 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1722807320 |
|
|
May 09 04:21:15 PM PDT 24 |
May 09 04:31:19 PM PDT 24 |
4882693120 ps |
| T760 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3730397621 |
|
|
May 09 04:42:38 PM PDT 24 |
May 09 04:53:57 PM PDT 24 |
4699411344 ps |
| T143 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.841830844 |
|
|
May 09 04:09:50 PM PDT 24 |
May 09 04:20:01 PM PDT 24 |
3947985760 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1473469727 |
|
|
May 09 04:41:08 PM PDT 24 |
May 09 05:00:18 PM PDT 24 |
20159978226 ps |
| T941 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1579106120 |
|
|
May 09 04:41:53 PM PDT 24 |
May 09 05:17:05 PM PDT 24 |
13060356196 ps |
| T298 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2651700713 |
|
|
May 09 04:44:04 PM PDT 24 |
May 09 04:55:20 PM PDT 24 |
4607172284 ps |
| T942 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.509688743 |
|
|
May 09 04:43:05 PM PDT 24 |
May 09 04:52:50 PM PDT 24 |
6384125474 ps |
| T408 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.171646920 |
|
|
May 09 04:12:03 PM PDT 24 |
May 09 04:24:41 PM PDT 24 |
4935637797 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3475487112 |
|
|
May 09 04:09:00 PM PDT 24 |
May 09 04:13:13 PM PDT 24 |
2568761300 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.803073722 |
|
|
May 09 04:14:30 PM PDT 24 |
May 09 04:22:30 PM PDT 24 |
6290426718 ps |
| T295 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.161610573 |
|
|
May 09 04:18:37 PM PDT 24 |
May 09 04:27:14 PM PDT 24 |
3871649174 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4202663880 |
|
|
May 09 04:20:52 PM PDT 24 |
May 09 04:25:21 PM PDT 24 |
2763138287 ps |
| T127 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3729399620 |
|
|
May 09 04:42:22 PM PDT 24 |
May 09 04:49:22 PM PDT 24 |
4011019576 ps |
| T946 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.347748600 |
|
|
May 09 04:39:53 PM PDT 24 |
May 09 04:46:57 PM PDT 24 |
6819775990 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2577934638 |
|
|
May 09 04:18:11 PM PDT 24 |
May 09 04:27:42 PM PDT 24 |
4964387864 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3628337949 |
|
|
May 09 04:09:03 PM PDT 24 |
May 09 04:11:20 PM PDT 24 |
3325486181 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2834875115 |
|
|
May 09 04:36:58 PM PDT 24 |
May 09 04:54:20 PM PDT 24 |
8609814442 ps |
| T949 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.50024699 |
|
|
May 09 04:41:59 PM PDT 24 |
May 09 04:52:02 PM PDT 24 |
4656561160 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_flash_init.1032042880 |
|
|
May 09 04:18:20 PM PDT 24 |
May 09 04:43:21 PM PDT 24 |
16838996406 ps |
| T309 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.616630639 |
|
|
May 09 04:19:16 PM PDT 24 |
May 09 04:29:52 PM PDT 24 |
4898591590 ps |
| T292 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3082315919 |
|
|
May 09 04:43:22 PM PDT 24 |
May 09 04:54:33 PM PDT 24 |
4488889264 ps |
| T731 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438036680 |
|
|
May 09 04:52:42 PM PDT 24 |
May 09 04:59:31 PM PDT 24 |
4280308504 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1437911828 |
|
|
May 09 04:09:32 PM PDT 24 |
May 09 04:28:01 PM PDT 24 |
8651860112 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.277909463 |
|
|
May 09 04:08:33 PM PDT 24 |
May 09 04:16:09 PM PDT 24 |
4411101050 ps |
| T649 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.723425704 |
|
|
May 09 04:45:08 PM PDT 24 |
May 09 04:51:43 PM PDT 24 |
3778478302 ps |
| T952 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3432221205 |
|
|
May 09 04:13:18 PM PDT 24 |
May 09 04:27:04 PM PDT 24 |
9955924136 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3461433232 |
|
|
May 09 04:40:12 PM PDT 24 |
May 09 04:46:23 PM PDT 24 |
3408351828 ps |
| T398 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.4101920095 |
|
|
May 09 04:44:17 PM PDT 24 |
May 09 04:52:01 PM PDT 24 |
4198446980 ps |
| T227 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3350626584 |
|
|
May 09 04:42:18 PM PDT 24 |
May 09 04:55:37 PM PDT 24 |
5530962280 ps |
| T229 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.891152821 |
|
|
May 09 04:40:54 PM PDT 24 |
May 09 04:50:07 PM PDT 24 |
6155882526 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2618212913 |
|
|
May 09 04:24:15 PM PDT 24 |
May 09 04:28:22 PM PDT 24 |
2715432410 ps |
| T231 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.718559780 |
|
|
May 09 04:13:10 PM PDT 24 |
May 09 04:17:18 PM PDT 24 |
2431612500 ps |
| T232 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.4038679590 |
|
|
May 09 04:40:32 PM PDT 24 |
May 09 04:43:59 PM PDT 24 |
2427965893 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.714345689 |
|
|
May 09 04:10:08 PM PDT 24 |
May 09 04:18:45 PM PDT 24 |
4786220004 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.193224395 |
|
|
May 09 04:07:55 PM PDT 24 |
May 09 04:13:19 PM PDT 24 |
3986152356 ps |
| T235 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2207165811 |
|
|
May 09 04:52:53 PM PDT 24 |
May 09 04:58:18 PM PDT 24 |
3521255460 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1393934841 |
|
|
May 09 04:18:50 PM PDT 24 |
May 09 04:22:35 PM PDT 24 |
2745716396 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.546968924 |
|
|
May 09 04:38:25 PM PDT 24 |
May 09 04:49:30 PM PDT 24 |
4250767684 ps |
| T954 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1194940720 |
|
|
May 09 04:40:58 PM PDT 24 |
May 09 05:09:35 PM PDT 24 |
9129106344 ps |
| T225 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.459417031 |
|
|
May 09 04:44:24 PM PDT 24 |
May 09 04:52:43 PM PDT 24 |
9033642024 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.658017863 |
|
|
May 09 04:39:42 PM PDT 24 |
May 09 04:44:36 PM PDT 24 |
6322521667 ps |
| T293 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.409611121 |
|
|
May 09 04:24:13 PM PDT 24 |
May 09 04:44:52 PM PDT 24 |
5609633480 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4056975191 |
|
|
May 09 04:18:38 PM PDT 24 |
May 09 04:25:01 PM PDT 24 |
6305801948 ps |
| T728 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3876908233 |
|
|
May 09 04:48:39 PM PDT 24 |
May 09 04:59:15 PM PDT 24 |
6152227956 ps |
| T644 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1997317975 |
|
|
May 09 04:21:22 PM PDT 24 |
May 09 04:42:34 PM PDT 24 |
5014140760 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2431592271 |
|
|
May 09 04:40:16 PM PDT 24 |
May 09 04:45:44 PM PDT 24 |
2375662512 ps |
| T958 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2091001759 |
|
|
May 09 04:43:52 PM PDT 24 |
May 09 04:53:33 PM PDT 24 |
3833144700 ps |
| T775 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1876148564 |
|
|
May 09 04:52:46 PM PDT 24 |
May 09 04:58:50 PM PDT 24 |
3543515740 ps |
| T661 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3509126735 |
|
|
May 09 04:43:07 PM PDT 24 |
May 09 04:53:44 PM PDT 24 |
5188345319 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.509825662 |
|
|
May 09 04:21:56 PM PDT 24 |
May 09 04:23:50 PM PDT 24 |
2162189824 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2361804719 |
|
|
May 09 04:11:18 PM PDT 24 |
May 09 04:21:43 PM PDT 24 |
10161224710 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3141287781 |
|
|
May 09 04:39:16 PM PDT 24 |
May 09 04:43:45 PM PDT 24 |
2547762056 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2341655870 |
|
|
May 09 04:08:41 PM PDT 24 |
May 09 04:34:17 PM PDT 24 |
11855480183 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2861349913 |
|
|
May 09 04:08:29 PM PDT 24 |
May 09 04:43:29 PM PDT 24 |
24327738288 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.3506965410 |
|
|
May 09 04:40:10 PM PDT 24 |
May 09 04:52:55 PM PDT 24 |
5949573108 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3062835787 |
|
|
May 09 04:41:14 PM PDT 24 |
May 09 04:46:54 PM PDT 24 |
2627607113 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2283721427 |
|
|
May 09 04:40:56 PM PDT 24 |
May 09 04:57:07 PM PDT 24 |
10878093494 ps |
| T317 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1119278854 |
|
|
May 09 04:43:14 PM PDT 24 |
May 09 04:51:04 PM PDT 24 |
6126244964 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1471992483 |
|
|
May 09 04:40:55 PM PDT 24 |
May 09 04:48:41 PM PDT 24 |
5827882376 ps |
| T965 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4289292050 |
|
|
May 09 04:42:32 PM PDT 24 |
May 09 04:51:41 PM PDT 24 |
4091342315 ps |
| T211 |
/workspace/coverage/default/1.chip_jtag_mem_access.2976595628 |
|
|
May 09 04:11:17 PM PDT 24 |
May 09 04:28:20 PM PDT 24 |
13408778070 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2104992990 |
|
|
May 09 04:40:21 PM PDT 24 |
May 09 04:44:46 PM PDT 24 |
2544270728 ps |
| T967 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1397929952 |
|
|
May 09 04:42:21 PM PDT 24 |
May 09 05:06:23 PM PDT 24 |
12789437670 ps |
| T226 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2446861948 |
|
|
May 09 04:19:46 PM PDT 24 |
May 09 04:22:37 PM PDT 24 |
3084094780 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3959426781 |
|
|
May 09 04:09:08 PM PDT 24 |
May 09 04:16:31 PM PDT 24 |
3970193650 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2191124457 |
|
|
May 09 04:40:18 PM PDT 24 |
May 09 06:02:36 PM PDT 24 |
48874735230 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3221089475 |
|
|
May 09 04:22:02 PM PDT 24 |
May 09 04:25:41 PM PDT 24 |
2648851558 ps |
| T144 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1225773385 |
|
|
May 09 04:44:38 PM PDT 24 |
May 09 04:53:34 PM PDT 24 |
4284506552 ps |
| T240 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1640540157 |
|
|
May 09 04:09:47 PM PDT 24 |
May 09 04:22:52 PM PDT 24 |
5141450000 ps |
| T124 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.572523913 |
|
|
May 09 04:42:56 PM PDT 24 |
May 09 04:56:28 PM PDT 24 |
6341953448 ps |
| T721 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.4082422319 |
|
|
May 09 04:46:54 PM PDT 24 |
May 09 04:55:08 PM PDT 24 |
5387719808 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.180104634 |
|
|
May 09 04:07:56 PM PDT 24 |
May 09 04:15:59 PM PDT 24 |
8042961944 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.410409624 |
|
|
May 09 04:08:25 PM PDT 24 |
May 09 04:55:59 PM PDT 24 |
29940141700 ps |
| T87 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3125161159 |
|
|
May 09 04:47:44 PM PDT 24 |
May 09 04:57:34 PM PDT 24 |
5837075016 ps |
| T971 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1842641271 |
|
|
May 09 04:42:11 PM PDT 24 |
May 09 04:51:19 PM PDT 24 |
3927765060 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3773439296 |
|
|
May 09 04:09:25 PM PDT 24 |
May 09 04:15:57 PM PDT 24 |
5048926664 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.944911268 |
|
|
May 09 04:41:35 PM PDT 24 |
May 09 04:55:44 PM PDT 24 |
7479996520 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.563347128 |
|
|
May 09 04:40:42 PM PDT 24 |
May 09 05:09:08 PM PDT 24 |
10502385536 ps |
| T53 |
/workspace/coverage/default/0.chip_jtag_csr_rw.4251307076 |
|
|
May 09 04:02:08 PM PDT 24 |
May 09 04:23:56 PM PDT 24 |
14276758894 ps |
| T709 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.909387463 |
|
|
May 09 04:43:58 PM PDT 24 |
May 09 04:51:01 PM PDT 24 |
4020841686 ps |
| T743 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3109795133 |
|
|
May 09 04:42:30 PM PDT 24 |
May 09 04:55:05 PM PDT 24 |
5011506700 ps |
| T323 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.723570698 |
|
|
May 09 04:38:27 PM PDT 24 |
May 09 05:11:00 PM PDT 24 |
22376672107 ps |
| T974 |
/workspace/coverage/default/2.chip_tap_straps_dev.3913897135 |
|
|
May 09 04:40:33 PM PDT 24 |
May 09 04:43:23 PM PDT 24 |
2315514938 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_example_flash.2132254750 |
|
|
May 09 04:35:05 PM PDT 24 |
May 09 04:40:44 PM PDT 24 |
2821855924 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2872697178 |
|
|
May 09 04:38:10 PM PDT 24 |
May 09 04:46:52 PM PDT 24 |
6276896280 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1154181722 |
|
|
May 09 04:11:17 PM PDT 24 |
May 09 04:14:02 PM PDT 24 |
3059777600 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3361876891 |
|
|
May 09 04:21:21 PM PDT 24 |
May 09 04:30:11 PM PDT 24 |
8809092140 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1558624848 |
|
|
May 09 04:19:56 PM PDT 24 |
May 09 04:26:54 PM PDT 24 |
4574375929 ps |
| T978 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2888461679 |
|
|
May 09 04:45:27 PM PDT 24 |
May 09 05:00:28 PM PDT 24 |
8744284621 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.554382484 |
|
|
May 09 04:20:40 PM PDT 24 |
May 09 04:47:12 PM PDT 24 |
6449321072 ps |
| T713 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2359956683 |
|
|
May 09 04:41:23 PM PDT 24 |
May 09 04:50:20 PM PDT 24 |
5490484392 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2177666699 |
|
|
May 09 04:09:39 PM PDT 24 |
May 09 04:19:31 PM PDT 24 |
6308132000 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2973571650 |
|
|
May 09 04:19:28 PM PDT 24 |
May 09 04:35:13 PM PDT 24 |
12066118285 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3044969302 |
|
|
May 09 04:42:23 PM PDT 24 |
May 09 04:59:19 PM PDT 24 |
5985642160 ps |
| T983 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.781317787 |
|
|
May 09 04:19:08 PM PDT 24 |
May 09 04:42:43 PM PDT 24 |
8903667278 ps |
| T717 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858411886 |
|
|
May 09 04:47:42 PM PDT 24 |
May 09 04:55:48 PM PDT 24 |
3542452192 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1694722189 |
|
|
May 09 04:08:37 PM PDT 24 |
May 09 05:21:01 PM PDT 24 |
19578308443 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2337699999 |
|
|
May 09 04:07:59 PM PDT 24 |
May 09 04:12:33 PM PDT 24 |
2489744400 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.462384289 |
|
|
May 09 04:09:39 PM PDT 24 |
May 09 04:13:07 PM PDT 24 |
2893977951 ps |
| T986 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2614983759 |
|
|
May 09 04:46:40 PM PDT 24 |
May 09 04:53:29 PM PDT 24 |
3836088326 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.634077203 |
|
|
May 09 04:10:52 PM PDT 24 |
May 09 04:21:58 PM PDT 24 |
4649890680 ps |
| T645 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3559357622 |
|
|
May 09 04:39:43 PM PDT 24 |
May 09 04:57:07 PM PDT 24 |
5192154192 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4076663718 |
|
|
May 09 04:39:41 PM PDT 24 |
May 09 04:44:16 PM PDT 24 |
3223732820 ps |
| T300 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.540126208 |
|
|
May 09 04:38:17 PM PDT 24 |
May 09 04:47:41 PM PDT 24 |
3705971044 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1930945697 |
|
|
May 09 04:19:55 PM PDT 24 |
May 09 04:34:03 PM PDT 24 |
8504784711 ps |
| T242 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2629432745 |
|
|
May 09 04:19:52 PM PDT 24 |
May 09 04:26:43 PM PDT 24 |
3178498696 ps |
| T97 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.625933890 |
|
|
May 09 04:19:32 PM PDT 24 |
May 09 04:36:40 PM PDT 24 |
20847866178 ps |
| T57 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1790495374 |
|
|
May 09 04:39:24 PM PDT 24 |
May 09 04:44:08 PM PDT 24 |
2847384360 ps |
| T45 |
/workspace/coverage/default/1.rom_e2e_smoke.4118016335 |
|
|
May 09 04:26:13 PM PDT 24 |
May 09 05:34:29 PM PDT 24 |
17414345068 ps |
| T699 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.223867895 |
|
|
May 09 04:21:23 PM PDT 24 |
May 09 04:29:28 PM PDT 24 |
4868636768 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.531273364 |
|
|
May 09 04:19:07 PM PDT 24 |
May 09 04:38:15 PM PDT 24 |
14188230221 ps |
| T29 |
/workspace/coverage/default/0.chip_sw_gpio.1758147556 |
|
|
May 09 04:08:44 PM PDT 24 |
May 09 04:17:39 PM PDT 24 |
4151460863 ps |
| T59 |
/workspace/coverage/default/2.chip_sw_alert_test.2122670751 |
|
|
May 09 04:42:01 PM PDT 24 |
May 09 04:48:41 PM PDT 24 |
2848866166 ps |
| T991 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3101882434 |
|
|
May 09 04:46:32 PM PDT 24 |
May 09 04:55:54 PM PDT 24 |
6882904147 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2803028442 |
|
|
May 09 04:23:37 PM PDT 24 |
May 09 04:34:53 PM PDT 24 |
4516198932 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.416113215 |
|
|
May 09 04:21:15 PM PDT 24 |
May 09 04:33:04 PM PDT 24 |
3567240180 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.3548164355 |
|
|
May 09 04:43:57 PM PDT 24 |
May 09 04:47:19 PM PDT 24 |
3122861624 ps |
| T995 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3349118102 |
|
|
May 09 04:40:12 PM PDT 24 |
May 09 04:55:44 PM PDT 24 |
10116727458 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1821228429 |
|
|
May 09 04:07:40 PM PDT 24 |
May 09 04:13:13 PM PDT 24 |
2836096656 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.918754647 |
|
|
May 09 04:20:10 PM PDT 24 |
May 09 04:24:26 PM PDT 24 |
2553354200 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2927783733 |
|
|
May 09 04:09:23 PM PDT 24 |
May 09 04:18:10 PM PDT 24 |
4819689480 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.131731716 |
|
|
May 09 04:09:38 PM PDT 24 |
May 09 04:14:12 PM PDT 24 |
3014288638 ps |
| T999 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3190157937 |
|
|
May 09 04:43:36 PM PDT 24 |
May 09 05:18:30 PM PDT 24 |
13129628968 ps |
| T1000 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1546631240 |
|
|
May 09 04:39:51 PM PDT 24 |
May 09 04:43:23 PM PDT 24 |
2773498000 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3608791784 |
|
|
May 09 04:43:37 PM PDT 24 |
May 09 05:13:23 PM PDT 24 |
13625879363 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1521748655 |
|
|
May 09 04:08:29 PM PDT 24 |
May 09 04:17:30 PM PDT 24 |
3880243015 ps |
| T771 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1215714787 |
|
|
May 09 04:42:32 PM PDT 24 |
May 09 04:54:35 PM PDT 24 |
5460044832 ps |
| T752 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1010164878 |
|
|
May 09 04:43:51 PM PDT 24 |
May 09 04:54:19 PM PDT 24 |
5268083096 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1527877791 |
|
|
May 09 04:38:17 PM PDT 24 |
May 09 04:48:56 PM PDT 24 |
6880554856 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1584476738 |
|
|
May 09 04:09:50 PM PDT 24 |
May 09 04:30:06 PM PDT 24 |
7284814952 ps |
| T764 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084673529 |
|
|
May 09 04:45:01 PM PDT 24 |
May 09 04:51:27 PM PDT 24 |
3540556160 ps |
| T220 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1203085876 |
|
|
May 09 04:40:38 PM PDT 24 |
May 09 04:47:47 PM PDT 24 |
4764799480 ps |
| T738 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4260127685 |
|
|
May 09 04:40:13 PM PDT 24 |
May 09 04:51:30 PM PDT 24 |
6051283046 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3969278559 |
|
|
May 09 04:08:54 PM PDT 24 |
May 09 04:22:08 PM PDT 24 |
6730992453 ps |
| T302 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3011653541 |
|
|
May 09 04:24:29 PM PDT 24 |
May 09 04:35:46 PM PDT 24 |
4411942848 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2898306580 |
|
|
May 09 04:21:50 PM PDT 24 |
May 09 04:35:26 PM PDT 24 |
7051211535 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.880952204 |
|
|
May 09 04:36:18 PM PDT 24 |
May 09 04:41:51 PM PDT 24 |
3325258290 ps |
| T313 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2510473215 |
|
|
May 09 04:19:06 PM PDT 24 |
May 09 04:25:55 PM PDT 24 |
3586176912 ps |
| T1004 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4024006197 |
|
|
May 09 04:39:36 PM PDT 24 |
May 09 04:50:02 PM PDT 24 |
4635313600 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3769986078 |
|
|
May 09 04:11:19 PM PDT 24 |
May 09 04:18:11 PM PDT 24 |
4951057450 ps |
| T720 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.868824009 |
|
|
May 09 04:37:16 PM PDT 24 |
May 09 04:43:39 PM PDT 24 |
3705949598 ps |
| T650 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409426055 |
|
|
May 09 04:45:07 PM PDT 24 |
May 09 04:53:09 PM PDT 24 |
4236275626 ps |
| T740 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1666378777 |
|
|
May 09 04:14:10 PM PDT 24 |
May 09 04:24:17 PM PDT 24 |
4430331520 ps |
| T685 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.847561033 |
|
|
May 09 04:48:50 PM PDT 24 |
May 09 04:55:47 PM PDT 24 |
4015973392 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.830437561 |
|
|
May 09 04:11:37 PM PDT 24 |
May 09 04:17:40 PM PDT 24 |
4008704200 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3358263418 |
|
|
May 09 04:40:57 PM PDT 24 |
May 09 04:50:13 PM PDT 24 |
7546618904 ps |