| T1151 |
/workspace/coverage/default/0.chip_sw_edn_kat.3334010200 |
|
|
May 09 04:10:31 PM PDT 24 |
May 09 04:20:31 PM PDT 24 |
3793458800 ps |
| T166 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1914630405 |
|
|
May 09 04:17:42 PM PDT 24 |
May 09 05:37:02 PM PDT 24 |
42577197775 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3063067805 |
|
|
May 09 04:14:28 PM PDT 24 |
May 09 04:43:16 PM PDT 24 |
8281422176 ps |
| T1153 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.953206563 |
|
|
May 09 04:42:33 PM PDT 24 |
May 09 04:51:50 PM PDT 24 |
5454189960 ps |
| T1154 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3556608424 |
|
|
May 09 04:43:31 PM PDT 24 |
May 09 05:06:07 PM PDT 24 |
8192267341 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.4177992374 |
|
|
May 09 04:12:05 PM PDT 24 |
May 09 04:16:23 PM PDT 24 |
2921010856 ps |
| T342 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.47934835 |
|
|
May 09 04:11:19 PM PDT 24 |
May 09 04:14:59 PM PDT 24 |
2703712016 ps |
| T744 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3262942717 |
|
|
May 09 04:44:13 PM PDT 24 |
May 09 04:53:46 PM PDT 24 |
5603309336 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.807563297 |
|
|
May 09 04:19:21 PM PDT 24 |
May 09 04:26:41 PM PDT 24 |
4132822760 ps |
| T777 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4292894533 |
|
|
May 09 04:43:30 PM PDT 24 |
May 09 04:50:00 PM PDT 24 |
3764203490 ps |
| T198 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.196430816 |
|
|
May 09 04:21:06 PM PDT 24 |
May 09 05:45:27 PM PDT 24 |
50837821210 ps |
| T1157 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1060902705 |
|
|
May 09 04:40:11 PM PDT 24 |
May 09 04:48:16 PM PDT 24 |
4763558328 ps |
| T1158 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3515412782 |
|
|
May 09 04:48:05 PM PDT 24 |
May 09 04:58:31 PM PDT 24 |
4693874364 ps |
| T1159 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.512420675 |
|
|
May 09 04:44:59 PM PDT 24 |
May 09 04:52:55 PM PDT 24 |
3712426686 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3236861302 |
|
|
May 09 04:08:29 PM PDT 24 |
May 09 04:58:39 PM PDT 24 |
11985053564 ps |
| T769 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3404926973 |
|
|
May 09 04:48:58 PM PDT 24 |
May 09 04:56:54 PM PDT 24 |
5484467316 ps |
| T1161 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.4099086034 |
|
|
May 09 04:36:18 PM PDT 24 |
May 09 04:41:27 PM PDT 24 |
3456006620 ps |
| T719 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2256047106 |
|
|
May 09 04:44:48 PM PDT 24 |
May 09 04:54:41 PM PDT 24 |
6128868510 ps |
| T1162 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1309442447 |
|
|
May 09 04:20:55 PM PDT 24 |
May 09 04:28:21 PM PDT 24 |
4293441306 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.3051641510 |
|
|
May 09 04:41:25 PM PDT 24 |
May 09 04:47:35 PM PDT 24 |
3341004520 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1327219846 |
|
|
May 09 04:19:15 PM PDT 24 |
May 09 04:21:14 PM PDT 24 |
2908377749 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.476347509 |
|
|
May 09 04:41:29 PM PDT 24 |
May 09 04:46:49 PM PDT 24 |
7736120336 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.71129047 |
|
|
May 09 04:07:33 PM PDT 24 |
May 09 05:39:34 PM PDT 24 |
32325338808 ps |
| T1165 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1073193182 |
|
|
May 09 04:18:33 PM PDT 24 |
May 09 04:27:34 PM PDT 24 |
4153030440 ps |
| T755 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826098772 |
|
|
May 09 04:46:32 PM PDT 24 |
May 09 04:51:56 PM PDT 24 |
3348179014 ps |
| T152 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3761067514 |
|
|
May 09 04:08:48 PM PDT 24 |
May 09 04:22:01 PM PDT 24 |
5837109762 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1862325501 |
|
|
May 09 04:39:55 PM PDT 24 |
May 09 04:52:38 PM PDT 24 |
4030482420 ps |
| T750 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1910602546 |
|
|
May 09 04:52:38 PM PDT 24 |
May 09 05:01:10 PM PDT 24 |
3682002184 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.532194632 |
|
|
May 09 04:20:44 PM PDT 24 |
May 09 04:27:32 PM PDT 24 |
4413124642 ps |
| T1168 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2401492725 |
|
|
May 09 04:42:46 PM PDT 24 |
May 09 05:19:23 PM PDT 24 |
12645021482 ps |
| T773 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.4114402983 |
|
|
May 09 04:48:39 PM PDT 24 |
May 09 04:56:19 PM PDT 24 |
5284334994 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2438797464 |
|
|
May 09 04:10:05 PM PDT 24 |
May 09 05:40:13 PM PDT 24 |
47130517036 ps |
| T1170 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1071872658 |
|
|
May 09 04:18:49 PM PDT 24 |
May 09 04:24:54 PM PDT 24 |
6006057728 ps |
| T61 |
/workspace/coverage/default/0.chip_sw_alert_test.3358533192 |
|
|
May 09 04:09:36 PM PDT 24 |
May 09 04:14:37 PM PDT 24 |
2634311376 ps |
| T741 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3854962383 |
|
|
May 09 04:47:46 PM PDT 24 |
May 09 04:53:59 PM PDT 24 |
3455351120 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2415906004 |
|
|
May 09 04:22:53 PM PDT 24 |
May 09 04:35:46 PM PDT 24 |
5012028260 ps |
| T1172 |
/workspace/coverage/default/2.chip_sival_flash_info_access.100027309 |
|
|
May 09 04:38:00 PM PDT 24 |
May 09 04:44:13 PM PDT 24 |
3120489480 ps |
| T1173 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3944000502 |
|
|
May 09 04:09:33 PM PDT 24 |
May 09 04:14:05 PM PDT 24 |
3564148991 ps |
| T758 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1312768801 |
|
|
May 09 04:45:34 PM PDT 24 |
May 09 04:51:24 PM PDT 24 |
3862196268 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1693250527 |
|
|
May 09 04:09:04 PM PDT 24 |
May 09 04:19:23 PM PDT 24 |
7730109354 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4017075766 |
|
|
May 09 04:09:46 PM PDT 24 |
May 09 05:14:00 PM PDT 24 |
17542166936 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2578674559 |
|
|
May 09 04:38:17 PM PDT 24 |
May 09 04:43:57 PM PDT 24 |
2709427188 ps |
| T376 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2024236758 |
|
|
May 09 04:23:40 PM PDT 24 |
May 09 04:30:06 PM PDT 24 |
7198448836 ps |
| T1177 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1463435014 |
|
|
May 09 04:10:47 PM PDT 24 |
May 09 04:20:22 PM PDT 24 |
5653080624 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3661578607 |
|
|
May 09 04:39:14 PM PDT 24 |
May 09 04:41:02 PM PDT 24 |
2037784272 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2080145922 |
|
|
May 09 04:19:59 PM PDT 24 |
May 09 04:31:12 PM PDT 24 |
4514085752 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2481061669 |
|
|
May 09 04:09:55 PM PDT 24 |
May 09 04:14:24 PM PDT 24 |
2802701844 ps |
| T646 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1252986652 |
|
|
May 09 04:10:52 PM PDT 24 |
May 09 04:40:59 PM PDT 24 |
6913544760 ps |
| T798 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708453211 |
|
|
May 09 04:52:13 PM PDT 24 |
May 09 04:58:13 PM PDT 24 |
3241407464 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.536791109 |
|
|
May 09 04:41:22 PM PDT 24 |
May 09 05:02:10 PM PDT 24 |
9079060022 ps |
| T385 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2001285764 |
|
|
May 09 04:11:54 PM PDT 24 |
May 09 04:18:29 PM PDT 24 |
3579411700 ps |
| T794 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.497542145 |
|
|
May 09 04:46:27 PM PDT 24 |
May 09 04:52:08 PM PDT 24 |
4269031090 ps |
| T1182 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1459618642 |
|
|
May 09 04:19:44 PM PDT 24 |
May 09 04:22:38 PM PDT 24 |
2690354430 ps |
| T1183 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3033585157 |
|
|
May 09 04:43:31 PM PDT 24 |
May 09 05:06:58 PM PDT 24 |
13531021448 ps |
| T1184 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3596667113 |
|
|
May 09 04:17:57 PM PDT 24 |
May 09 04:22:43 PM PDT 24 |
2424693624 ps |
| T1185 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1287175122 |
|
|
May 09 04:43:40 PM PDT 24 |
May 09 05:05:06 PM PDT 24 |
8841937168 ps |
| T1186 |
/workspace/coverage/default/0.chip_tap_straps_dev.31837549 |
|
|
May 09 04:08:32 PM PDT 24 |
May 09 04:10:56 PM PDT 24 |
3339198246 ps |
| T687 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3671435044 |
|
|
May 09 04:40:52 PM PDT 24 |
May 09 04:44:19 PM PDT 24 |
2684316760 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2808711989 |
|
|
May 09 04:14:15 PM PDT 24 |
May 09 04:26:59 PM PDT 24 |
4734730568 ps |
| T792 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1243937264 |
|
|
May 09 04:43:48 PM PDT 24 |
May 09 04:49:57 PM PDT 24 |
3515102500 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.3541268049 |
|
|
May 09 04:18:30 PM PDT 24 |
May 09 04:21:50 PM PDT 24 |
2836450048 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.4136964834 |
|
|
May 09 04:11:33 PM PDT 24 |
May 09 07:22:21 PM PDT 24 |
64015643338 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.400667470 |
|
|
May 09 04:09:04 PM PDT 24 |
May 09 05:44:16 PM PDT 24 |
50501433183 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.4139629205 |
|
|
May 09 04:13:28 PM PDT 24 |
May 09 04:17:21 PM PDT 24 |
2417719166 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1683924372 |
|
|
May 09 04:20:30 PM PDT 24 |
May 09 04:28:17 PM PDT 24 |
7906019376 ps |
| T1191 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4021300100 |
|
|
May 09 04:13:09 PM PDT 24 |
May 09 04:22:45 PM PDT 24 |
7353276694 ps |
| T1192 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1141215837 |
|
|
May 09 04:42:18 PM PDT 24 |
May 09 04:51:49 PM PDT 24 |
6047825000 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.226535126 |
|
|
May 09 04:09:35 PM PDT 24 |
May 09 04:20:11 PM PDT 24 |
18632159202 ps |
| T1194 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3012182463 |
|
|
May 09 04:43:31 PM PDT 24 |
May 09 04:53:31 PM PDT 24 |
3773053180 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3592890806 |
|
|
May 09 04:20:40 PM PDT 24 |
May 09 04:25:02 PM PDT 24 |
2779231014 ps |
| T284 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.112479043 |
|
|
May 09 04:44:17 PM PDT 24 |
May 09 04:50:29 PM PDT 24 |
3686287058 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1933169545 |
|
|
May 09 04:10:15 PM PDT 24 |
May 09 04:23:25 PM PDT 24 |
6696623080 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3671673167 |
|
|
May 09 04:07:10 PM PDT 24 |
May 09 05:23:47 PM PDT 24 |
42558442380 ps |
| T1197 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3349143005 |
|
|
May 09 04:46:34 PM PDT 24 |
May 09 05:03:39 PM PDT 24 |
10844017620 ps |
| T746 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3051977959 |
|
|
May 09 04:38:08 PM PDT 24 |
May 09 04:49:50 PM PDT 24 |
5582126440 ps |
| T349 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2875937251 |
|
|
May 09 04:08:06 PM PDT 24 |
May 09 04:23:47 PM PDT 24 |
5091880424 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4186653189 |
|
|
May 09 04:18:44 PM PDT 24 |
May 09 04:27:33 PM PDT 24 |
3773203750 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2902370692 |
|
|
May 09 04:19:32 PM PDT 24 |
May 09 04:46:34 PM PDT 24 |
11833382493 ps |
| T756 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.461980124 |
|
|
May 09 04:40:46 PM PDT 24 |
May 09 04:48:07 PM PDT 24 |
4172374740 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3623042518 |
|
|
May 09 04:40:16 PM PDT 24 |
May 09 04:49:03 PM PDT 24 |
4331989312 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1779987797 |
|
|
May 09 04:20:49 PM PDT 24 |
May 09 05:08:15 PM PDT 24 |
17276238856 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.200795818 |
|
|
May 09 04:19:22 PM PDT 24 |
May 09 05:45:35 PM PDT 24 |
46520242590 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.639217598 |
|
|
May 09 04:38:40 PM PDT 24 |
May 09 04:48:46 PM PDT 24 |
4827686242 ps |
| T1202 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2758567397 |
|
|
May 09 04:43:17 PM PDT 24 |
May 09 04:55:36 PM PDT 24 |
4610729248 ps |
| T789 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1790707112 |
|
|
May 09 04:44:37 PM PDT 24 |
May 09 04:54:06 PM PDT 24 |
5855480640 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2940090131 |
|
|
May 09 04:08:41 PM PDT 24 |
May 09 04:16:29 PM PDT 24 |
7108414680 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2231785829 |
|
|
May 09 04:21:16 PM PDT 24 |
May 09 04:36:29 PM PDT 24 |
8698851138 ps |
| T1205 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1131861505 |
|
|
May 09 04:40:49 PM PDT 24 |
May 09 04:56:57 PM PDT 24 |
7205541020 ps |
| T1206 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.945221102 |
|
|
May 09 04:45:15 PM PDT 24 |
May 09 04:52:10 PM PDT 24 |
6886789361 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3430755420 |
|
|
May 09 04:18:43 PM PDT 24 |
May 09 04:21:22 PM PDT 24 |
2682616740 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3913086025 |
|
|
May 09 04:09:27 PM PDT 24 |
May 09 04:13:09 PM PDT 24 |
3260124510 ps |
| T185 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2867065493 |
|
|
May 09 04:09:43 PM PDT 24 |
May 09 04:19:54 PM PDT 24 |
4341294262 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2725082523 |
|
|
May 09 04:08:29 PM PDT 24 |
May 09 04:26:01 PM PDT 24 |
5761960505 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3410202379 |
|
|
May 09 04:24:07 PM PDT 24 |
May 09 04:42:21 PM PDT 24 |
12195797260 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.132649774 |
|
|
May 09 04:11:14 PM PDT 24 |
May 09 04:15:37 PM PDT 24 |
2714499952 ps |
| T1211 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3311588799 |
|
|
May 09 04:47:14 PM PDT 24 |
May 09 04:56:41 PM PDT 24 |
4836179260 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.716546313 |
|
|
May 09 04:14:30 PM PDT 24 |
May 09 04:48:29 PM PDT 24 |
8799549580 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3485656498 |
|
|
May 09 04:23:14 PM PDT 24 |
May 09 04:35:07 PM PDT 24 |
4689273834 ps |
| T785 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466785976 |
|
|
May 09 04:52:46 PM PDT 24 |
May 09 04:58:20 PM PDT 24 |
3243319024 ps |
| T1214 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051757136 |
|
|
May 09 04:49:35 PM PDT 24 |
May 09 04:56:26 PM PDT 24 |
4051792324 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.187722047 |
|
|
May 09 04:19:46 PM PDT 24 |
May 09 04:36:26 PM PDT 24 |
5155807232 ps |
| T1216 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2724244601 |
|
|
May 09 04:51:23 PM PDT 24 |
May 09 05:01:39 PM PDT 24 |
5049891504 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3832324435 |
|
|
May 09 04:08:10 PM PDT 24 |
May 09 04:18:22 PM PDT 24 |
4136289678 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.168578687 |
|
|
May 09 04:38:41 PM PDT 24 |
May 09 05:02:56 PM PDT 24 |
8635442846 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2430110417 |
|
|
May 09 04:38:02 PM PDT 24 |
May 09 04:44:43 PM PDT 24 |
5799108528 ps |
| T1220 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2887279225 |
|
|
May 09 04:40:57 PM PDT 24 |
May 09 04:50:29 PM PDT 24 |
6624687150 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3827193793 |
|
|
May 09 04:40:19 PM PDT 24 |
May 09 05:23:05 PM PDT 24 |
28775815374 ps |
| T774 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727713655 |
|
|
May 09 04:42:48 PM PDT 24 |
May 09 04:48:19 PM PDT 24 |
3717598312 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2883410477 |
|
|
May 09 04:36:15 PM PDT 24 |
May 09 04:41:35 PM PDT 24 |
2991210812 ps |
| T759 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1010455712 |
|
|
May 09 04:42:54 PM PDT 24 |
May 09 04:50:48 PM PDT 24 |
4204236544 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3570544960 |
|
|
May 09 04:13:40 PM PDT 24 |
May 09 04:18:49 PM PDT 24 |
2791757128 ps |
| T264 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4111244479 |
|
|
May 09 04:09:35 PM PDT 24 |
May 09 04:22:30 PM PDT 24 |
6050902282 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3545059776 |
|
|
May 09 04:19:29 PM PDT 24 |
May 09 04:25:29 PM PDT 24 |
3702319010 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.442890108 |
|
|
May 09 04:40:33 PM PDT 24 |
May 09 08:09:27 PM PDT 24 |
255712807208 ps |
| T377 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1057866744 |
|
|
May 09 04:10:59 PM PDT 24 |
May 09 04:33:57 PM PDT 24 |
22448569472 ps |
| T336 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3271738409 |
|
|
May 09 04:43:59 PM PDT 24 |
May 09 04:54:37 PM PDT 24 |
5848224116 ps |
| T787 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2411724947 |
|
|
May 09 04:42:57 PM PDT 24 |
May 09 04:50:37 PM PDT 24 |
3935803720 ps |
| T121 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.702087115 |
|
|
May 09 04:21:07 PM PDT 24 |
May 09 04:29:36 PM PDT 24 |
6520611086 ps |
| T1226 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2152805249 |
|
|
May 09 04:19:10 PM PDT 24 |
May 09 04:22:20 PM PDT 24 |
2931693848 ps |
| T754 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012506583 |
|
|
May 09 04:42:07 PM PDT 24 |
May 09 04:47:28 PM PDT 24 |
3753389440 ps |
| T75 |
/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2718119109 |
|
|
May 09 03:50:28 PM PDT 24 |
May 09 03:51:53 PM PDT 24 |
209209720 ps |
| T76 |
/workspace/coverage/cover_reg_top/97.xbar_same_source.3343587984 |
|
|
May 09 04:00:00 PM PDT 24 |
May 09 04:00:22 PM PDT 24 |
259007165 ps |
| T77 |
/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1145345688 |
|
|
May 09 03:53:43 PM PDT 24 |
May 09 03:57:05 PM PDT 24 |
1801352653 ps |
| T139 |
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1333775904 |
|
|
May 09 03:47:11 PM PDT 24 |
May 09 03:47:57 PM PDT 24 |
439698291 ps |
| T210 |
/workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3505144848 |
|
|
May 09 03:59:07 PM PDT 24 |
May 09 04:00:33 PM PDT 24 |
5016512356 ps |
| T410 |
/workspace/coverage/cover_reg_top/72.xbar_same_source.1058413959 |
|
|
May 09 03:56:07 PM PDT 24 |
May 09 03:56:27 PM PDT 24 |
445081026 ps |
| T413 |
/workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.4003581322 |
|
|
May 09 03:55:46 PM PDT 24 |
May 09 03:56:11 PM PDT 24 |
196160181 ps |
| T416 |
/workspace/coverage/cover_reg_top/20.xbar_stress_all.120115439 |
|
|
May 09 03:48:34 PM PDT 24 |
May 09 03:53:33 PM PDT 24 |
7561288141 ps |
| T411 |
/workspace/coverage/cover_reg_top/66.xbar_error_random.3795074232 |
|
|
May 09 03:55:25 PM PDT 24 |
May 09 03:55:56 PM PDT 24 |
363921121 ps |
| T500 |
/workspace/coverage/cover_reg_top/91.xbar_random.1411514778 |
|
|
May 09 03:59:10 PM PDT 24 |
May 09 03:59:41 PM PDT 24 |
770036683 ps |
| T412 |
/workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.4181847710 |
|
|
May 09 03:57:18 PM PDT 24 |
May 09 03:57:28 PM PDT 24 |
60166685 ps |
| T499 |
/workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1950493732 |
|
|
May 09 03:54:22 PM PDT 24 |
May 09 03:54:52 PM PDT 24 |
603777907 ps |
| T498 |
/workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3291459339 |
|
|
May 09 03:59:02 PM PDT 24 |
May 09 03:59:46 PM PDT 24 |
433456313 ps |
| T502 |
/workspace/coverage/cover_reg_top/14.xbar_error_random.1476874899 |
|
|
May 09 03:47:21 PM PDT 24 |
May 09 03:47:46 PM PDT 24 |
219494738 ps |
| T392 |
/workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3683347966 |
|
|
May 09 03:55:44 PM PDT 24 |
May 09 03:56:26 PM PDT 24 |
398617228 ps |
| T504 |
/workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2712242901 |
|
|
May 09 03:53:20 PM PDT 24 |
May 09 03:54:59 PM PDT 24 |
8607848973 ps |
| T395 |
/workspace/coverage/cover_reg_top/90.xbar_access_same_device.2355467059 |
|
|
May 09 03:58:48 PM PDT 24 |
May 09 04:01:09 PM PDT 24 |
3202285933 ps |
| T507 |
/workspace/coverage/cover_reg_top/68.xbar_smoke.3099498896 |
|
|
May 09 03:55:40 PM PDT 24 |
May 09 03:55:51 PM PDT 24 |
161862663 ps |
| T510 |
/workspace/coverage/cover_reg_top/77.xbar_smoke.4213658784 |
|
|
May 09 03:57:02 PM PDT 24 |
May 09 03:57:13 PM PDT 24 |
190257972 ps |
| T496 |
/workspace/coverage/cover_reg_top/80.xbar_error_random.1168516568 |
|
|
May 09 03:57:17 PM PDT 24 |
May 09 03:57:40 PM PDT 24 |
653969571 ps |
| T506 |
/workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2465872713 |
|
|
May 09 03:51:50 PM PDT 24 |
May 09 03:53:29 PM PDT 24 |
5620495883 ps |
| T508 |
/workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4039390554 |
|
|
May 09 03:46:51 PM PDT 24 |
May 09 03:48:02 PM PDT 24 |
4001650046 ps |
| T381 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all.2020940039 |
|
|
May 09 03:46:52 PM PDT 24 |
May 09 03:50:08 PM PDT 24 |
2195726648 ps |
| T605 |
/workspace/coverage/cover_reg_top/82.xbar_stress_all.2236556025 |
|
|
May 09 03:57:41 PM PDT 24 |
May 09 03:58:52 PM PDT 24 |
1833222954 ps |
| T382 |
/workspace/coverage/cover_reg_top/32.xbar_stress_all.12827769 |
|
|
May 09 03:50:26 PM PDT 24 |
May 09 03:57:40 PM PDT 24 |
11279200633 ps |
| T415 |
/workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3010927919 |
|
|
May 09 03:51:05 PM PDT 24 |
May 09 04:10:28 PM PDT 24 |
98232896920 ps |
| T819 |
/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1835537559 |
|
|
May 09 03:54:32 PM PDT 24 |
May 09 04:05:17 PM PDT 24 |
38344947071 ps |
| T501 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2175259640 |
|
|
May 09 03:54:06 PM PDT 24 |
May 09 03:57:25 PM PDT 24 |
543567096 ps |
| T503 |
/workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1252707189 |
|
|
May 09 03:54:31 PM PDT 24 |
May 09 04:15:12 PM PDT 24 |
67067021431 ps |
| T703 |
/workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3611452964 |
|
|
May 09 03:52:48 PM PDT 24 |
May 09 03:53:13 PM PDT 24 |
208483759 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.112190963 |
|
|
May 09 03:46:31 PM PDT 24 |
May 09 03:46:46 PM PDT 24 |
282585619 ps |
| T619 |
/workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1890666630 |
|
|
May 09 03:58:44 PM PDT 24 |
May 09 03:59:59 PM PDT 24 |
3766533088 ps |
| T505 |
/workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3615058733 |
|
|
May 09 03:56:18 PM PDT 24 |
May 09 03:56:41 PM PDT 24 |
182453265 ps |
| T537 |
/workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3079075829 |
|
|
May 09 03:59:02 PM PDT 24 |
May 09 03:59:13 PM PDT 24 |
43861778 ps |
| T526 |
/workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2086698467 |
|
|
May 09 03:57:26 PM PDT 24 |
May 09 03:57:33 PM PDT 24 |
44456609 ps |
| T489 |
/workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3886040945 |
|
|
May 09 03:51:23 PM PDT 24 |
May 09 03:52:07 PM PDT 24 |
509269941 ps |
| T422 |
/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1932009574 |
|
|
May 09 03:59:36 PM PDT 24 |
May 09 04:34:21 PM PDT 24 |
106148846264 ps |
| T509 |
/workspace/coverage/cover_reg_top/92.xbar_random.403477198 |
|
|
May 09 03:59:13 PM PDT 24 |
May 09 03:59:28 PM PDT 24 |
116495727 ps |
| T808 |
/workspace/coverage/cover_reg_top/30.xbar_access_same_device.192047575 |
|
|
May 09 03:50:13 PM PDT 24 |
May 09 03:50:43 PM PDT 24 |
388443010 ps |
| T609 |
/workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3836280482 |
|
|
May 09 03:49:57 PM PDT 24 |
May 09 03:54:59 PM PDT 24 |
16861054736 ps |
| T523 |
/workspace/coverage/cover_reg_top/44.xbar_smoke.2378274670 |
|
|
May 09 03:52:02 PM PDT 24 |
May 09 03:52:17 PM PDT 24 |
216882499 ps |
| T603 |
/workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3242850441 |
|
|
May 09 03:52:12 PM PDT 24 |
May 09 03:53:35 PM PDT 24 |
4480729754 ps |
| T823 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2019773631 |
|
|
May 09 03:46:48 PM PDT 24 |
May 09 03:48:56 PM PDT 24 |
586217960 ps |
| T497 |
/workspace/coverage/cover_reg_top/24.chip_tl_errors.3980330041 |
|
|
May 09 03:48:49 PM PDT 24 |
May 09 03:51:52 PM PDT 24 |
3099888800 ps |
| T827 |
/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3469209065 |
|
|
May 09 03:57:20 PM PDT 24 |
May 09 03:57:57 PM PDT 24 |
115819578 ps |
| T391 |
/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3022841637 |
|
|
May 09 03:54:36 PM PDT 24 |
May 09 04:08:33 PM PDT 24 |
81688919792 ps |
| T394 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.106942024 |
|
|
May 09 03:46:56 PM PDT 24 |
May 09 03:49:00 PM PDT 24 |
2860196250 ps |
| T539 |
/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3677049722 |
|
|
May 09 03:51:35 PM PDT 24 |
May 09 03:51:55 PM PDT 24 |
383925639 ps |
| T1228 |
/workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.1761702560 |
|
|
May 09 03:53:42 PM PDT 24 |
May 09 03:54:59 PM PDT 24 |
7523605006 ps |
| T551 |
/workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.2476525289 |
|
|
May 09 03:56:08 PM PDT 24 |
May 09 03:57:01 PM PDT 24 |
608468590 ps |
| T651 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1893789119 |
|
|
May 09 03:55:33 PM PDT 24 |
May 09 03:58:38 PM PDT 24 |
2760728192 ps |
| T371 |
/workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.741184474 |
|
|
May 09 03:59:26 PM PDT 24 |
May 09 03:59:36 PM PDT 24 |
48357070 ps |
| T1229 |
/workspace/coverage/cover_reg_top/31.xbar_smoke.1798668823 |
|
|
May 09 03:50:14 PM PDT 24 |
May 09 03:50:22 PM PDT 24 |
41030585 ps |
| T516 |
/workspace/coverage/cover_reg_top/22.chip_tl_errors.2601697910 |
|
|
May 09 03:48:38 PM PDT 24 |
May 09 03:51:05 PM PDT 24 |
2735482216 ps |
| T1230 |
/workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1983535906 |
|
|
May 09 03:58:47 PM PDT 24 |
May 09 03:58:56 PM PDT 24 |
53275294 ps |
| T636 |
/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.4205470124 |
|
|
May 09 03:52:25 PM PDT 24 |
May 09 03:54:16 PM PDT 24 |
297696341 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.xbar_error_random.2114113575 |
|
|
May 09 03:46:40 PM PDT 24 |
May 09 03:47:20 PM PDT 24 |
486390062 ps |
| T372 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all.4132564833 |
|
|
May 09 03:48:17 PM PDT 24 |
May 09 03:52:51 PM PDT 24 |
3352562552 ps |
| T574 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.1502391446 |
|
|
May 09 03:46:49 PM PDT 24 |
May 09 03:47:28 PM PDT 24 |
428446711 ps |
| T454 |
/workspace/coverage/cover_reg_top/70.xbar_stress_all.2780194009 |
|
|
May 09 03:55:54 PM PDT 24 |
May 09 03:57:23 PM PDT 24 |
1239236515 ps |
| T828 |
/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1722466076 |
|
|
May 09 03:51:17 PM PDT 24 |
May 09 03:57:38 PM PDT 24 |
21559376305 ps |
| T480 |
/workspace/coverage/cover_reg_top/19.xbar_access_same_device.2032701224 |
|
|
May 09 03:48:18 PM PDT 24 |
May 09 03:50:29 PM PDT 24 |
2864379726 ps |
| T393 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.415147076 |
|
|
May 09 03:46:35 PM PDT 24 |
May 09 03:56:02 PM PDT 24 |
11364005747 ps |
| T814 |
/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1055585005 |
|
|
May 09 03:57:29 PM PDT 24 |
May 09 04:37:46 PM PDT 24 |
123976363002 ps |
| T575 |
/workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2742186217 |
|
|
May 09 03:51:39 PM PDT 24 |
May 09 03:51:49 PM PDT 24 |
43894940 ps |
| T430 |
/workspace/coverage/cover_reg_top/29.xbar_stress_all.871658181 |
|
|
May 09 03:50:00 PM PDT 24 |
May 09 03:51:37 PM PDT 24 |
992882438 ps |
| T652 |
/workspace/coverage/cover_reg_top/20.xbar_error_random.2491589688 |
|
|
May 09 03:48:29 PM PDT 24 |
May 09 03:49:11 PM PDT 24 |
457301947 ps |
| T1232 |
/workspace/coverage/cover_reg_top/87.xbar_error_random.1289925027 |
|
|
May 09 03:58:34 PM PDT 24 |
May 09 03:58:49 PM PDT 24 |
268812420 ps |
| T606 |
/workspace/coverage/cover_reg_top/38.xbar_same_source.4273079120 |
|
|
May 09 03:51:23 PM PDT 24 |
May 09 03:51:50 PM PDT 24 |
686615393 ps |
| T653 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1318237662 |
|
|
May 09 03:46:36 PM PDT 24 |
May 09 03:47:10 PM PDT 24 |
81430181 ps |
| T1233 |
/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.3739405253 |
|
|
May 09 03:51:29 PM PDT 24 |
May 09 03:52:52 PM PDT 24 |
8314813229 ps |
| T802 |
/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3412945759 |
|
|
May 09 03:51:04 PM PDT 24 |
May 09 03:53:37 PM PDT 24 |
1882833962 ps |
| T557 |
/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2441114123 |
|
|
May 09 03:53:11 PM PDT 24 |
May 09 04:01:15 PM PDT 24 |
25935186806 ps |
| T1234 |
/workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3432217897 |
|
|
May 09 03:46:20 PM PDT 24 |
May 09 03:46:28 PM PDT 24 |
46286637 ps |
| T1235 |
/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3033012434 |
|
|
May 09 03:52:01 PM PDT 24 |
May 09 03:53:18 PM PDT 24 |
3972293269 ps |
| T596 |
/workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.2141152616 |
|
|
May 09 04:00:00 PM PDT 24 |
May 09 04:00:09 PM PDT 24 |
41037755 ps |
| T1236 |
/workspace/coverage/cover_reg_top/60.xbar_random_large_delays.1988108038 |
|
|
May 09 03:54:30 PM PDT 24 |
May 09 03:55:57 PM PDT 24 |
7264449626 ps |
| T417 |
/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.704431782 |
|
|
May 09 03:54:52 PM PDT 24 |
May 09 04:43:55 PM PDT 24 |
164557596948 ps |
| T834 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1828207862 |
|
|
May 09 03:46:33 PM PDT 24 |
May 09 03:47:26 PM PDT 24 |
599679805 ps |
| T697 |
/workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2842983011 |
|
|
May 09 03:51:55 PM PDT 24 |
May 09 03:52:04 PM PDT 24 |
52787747 ps |
| T455 |
/workspace/coverage/cover_reg_top/60.xbar_stress_all.1826742299 |
|
|
May 09 03:54:36 PM PDT 24 |
May 09 04:00:18 PM PDT 24 |
10260767127 ps |
| T1237 |
/workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.464433694 |
|
|
May 09 03:50:01 PM PDT 24 |
May 09 03:50:40 PM PDT 24 |
967326929 ps |
| T1238 |
/workspace/coverage/cover_reg_top/45.xbar_error_random.1722781964 |
|
|
May 09 03:52:14 PM PDT 24 |
May 09 03:52:34 PM PDT 24 |
156882748 ps |
| T445 |
/workspace/coverage/cover_reg_top/2.xbar_access_same_device.3594838926 |
|
|
May 09 03:46:17 PM PDT 24 |
May 09 03:47:23 PM PDT 24 |
889371395 ps |
| T565 |
/workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.635571117 |
|
|
May 09 03:54:10 PM PDT 24 |
May 09 03:54:37 PM PDT 24 |
501915448 ps |
| T616 |
/workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3997121246 |
|
|
May 09 03:48:35 PM PDT 24 |
May 09 03:49:57 PM PDT 24 |
7414790790 ps |
| T418 |
/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.176747718 |
|
|
May 09 03:53:22 PM PDT 24 |
May 09 04:16:25 PM PDT 24 |
75167372659 ps |
| T803 |
/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.731969652 |
|
|
May 09 03:59:31 PM PDT 24 |
May 09 04:37:34 PM PDT 24 |
129780567595 ps |
| T807 |
/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3371690738 |
|
|
May 09 03:52:05 PM PDT 24 |
May 09 04:17:58 PM PDT 24 |
84313276534 ps |
| T442 |
/workspace/coverage/cover_reg_top/80.xbar_random.1798507390 |
|
|
May 09 03:57:18 PM PDT 24 |
May 09 03:58:27 PM PDT 24 |
1827008123 ps |
| T1239 |
/workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3746519631 |
|
|
May 09 03:52:38 PM PDT 24 |
May 09 03:53:02 PM PDT 24 |
490160273 ps |
| T1240 |
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1372632463 |
|
|
May 09 03:47:50 PM PDT 24 |
May 09 03:47:58 PM PDT 24 |
41162624 ps |
| T1241 |
/workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2464689856 |
|
|
May 09 03:53:11 PM PDT 24 |
May 09 03:53:20 PM PDT 24 |
41032438 ps |
| T658 |
/workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1438660630 |
|
|
May 09 03:49:47 PM PDT 24 |
May 09 03:50:38 PM PDT 24 |
1159956185 ps |
| T571 |
/workspace/coverage/cover_reg_top/2.xbar_same_source.2862810942 |
|
|
May 09 03:46:19 PM PDT 24 |
May 09 03:47:04 PM PDT 24 |
1421073603 ps |
| T1242 |
/workspace/coverage/cover_reg_top/78.xbar_error_random.2847105360 |
|
|
May 09 03:57:07 PM PDT 24 |
May 09 03:58:11 PM PDT 24 |
1673951665 ps |
| T547 |
/workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3103879465 |
|
|
May 09 03:46:36 PM PDT 24 |
May 09 03:58:49 PM PDT 24 |
64100846519 ps |
| T450 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all.3755620732 |
|
|
May 09 03:47:52 PM PDT 24 |
May 09 03:53:36 PM PDT 24 |
8179891026 ps |
| T1243 |
/workspace/coverage/cover_reg_top/59.xbar_smoke.344838115 |
|
|
May 09 03:54:05 PM PDT 24 |
May 09 03:54:15 PM PDT 24 |
58022414 ps |
| T579 |
/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2515346568 |
|
|
May 09 04:00:04 PM PDT 24 |
May 09 04:07:54 PM PDT 24 |
37228287316 ps |
| T830 |
/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3478259592 |
|
|
May 09 03:48:52 PM PDT 24 |
May 09 03:49:11 PM PDT 24 |
363977267 ps |
| T476 |
/workspace/coverage/cover_reg_top/76.xbar_stress_all.2909098351 |
|
|
May 09 03:56:54 PM PDT 24 |
May 09 04:01:14 PM PDT 24 |
7080230592 ps |
| T1244 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4163229156 |
|
|
May 09 03:46:51 PM PDT 24 |
May 09 03:48:04 PM PDT 24 |
6560749363 ps |
| T452 |
/workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2354579312 |
|
|
May 09 03:55:20 PM PDT 24 |
May 09 04:01:58 PM PDT 24 |
39316794565 ps |
| T1245 |
/workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3857867414 |
|
|
May 09 03:46:44 PM PDT 24 |
May 09 03:48:29 PM PDT 24 |
10620442267 ps |
| T433 |
/workspace/coverage/cover_reg_top/53.xbar_stress_all.2870099700 |
|
|
May 09 03:53:21 PM PDT 24 |
May 09 03:53:51 PM PDT 24 |
340143969 ps |
| T1246 |
/workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.72679511 |
|
|
May 09 03:56:35 PM PDT 24 |
May 09 03:58:07 PM PDT 24 |
5264463112 ps |
| T544 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1755861445 |
|
|
May 09 03:54:06 PM PDT 24 |
May 09 03:59:41 PM PDT 24 |
2357406851 ps |
| T817 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3105599017 |
|
|
May 09 03:47:21 PM PDT 24 |
May 09 03:59:08 PM PDT 24 |
43651680140 ps |
| T597 |
/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3860417270 |
|
|
May 09 03:54:41 PM PDT 24 |
May 09 03:57:52 PM PDT 24 |
2427118154 ps |
| T613 |
/workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3421680373 |
|
|
May 09 03:55:45 PM PDT 24 |
May 09 03:57:22 PM PDT 24 |
8314142192 ps |
| T640 |
/workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3313446203 |
|
|
May 09 03:51:17 PM PDT 24 |
May 09 03:52:08 PM PDT 24 |
1119943735 ps |
| T1247 |
/workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3367309098 |
|
|
May 09 03:48:31 PM PDT 24 |
May 09 03:48:53 PM PDT 24 |
377528494 ps |
| T473 |
/workspace/coverage/cover_reg_top/93.xbar_same_source.1787741246 |
|
|
May 09 03:59:23 PM PDT 24 |
May 09 03:59:48 PM PDT 24 |
283156263 ps |
| T1248 |
/workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2131690347 |
|
|
May 09 03:46:35 PM PDT 24 |
May 09 03:48:02 PM PDT 24 |
8205164323 ps |
| T836 |
/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.4184138288 |
|
|
May 09 04:00:29 PM PDT 24 |
May 09 04:02:15 PM PDT 24 |
781522169 ps |
| T815 |
/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1020693474 |
|
|
May 09 03:46:52 PM PDT 24 |
May 09 04:20:00 PM PDT 24 |
115158862695 ps |
| T660 |
/workspace/coverage/cover_reg_top/9.xbar_error_random.1279402686 |
|
|
May 09 03:46:48 PM PDT 24 |
May 09 03:47:21 PM PDT 24 |
353262408 ps |
| T804 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1697451759 |
|
|
May 09 03:46:50 PM PDT 24 |
May 09 03:49:02 PM PDT 24 |
1573077331 ps |
| T816 |
/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1625421021 |
|
|
May 09 03:51:38 PM PDT 24 |
May 09 04:13:39 PM PDT 24 |
75368923254 ps |
| T805 |
/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.4135757263 |
|
|
May 09 03:54:11 PM PDT 24 |
May 09 04:01:28 PM PDT 24 |
25319715664 ps |
| T420 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all.886307689 |
|
|
May 09 03:55:31 PM PDT 24 |
May 09 04:04:40 PM PDT 24 |
16784979614 ps |
| T607 |
/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2835505242 |
|
|
May 09 03:55:23 PM PDT 24 |
May 09 03:57:12 PM PDT 24 |
324037842 ps |
| T704 |
/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2214648004 |
|
|
May 09 03:50:00 PM PDT 24 |
May 09 03:52:00 PM PDT 24 |
478065708 ps |
| T1249 |
/workspace/coverage/cover_reg_top/49.xbar_smoke.2062641400 |
|
|
May 09 03:52:38 PM PDT 24 |
May 09 03:52:47 PM PDT 24 |
56569603 ps |
| T383 |
/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1287359811 |
|
|
May 09 03:53:56 PM PDT 24 |
May 09 04:28:09 PM PDT 24 |
108046219558 ps |
| T421 |
/workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3276641178 |
|
|
May 09 03:49:52 PM PDT 24 |
May 09 03:50:14 PM PDT 24 |
232036506 ps |
| T1250 |
/workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3834806651 |
|
|
May 09 03:49:35 PM PDT 24 |
May 09 03:50:58 PM PDT 24 |
4594491356 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.203026360 |
|
|
May 09 03:46:21 PM PDT 24 |
May 09 03:53:22 PM PDT 24 |
8279284640 ps |
| T328 |
/workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2980311847 |
|
|
May 09 03:46:44 PM PDT 24 |
May 09 05:07:53 PM PDT 24 |
35057503626 ps |