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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.37 93.88 95.58 94.49 97.38 99.54


Total test records in report: 2783
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T237 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1456505496 May 12 03:48:16 PM PDT 24 May 12 03:58:53 PM PDT 24 4734995750 ps
T238 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3622264759 May 12 03:48:19 PM PDT 24 May 12 03:56:30 PM PDT 24 3620132408 ps
T239 /workspace/coverage/default/3.chip_sw_all_escalation_resets.4281428943 May 12 03:41:18 PM PDT 24 May 12 03:52:53 PM PDT 24 4300688856 ps
T240 /workspace/coverage/default/86.chip_sw_all_escalation_resets.197109594 May 12 03:51:59 PM PDT 24 May 12 04:03:52 PM PDT 24 4623057920 ps
T241 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2050744941 May 12 03:18:43 PM PDT 24 May 12 03:48:27 PM PDT 24 7348435392 ps
T242 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3557487295 May 12 03:32:45 PM PDT 24 May 12 03:45:00 PM PDT 24 4123837364 ps
T243 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.738729067 May 12 03:45:23 PM PDT 24 May 12 03:51:44 PM PDT 24 3413790812 ps
T244 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3873692170 May 12 03:34:17 PM PDT 24 May 12 03:44:39 PM PDT 24 18552683000 ps
T839 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3475549506 May 12 03:18:45 PM PDT 24 May 12 03:28:03 PM PDT 24 4407087981 ps
T840 /workspace/coverage/default/1.chip_sw_example_manufacturer.3688598326 May 12 03:21:00 PM PDT 24 May 12 03:24:40 PM PDT 24 2795080550 ps
T364 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1722860446 May 12 03:15:23 PM PDT 24 May 12 03:36:05 PM PDT 24 5570076332 ps
T694 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444290721 May 12 03:49:58 PM PDT 24 May 12 03:56:58 PM PDT 24 4035945270 ps
T841 /workspace/coverage/default/27.chip_sw_all_escalation_resets.740566857 May 12 03:45:43 PM PDT 24 May 12 03:58:23 PM PDT 24 4547108796 ps
T662 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1872142277 May 12 03:52:11 PM PDT 24 May 12 04:01:55 PM PDT 24 5299161856 ps
T277 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1081940436 May 12 03:32:15 PM PDT 24 May 12 03:55:34 PM PDT 24 7205825340 ps
T842 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.59974812 May 12 03:15:36 PM PDT 24 May 12 03:20:42 PM PDT 24 2956235916 ps
T65 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1518299533 May 12 03:17:40 PM PDT 24 May 12 03:23:47 PM PDT 24 3607725400 ps
T245 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2900412365 May 12 03:33:41 PM PDT 24 May 12 03:39:48 PM PDT 24 3368609394 ps
T73 /workspace/coverage/default/0.chip_jtag_csr_rw.2237608129 May 12 03:06:25 PM PDT 24 May 12 03:24:59 PM PDT 24 10402141202 ps
T843 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2871248881 May 12 03:24:59 PM PDT 24 May 12 03:33:21 PM PDT 24 7154120124 ps
T208 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3136356509 May 12 03:13:56 PM PDT 24 May 12 03:34:35 PM PDT 24 6700316088 ps
T844 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1071884613 May 12 03:45:41 PM PDT 24 May 12 03:56:03 PM PDT 24 5471215512 ps
T125 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2012131217 May 12 03:14:27 PM PDT 24 May 12 03:25:12 PM PDT 24 4790432816 ps
T845 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1459216137 May 12 03:29:11 PM PDT 24 May 12 03:32:33 PM PDT 24 2144182439 ps
T312 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.241366235 May 12 03:13:06 PM PDT 24 May 12 03:21:16 PM PDT 24 4335862020 ps
T61 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2265228162 May 12 03:28:25 PM PDT 24 May 12 03:34:03 PM PDT 24 4540390560 ps
T846 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2956897033 May 12 03:17:05 PM PDT 24 May 12 03:23:29 PM PDT 24 3426048030 ps
T847 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1491467646 May 12 03:15:23 PM PDT 24 May 12 03:36:54 PM PDT 24 11738078909 ps
T172 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3879782982 May 12 03:26:34 PM PDT 24 May 12 03:36:11 PM PDT 24 5743930576 ps
T654 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1260367864 May 12 03:45:15 PM PDT 24 May 12 03:52:16 PM PDT 24 3516426768 ps
T164 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.98409586 May 12 03:37:17 PM PDT 24 May 12 03:39:28 PM PDT 24 2828227958 ps
T848 /workspace/coverage/default/0.chip_sw_aes_entropy.3139543541 May 12 03:16:02 PM PDT 24 May 12 03:19:01 PM PDT 24 2771794056 ps
T849 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2171439932 May 12 03:30:07 PM PDT 24 May 12 03:49:06 PM PDT 24 5089431580 ps
T850 /workspace/coverage/default/1.chip_tap_straps_prod.3010009608 May 12 03:28:54 PM PDT 24 May 12 03:31:45 PM PDT 24 2778421364 ps
T17 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2687905639 May 12 03:12:48 PM PDT 24 May 12 05:04:17 PM PDT 24 30844934276 ps
T851 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2777831963 May 12 03:31:34 PM PDT 24 May 12 03:36:42 PM PDT 24 2824257102 ps
T852 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1553667240 May 12 03:37:32 PM PDT 24 May 12 03:43:35 PM PDT 24 3609348752 ps
T853 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1831790205 May 12 03:20:32 PM PDT 24 May 12 06:31:02 PM PDT 24 65118520318 ps
T683 /workspace/coverage/default/12.chip_sw_all_escalation_resets.706915977 May 12 03:43:58 PM PDT 24 May 12 03:54:33 PM PDT 24 5562004592 ps
T854 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3782428394 May 12 03:13:27 PM PDT 24 May 12 04:28:52 PM PDT 24 18876492918 ps
T735 /workspace/coverage/default/94.chip_sw_all_escalation_resets.1839437052 May 12 03:50:14 PM PDT 24 May 12 03:59:14 PM PDT 24 5127963108 ps
T855 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3832177820 May 12 03:23:55 PM PDT 24 May 12 03:27:43 PM PDT 24 2794108476 ps
T669 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922184270 May 12 03:47:33 PM PDT 24 May 12 03:54:39 PM PDT 24 4423440980 ps
T289 /workspace/coverage/default/1.chip_plic_all_irqs_20.1379396365 May 12 03:31:55 PM PDT 24 May 12 03:44:18 PM PDT 24 4230629086 ps
T411 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1478318837 May 12 03:14:15 PM PDT 24 May 12 03:30:48 PM PDT 24 5306862790 ps
T856 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3989116586 May 12 03:32:45 PM PDT 24 May 12 04:36:36 PM PDT 24 18508924236 ps
T663 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3240109139 May 12 03:45:57 PM PDT 24 May 12 03:54:08 PM PDT 24 3703194508 ps
T42 /workspace/coverage/default/2.rom_e2e_smoke.3947229676 May 12 03:45:46 PM PDT 24 May 12 04:54:53 PM PDT 24 16611024856 ps
T193 /workspace/coverage/default/1.rom_keymgr_functest.3182934819 May 12 03:31:04 PM PDT 24 May 12 03:42:35 PM PDT 24 5802618788 ps
T857 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1849983749 May 12 03:13:29 PM PDT 24 May 12 03:21:20 PM PDT 24 4210863744 ps
T858 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1996849224 May 12 03:28:05 PM PDT 24 May 12 03:36:57 PM PDT 24 6374523310 ps
T18 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3601354657 May 12 03:38:15 PM PDT 24 May 12 04:11:25 PM PDT 24 24415396634 ps
T859 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2442286959 May 12 03:37:29 PM PDT 24 May 12 03:43:01 PM PDT 24 2783965000 ps
T74 /workspace/coverage/default/2.chip_jtag_mem_access.3955011039 May 12 03:30:05 PM PDT 24 May 12 03:58:12 PM PDT 24 13793089700 ps
T290 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3315622624 May 12 03:32:53 PM PDT 24 May 12 03:46:20 PM PDT 24 4915683190 ps
T166 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1746359676 May 12 03:38:50 PM PDT 24 May 12 03:52:20 PM PDT 24 4943639822 ps
T860 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3176692709 May 12 03:27:05 PM PDT 24 May 12 03:32:32 PM PDT 24 2831833960 ps
T273 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1301899889 May 12 03:24:33 PM PDT 24 May 12 03:35:27 PM PDT 24 4478244078 ps
T861 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2596826553 May 12 03:45:35 PM PDT 24 May 12 03:54:13 PM PDT 24 4536296112 ps
T366 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1180770500 May 12 03:41:23 PM PDT 24 May 12 03:46:48 PM PDT 24 5508296912 ps
T656 /workspace/coverage/default/60.chip_sw_all_escalation_resets.116575986 May 12 03:50:35 PM PDT 24 May 12 04:00:34 PM PDT 24 4721282384 ps
T862 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3665447757 May 12 03:41:14 PM PDT 24 May 12 03:52:42 PM PDT 24 4355317178 ps
T863 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.962097852 May 12 03:33:54 PM PDT 24 May 12 03:47:25 PM PDT 24 6264710122 ps
T864 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.270374018 May 12 03:33:53 PM PDT 24 May 12 03:41:46 PM PDT 24 6110558998 ps
T865 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1798888659 May 12 03:39:54 PM PDT 24 May 12 03:49:37 PM PDT 24 3379441432 ps
T162 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.94996037 May 12 03:32:28 PM PDT 24 May 12 04:59:13 PM PDT 24 50012464555 ps
T866 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.423665871 May 12 03:40:39 PM PDT 24 May 12 03:48:01 PM PDT 24 4195999557 ps
T652 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.965602872 May 12 03:52:46 PM PDT 24 May 12 03:58:31 PM PDT 24 3411988750 ps
T867 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.138685800 May 12 03:15:21 PM PDT 24 May 12 03:26:30 PM PDT 24 5580421558 ps
T868 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.42855325 May 12 03:36:20 PM PDT 24 May 12 03:42:17 PM PDT 24 2935871715 ps
T736 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3334593239 May 12 03:52:13 PM PDT 24 May 12 04:03:06 PM PDT 24 5443878730 ps
T687 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1179025529 May 12 03:43:38 PM PDT 24 May 12 03:51:10 PM PDT 24 4124513192 ps
T869 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.363664765 May 12 03:36:30 PM PDT 24 May 12 03:58:14 PM PDT 24 10321684562 ps
T82 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1122771337 May 12 03:39:58 PM PDT 24 May 12 03:43:12 PM PDT 24 2796877262 ps
T713 /workspace/coverage/default/72.chip_sw_all_escalation_resets.4005397398 May 12 03:48:53 PM PDT 24 May 12 03:58:55 PM PDT 24 5331489496 ps
T870 /workspace/coverage/default/0.chip_sw_example_flash.4180308765 May 12 03:15:41 PM PDT 24 May 12 03:19:22 PM PDT 24 2723348522 ps
T871 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4166689999 May 12 03:20:34 PM PDT 24 May 12 04:08:14 PM PDT 24 25250424167 ps
T872 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3743520916 May 12 03:20:37 PM PDT 24 May 12 03:23:58 PM PDT 24 2455967592 ps
T873 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2260646014 May 12 03:12:14 PM PDT 24 May 12 03:16:54 PM PDT 24 3665527664 ps
T874 /workspace/coverage/default/0.chip_tap_straps_prod.1991871865 May 12 03:18:00 PM PDT 24 May 12 03:27:51 PM PDT 24 7170772682 ps
T875 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.294283029 May 12 03:14:13 PM PDT 24 May 12 03:30:35 PM PDT 24 5058808636 ps
T311 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3603290204 May 12 03:14:27 PM PDT 24 May 12 03:24:00 PM PDT 24 4236065880 ps
T708 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1338897390 May 12 03:50:49 PM PDT 24 May 12 04:00:06 PM PDT 24 4691596310 ps
T876 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2359131315 May 12 03:47:12 PM PDT 24 May 12 03:52:54 PM PDT 24 3051985212 ps
T227 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2404894764 May 12 03:33:55 PM PDT 24 May 12 03:45:06 PM PDT 24 5003625976 ps
T712 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3607107773 May 12 03:36:11 PM PDT 24 May 12 03:44:11 PM PDT 24 3789226656 ps
T688 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838037368 May 12 03:49:39 PM PDT 24 May 12 03:56:57 PM PDT 24 4104220060 ps
T696 /workspace/coverage/default/88.chip_sw_all_escalation_resets.800087294 May 12 03:50:21 PM PDT 24 May 12 03:58:35 PM PDT 24 5109934192 ps
T123 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.881759482 May 12 03:16:38 PM PDT 24 May 12 03:27:31 PM PDT 24 6720331528 ps
T877 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3786545859 May 12 03:25:50 PM PDT 24 May 12 03:31:24 PM PDT 24 3656272636 ps
T231 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1048962741 May 12 03:20:13 PM PDT 24 May 12 03:21:55 PM PDT 24 1847721934 ps
T189 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3915276125 May 12 03:22:36 PM PDT 24 May 12 03:40:42 PM PDT 24 7356087750 ps
T188 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2536393646 May 12 03:32:46 PM PDT 24 May 12 03:53:27 PM PDT 24 7911908998 ps
T878 /workspace/coverage/default/1.chip_sw_aes_enc.3766962246 May 12 03:25:25 PM PDT 24 May 12 03:29:15 PM PDT 24 2199133452 ps
T22 /workspace/coverage/default/0.chip_sw_usbdev_config_host.4270192889 May 12 03:13:39 PM PDT 24 May 12 03:47:38 PM PDT 24 8154626440 ps
T879 /workspace/coverage/default/0.chip_sw_otbn_randomness.2202464888 May 12 03:15:28 PM PDT 24 May 12 03:33:20 PM PDT 24 5837666568 ps
T880 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2101149689 May 12 03:22:45 PM PDT 24 May 12 03:38:31 PM PDT 24 8275172984 ps
T881 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3628445589 May 12 03:17:04 PM PDT 24 May 12 03:35:16 PM PDT 24 5659970552 ps
T882 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1106350401 May 12 03:21:11 PM PDT 24 May 12 03:30:43 PM PDT 24 4042723412 ps
T650 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.536221567 May 12 03:47:04 PM PDT 24 May 12 03:53:41 PM PDT 24 3455398920 ps
T883 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2779773981 May 12 03:43:07 PM PDT 24 May 12 03:48:06 PM PDT 24 2624077902 ps
T884 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3607409589 May 12 03:38:11 PM PDT 24 May 12 03:47:25 PM PDT 24 4980386650 ps
T885 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2657699209 May 12 03:30:42 PM PDT 24 May 12 03:36:51 PM PDT 24 3563233892 ps
T214 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.441231759 May 12 03:52:21 PM PDT 24 May 12 03:58:29 PM PDT 24 3285693888 ps
T886 /workspace/coverage/default/0.chip_sw_kmac_smoketest.4121769979 May 12 03:19:24 PM PDT 24 May 12 03:23:00 PM PDT 24 3033520820 ps
T197 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1576497919 May 12 03:16:12 PM PDT 24 May 12 04:59:36 PM PDT 24 49817596310 ps
T499 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.924544625 May 12 03:33:52 PM PDT 24 May 12 03:47:21 PM PDT 24 5012283512 ps
T887 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2678723117 May 12 03:33:07 PM PDT 24 May 12 04:07:23 PM PDT 24 24087888388 ps
T888 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.311602148 May 12 03:40:06 PM PDT 24 May 12 03:43:38 PM PDT 24 2558435180 ps
T889 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3681516913 May 12 03:12:22 PM PDT 24 May 12 06:59:47 PM PDT 24 77192372670 ps
T605 /workspace/coverage/default/2.chip_sw_edn_boot_mode.4180869600 May 12 03:35:14 PM PDT 24 May 12 03:46:38 PM PDT 24 3091999810 ps
T890 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.616381457 May 12 03:13:42 PM PDT 24 May 12 03:44:52 PM PDT 24 11558723907 ps
T307 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1647814164 May 12 03:23:51 PM PDT 24 May 12 03:41:33 PM PDT 24 5664979516 ps
T62 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3266342269 May 12 03:38:21 PM PDT 24 May 12 03:45:19 PM PDT 24 5519138037 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1449544411 May 12 03:13:10 PM PDT 24 May 12 03:19:09 PM PDT 24 3679247724 ps
T891 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.294449953 May 12 03:16:08 PM PDT 24 May 12 03:27:23 PM PDT 24 5757326446 ps
T892 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3037085454 May 12 03:40:16 PM PDT 24 May 12 03:52:53 PM PDT 24 4695883096 ps
T327 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3677727350 May 12 03:22:07 PM PDT 24 May 12 03:34:55 PM PDT 24 4271077795 ps
T658 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1368429930 May 12 03:50:53 PM PDT 24 May 12 03:59:36 PM PDT 24 4144827792 ps
T893 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.285135154 May 12 03:32:25 PM PDT 24 May 12 03:49:11 PM PDT 24 6687722488 ps
T83 /workspace/coverage/default/1.chip_sw_gpio_smoketest.561828946 May 12 03:32:12 PM PDT 24 May 12 03:37:02 PM PDT 24 3238894830 ps
T894 /workspace/coverage/default/2.chip_sw_kmac_idle.1731951734 May 12 03:35:45 PM PDT 24 May 12 03:39:21 PM PDT 24 2604037274 ps
T704 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709929455 May 12 03:49:10 PM PDT 24 May 12 03:55:19 PM PDT 24 3996203100 ps
T48 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2425079948 May 12 03:38:45 PM PDT 24 May 12 04:02:11 PM PDT 24 19682241358 ps
T706 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1359169576 May 12 03:42:48 PM PDT 24 May 12 03:50:09 PM PDT 24 3717630046 ps
T895 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.475166521 May 12 03:20:39 PM PDT 24 May 12 03:29:05 PM PDT 24 3361995670 ps
T190 /workspace/coverage/default/97.chip_sw_all_escalation_resets.4229960847 May 12 03:50:11 PM PDT 24 May 12 04:00:15 PM PDT 24 6039638416 ps
T896 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1597319793 May 12 03:37:21 PM PDT 24 May 12 03:41:03 PM PDT 24 2733679152 ps
T897 /workspace/coverage/default/0.chip_sw_kmac_entropy.1872379114 May 12 03:15:04 PM PDT 24 May 12 03:18:16 PM PDT 24 3396130704 ps
T898 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1234717572 May 12 03:27:21 PM PDT 24 May 12 04:07:53 PM PDT 24 20360142393 ps
T899 /workspace/coverage/default/0.chip_sw_hmac_enc.501641406 May 12 03:13:20 PM PDT 24 May 12 03:16:53 PM PDT 24 2995208118 ps
T25 /workspace/coverage/default/1.chip_sw_gpio.1716071671 May 12 03:22:26 PM PDT 24 May 12 03:29:28 PM PDT 24 3729744812 ps
T313 /workspace/coverage/default/1.chip_sw_pattgen_ios.3574296828 May 12 03:22:23 PM PDT 24 May 12 03:26:35 PM PDT 24 2474719410 ps
T900 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2408121722 May 12 03:32:58 PM PDT 24 May 12 03:40:54 PM PDT 24 5014659730 ps
T901 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1997814465 May 12 03:16:12 PM PDT 24 May 12 03:20:25 PM PDT 24 3033468279 ps
T664 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1640658894 May 12 03:48:54 PM PDT 24 May 12 03:56:56 PM PDT 24 4141743160 ps
T902 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3175809890 May 12 03:35:37 PM PDT 24 May 12 03:40:53 PM PDT 24 3531901200 ps
T127 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1682725818 May 12 03:27:51 PM PDT 24 May 12 03:43:59 PM PDT 24 6367414320 ps
T98 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.322639100 May 12 03:15:10 PM PDT 24 May 12 03:40:31 PM PDT 24 19850939492 ps
T903 /workspace/coverage/default/1.chip_sw_power_sleep_load.1909164815 May 12 03:30:45 PM PDT 24 May 12 03:42:10 PM PDT 24 11282249520 ps
T904 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.129005677 May 12 03:15:11 PM PDT 24 May 12 03:35:33 PM PDT 24 8222264860 ps
T235 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2408874374 May 12 03:41:18 PM PDT 24 May 12 03:55:44 PM PDT 24 5942283292 ps
T905 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2150375175 May 12 03:33:46 PM PDT 24 May 12 03:42:51 PM PDT 24 6328457528 ps
T906 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3544808736 May 12 03:41:41 PM PDT 24 May 12 03:50:13 PM PDT 24 4404163810 ps
T145 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3899629051 May 12 03:26:38 PM PDT 24 May 12 06:33:13 PM PDT 24 256368595702 ps
T105 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.358662449 May 12 03:40:29 PM PDT 24 May 12 04:28:53 PM PDT 24 20733915200 ps
T228 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2506993235 May 12 03:49:29 PM PDT 24 May 12 03:58:39 PM PDT 24 5459843870 ps
T717 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3038502876 May 12 03:47:55 PM PDT 24 May 12 03:58:42 PM PDT 24 5881738946 ps
T282 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2638746861 May 12 03:35:30 PM PDT 24 May 12 07:00:36 PM PDT 24 254459290804 ps
T343 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.233253834 May 12 03:14:37 PM PDT 24 May 12 03:16:49 PM PDT 24 2543327920 ps
T679 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1908141585 May 12 03:48:05 PM PDT 24 May 12 03:58:47 PM PDT 24 5777100100 ps
T232 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2621226451 May 12 03:32:57 PM PDT 24 May 12 03:34:46 PM PDT 24 2631841329 ps
T907 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.133815482 May 12 03:45:26 PM PDT 24 May 12 03:53:00 PM PDT 24 3434128072 ps
T908 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2983125575 May 12 03:19:38 PM PDT 24 May 12 04:01:25 PM PDT 24 9911264572 ps
T215 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1917624377 May 12 03:46:14 PM PDT 24 May 12 03:56:37 PM PDT 24 6366242024 ps
T909 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.184601118 May 12 03:23:24 PM PDT 24 May 12 03:41:58 PM PDT 24 5598923493 ps
T300 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.317938291 May 12 03:29:15 PM PDT 24 May 12 04:02:23 PM PDT 24 8053221444 ps
T365 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3456315781 May 12 03:13:03 PM PDT 24 May 12 03:16:59 PM PDT 24 2730558360 ps
T910 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1300757297 May 12 03:26:36 PM PDT 24 May 12 04:45:35 PM PDT 24 20561098096 ps
T202 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.317777246 May 12 03:23:32 PM PDT 24 May 12 05:04:39 PM PDT 24 48167770256 ps
T911 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2852591425 May 12 03:32:59 PM PDT 24 May 12 03:42:47 PM PDT 24 5233336462 ps
T912 /workspace/coverage/default/1.chip_sw_aes_masking_off.2165889146 May 12 03:25:43 PM PDT 24 May 12 03:29:42 PM PDT 24 2598655543 ps
T913 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.603614583 May 12 03:29:04 PM PDT 24 May 12 03:55:31 PM PDT 24 10675255620 ps
T7 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3380985928 May 12 03:34:30 PM PDT 24 May 12 03:39:15 PM PDT 24 2697559091 ps
T728 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3972370731 May 12 03:48:06 PM PDT 24 May 12 03:55:59 PM PDT 24 4317328536 ps
T216 /workspace/coverage/default/0.chip_jtag_mem_access.2170625444 May 12 03:06:24 PM PDT 24 May 12 03:30:00 PM PDT 24 13293142375 ps
T86 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898500312 May 12 03:47:23 PM PDT 24 May 12 03:55:20 PM PDT 24 4393210032 ps
T200 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1311088367 May 12 03:34:29 PM PDT 24 May 12 05:10:56 PM PDT 24 47853108985 ps
T914 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2845114936 May 12 03:29:48 PM PDT 24 May 12 03:39:38 PM PDT 24 5017565120 ps
T148 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1131827277 May 12 03:32:38 PM PDT 24 May 12 03:35:21 PM PDT 24 2122292825 ps
T619 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1499496042 May 12 03:23:16 PM PDT 24 May 12 03:24:52 PM PDT 24 2685451092 ps
T915 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2455291499 May 12 03:13:08 PM PDT 24 May 12 03:34:02 PM PDT 24 5798918064 ps
T672 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3510625831 May 12 03:43:59 PM PDT 24 May 12 03:54:53 PM PDT 24 4833072674 ps
T325 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1565028113 May 12 03:34:03 PM PDT 24 May 12 03:41:59 PM PDT 24 3955713100 ps
T613 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1126226493 May 12 03:12:38 PM PDT 24 May 12 03:22:13 PM PDT 24 5283995412 ps
T684 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2567732302 May 12 03:44:02 PM PDT 24 May 12 03:55:21 PM PDT 24 6347077528 ps
T620 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.771016069 May 12 03:12:51 PM PDT 24 May 12 03:15:29 PM PDT 24 3234765888 ps
T916 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3197804546 May 12 03:24:54 PM PDT 24 May 12 03:36:40 PM PDT 24 8185663550 ps
T81 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2073816936 May 12 03:25:46 PM PDT 24 May 12 03:30:14 PM PDT 24 3231659705 ps
T917 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.466471864 May 12 03:28:44 PM PDT 24 May 12 03:38:29 PM PDT 24 4004178920 ps
T918 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1553444251 May 12 03:35:42 PM PDT 24 May 12 03:39:30 PM PDT 24 2660363283 ps
T919 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3939026388 May 12 03:28:36 PM PDT 24 May 12 03:31:31 PM PDT 24 2484540242 ps
T723 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1043311931 May 12 03:52:46 PM PDT 24 May 12 04:04:44 PM PDT 24 5199186522 ps
T666 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.383817983 May 12 03:32:20 PM PDT 24 May 12 03:43:16 PM PDT 24 5463456200 ps
T920 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3178172070 May 12 03:44:49 PM PDT 24 May 12 03:54:43 PM PDT 24 4033423672 ps
T168 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.886679141 May 12 03:13:30 PM PDT 24 May 12 03:30:31 PM PDT 24 9368008073 ps
T323 /workspace/coverage/default/61.chip_sw_all_escalation_resets.812082067 May 12 03:48:58 PM PDT 24 May 12 03:59:33 PM PDT 24 4541651810 ps
T10 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3088079268 May 12 03:16:00 PM PDT 24 May 12 03:29:50 PM PDT 24 7996535957 ps
T921 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101106454 May 12 03:44:36 PM PDT 24 May 12 03:51:00 PM PDT 24 3801501228 ps
T922 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3135670210 May 12 03:38:18 PM PDT 24 May 12 03:58:26 PM PDT 24 6741625431 ps
T54 /workspace/coverage/default/2.chip_sw_alert_test.1805241976 May 12 03:34:50 PM PDT 24 May 12 03:39:17 PM PDT 24 2932007656 ps
T203 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.619770902 May 12 03:15:10 PM PDT 24 May 12 04:39:59 PM PDT 24 48153431984 ps
T709 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.524409836 May 12 03:51:22 PM PDT 24 May 12 03:57:15 PM PDT 24 4262662156 ps
T286 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.575110114 May 12 03:34:06 PM PDT 24 May 12 03:56:06 PM PDT 24 11639626250 ps
T923 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.767249615 May 12 03:33:50 PM PDT 24 May 12 03:56:16 PM PDT 24 11542599332 ps
T924 /workspace/coverage/default/0.chip_sw_aes_smoketest.2112971488 May 12 03:18:26 PM PDT 24 May 12 03:23:44 PM PDT 24 3311037888 ps
T925 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1943581529 May 12 03:24:26 PM PDT 24 May 12 03:33:31 PM PDT 24 4820271888 ps
T926 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4057356405 May 12 03:36:56 PM PDT 24 May 12 03:47:16 PM PDT 24 4558602706 ps
T927 /workspace/coverage/default/2.chip_sw_hmac_smoketest.3249713242 May 12 03:40:36 PM PDT 24 May 12 03:46:25 PM PDT 24 3137040104 ps
T306 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3358916880 May 12 03:13:42 PM PDT 24 May 12 03:27:40 PM PDT 24 5474697080 ps
T928 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3884651873 May 12 03:20:38 PM PDT 24 May 12 03:23:38 PM PDT 24 2239728348 ps
T621 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2814516029 May 12 03:33:01 PM PDT 24 May 12 03:34:48 PM PDT 24 2827499462 ps
T691 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1835443306 May 12 03:13:57 PM PDT 24 May 12 03:26:45 PM PDT 24 5398173032 ps
T929 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1892208555 May 12 03:40:45 PM PDT 24 May 12 03:46:48 PM PDT 24 3278791548 ps
T930 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.832108541 May 12 03:12:26 PM PDT 24 May 12 03:16:08 PM PDT 24 2805111204 ps
T169 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3504915491 May 12 03:28:29 PM PDT 24 May 12 03:34:22 PM PDT 24 2769575318 ps
T350 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1071972346 May 12 03:15:11 PM PDT 24 May 12 03:20:20 PM PDT 24 2395694958 ps
T351 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.702661336 May 12 03:28:19 PM PDT 24 May 12 03:39:23 PM PDT 24 4126994900 ps
T352 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.190961525 May 12 03:41:03 PM PDT 24 May 12 03:51:58 PM PDT 24 4708901226 ps
T353 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1327624122 May 12 03:18:52 PM PDT 24 May 12 07:02:17 PM PDT 24 254493106920 ps
T354 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.4106611238 May 12 03:38:03 PM PDT 24 May 12 03:52:42 PM PDT 24 6246772588 ps
T355 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038281173 May 12 03:50:08 PM PDT 24 May 12 03:57:39 PM PDT 24 3714229800 ps
T356 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3032918195 May 12 03:32:16 PM PDT 24 May 12 03:42:47 PM PDT 24 4024161596 ps
T357 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2385602953 May 12 03:15:57 PM PDT 24 May 12 03:23:24 PM PDT 24 4832027780 ps
T358 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2737903167 May 12 03:29:51 PM PDT 24 May 12 04:33:40 PM PDT 24 25404701699 ps
T931 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1464908173 May 12 03:41:23 PM PDT 24 May 12 03:53:16 PM PDT 24 3565553600 ps
T932 /workspace/coverage/default/1.chip_sw_example_concurrency.4258774675 May 12 03:21:12 PM PDT 24 May 12 03:24:31 PM PDT 24 2195180500 ps
T933 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2731968862 May 12 03:32:34 PM PDT 24 May 12 03:51:10 PM PDT 24 5352811294 ps
T66 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.721355068 May 12 03:14:12 PM PDT 24 May 12 03:22:56 PM PDT 24 3562700980 ps
T675 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377639555 May 12 03:15:23 PM PDT 24 May 12 03:22:47 PM PDT 24 3926684612 ps
T934 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3504289061 May 12 03:44:15 PM PDT 24 May 12 04:12:37 PM PDT 24 7719764490 ps
T403 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.226050462 May 12 03:42:04 PM PDT 24 May 12 03:47:40 PM PDT 24 4164952690 ps
T935 /workspace/coverage/default/2.chip_sw_example_concurrency.3228545924 May 12 03:35:48 PM PDT 24 May 12 03:39:54 PM PDT 24 2152732040 ps
T697 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849084989 May 12 03:49:22 PM PDT 24 May 12 03:54:48 PM PDT 24 3677794258 ps
T936 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3036621561 May 12 03:17:06 PM PDT 24 May 12 03:27:44 PM PDT 24 4237774020 ps
T937 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2997948226 May 12 03:40:04 PM PDT 24 May 12 03:46:46 PM PDT 24 5662178960 ps
T287 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.423184537 May 12 03:23:57 PM PDT 24 May 12 03:53:30 PM PDT 24 11465757440 ps
T689 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1645378317 May 12 03:47:43 PM PDT 24 May 12 03:57:23 PM PDT 24 4251415680 ps
T938 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3961276182 May 12 03:32:42 PM PDT 24 May 12 04:16:23 PM PDT 24 13214165554 ps
T939 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2130911873 May 12 03:29:16 PM PDT 24 May 12 03:41:14 PM PDT 24 5841240980 ps
T940 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.613087454 May 12 03:34:19 PM PDT 24 May 12 03:46:09 PM PDT 24 5292224848 ps
T941 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1750036452 May 12 03:37:49 PM PDT 24 May 12 03:45:53 PM PDT 24 3973504436 ps
T8 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2255129871 May 12 03:13:24 PM PDT 24 May 12 03:17:48 PM PDT 24 3366233132 ps
T221 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.859226585 May 12 03:28:53 PM PDT 24 May 12 03:37:42 PM PDT 24 4603529560 ps
T942 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1336224661 May 12 03:29:54 PM PDT 24 May 12 03:48:52 PM PDT 24 7246825023 ps
T651 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3738280577 May 12 03:47:57 PM PDT 24 May 12 04:01:38 PM PDT 24 6115172176 ps
T943 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.287596434 May 12 03:34:53 PM PDT 24 May 12 04:16:26 PM PDT 24 9693712110 ps
T149 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4194261588 May 12 03:17:54 PM PDT 24 May 12 03:19:54 PM PDT 24 2555021071 ps
T944 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3015263641 May 12 03:18:25 PM PDT 24 May 12 03:37:54 PM PDT 24 10840824400 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2507860618 May 12 03:32:44 PM PDT 24 May 12 03:40:44 PM PDT 24 4620247624 ps
T945 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1281975312 May 12 03:42:14 PM PDT 24 May 12 03:55:52 PM PDT 24 9630963651 ps
T946 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3397031966 May 12 03:34:24 PM PDT 24 May 12 04:23:20 PM PDT 24 26701812904 ps
T947 /workspace/coverage/default/2.rom_keymgr_functest.954881263 May 12 03:39:34 PM PDT 24 May 12 03:50:10 PM PDT 24 4523658160 ps
T330 /workspace/coverage/default/2.chip_sw_hmac_enc.2703245895 May 12 03:35:22 PM PDT 24 May 12 03:39:47 PM PDT 24 2362277376 ps
T948 /workspace/coverage/default/2.chip_sw_example_manufacturer.615111461 May 12 03:36:03 PM PDT 24 May 12 03:39:18 PM PDT 24 2699237798 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.408727702 May 12 03:21:21 PM PDT 24 May 12 03:31:55 PM PDT 24 3956302312 ps
T949 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.681973457 May 12 03:41:54 PM PDT 24 May 12 03:45:26 PM PDT 24 2505239068 ps
T950 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.561472517 May 12 03:24:08 PM PDT 24 May 12 03:52:44 PM PDT 24 13657369373 ps
T951 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1149435065 May 12 03:33:59 PM PDT 24 May 12 03:46:56 PM PDT 24 7721298096 ps
T952 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.430862986 May 12 03:34:40 PM PDT 24 May 12 04:16:20 PM PDT 24 25432720565 ps
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