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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.37 93.88 95.58 94.49 97.38 99.54


Total test records in report: 2783
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T953 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.947299928 May 12 03:37:04 PM PDT 24 May 12 03:45:11 PM PDT 24 5176446344 ps
T653 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2758993949 May 12 03:43:07 PM PDT 24 May 12 03:51:42 PM PDT 24 5251654596 ps
T954 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3624862848 May 12 03:24:23 PM PDT 24 May 12 03:38:44 PM PDT 24 4143329832 ps
T955 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2433086094 May 12 03:32:55 PM PDT 24 May 12 03:40:26 PM PDT 24 3944264832 ps
T194 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.506501961 May 12 03:36:16 PM PDT 24 May 12 04:32:44 PM PDT 24 12675348880 ps
T956 /workspace/coverage/default/1.chip_sw_edn_kat.19059940 May 12 03:26:36 PM PDT 24 May 12 03:37:19 PM PDT 24 3622021592 ps
T603 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3127962450 May 12 03:35:04 PM PDT 24 May 12 03:56:16 PM PDT 24 4485468524 ps
T659 /workspace/coverage/default/39.chip_sw_all_escalation_resets.4260747950 May 12 03:47:03 PM PDT 24 May 12 03:58:29 PM PDT 24 4371048272 ps
T957 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3086118479 May 12 03:31:57 PM PDT 24 May 12 03:36:45 PM PDT 24 2811660600 ps
T958 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4073744782 May 12 03:28:44 PM PDT 24 May 12 03:34:10 PM PDT 24 5493638200 ps
T959 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1155560795 May 12 03:48:47 PM PDT 24 May 12 03:57:50 PM PDT 24 5191479922 ps
T960 /workspace/coverage/default/2.chip_sw_kmac_entropy.2770168029 May 12 03:31:40 PM PDT 24 May 12 03:35:21 PM PDT 24 2521933634 ps
T729 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2272544501 May 12 03:41:54 PM PDT 24 May 12 03:50:13 PM PDT 24 4223652268 ps
T21 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2998135578 May 12 03:33:42 PM PDT 24 May 12 04:01:19 PM PDT 24 21790538088 ps
T961 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2829281396 May 12 03:25:43 PM PDT 24 May 12 03:36:40 PM PDT 24 3821751068 ps
T962 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3164420286 May 12 03:25:25 PM PDT 24 May 12 03:38:21 PM PDT 24 4461799008 ps
T326 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2381002481 May 12 03:14:12 PM PDT 24 May 12 03:21:06 PM PDT 24 4043655166 ps
T963 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1167122037 May 12 03:36:04 PM PDT 24 May 12 03:45:08 PM PDT 24 3887206136 ps
T964 /workspace/coverage/default/2.chip_sw_aes_entropy.530926345 May 12 03:35:44 PM PDT 24 May 12 03:40:24 PM PDT 24 2154191640 ps
T965 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2293447303 May 12 03:36:55 PM PDT 24 May 12 03:44:43 PM PDT 24 7314871610 ps
T367 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3398978083 May 12 03:38:29 PM PDT 24 May 12 03:44:19 PM PDT 24 4316954444 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2247424304 May 12 03:22:06 PM PDT 24 May 12 03:36:20 PM PDT 24 6639848754 ps
T386 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.601300973 May 12 03:15:06 PM PDT 24 May 12 03:26:34 PM PDT 24 4791313363 ps
T387 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3673127872 May 12 03:35:17 PM PDT 24 May 12 03:38:57 PM PDT 24 2390613678 ps
T388 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4138837664 May 12 03:29:58 PM PDT 24 May 12 03:41:00 PM PDT 24 4397313452 ps
T389 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2699176038 May 12 03:30:42 PM PDT 24 May 12 03:33:47 PM PDT 24 3069554256 ps
T99 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.604031114 May 12 03:28:53 PM PDT 24 May 12 03:58:21 PM PDT 24 20503844106 ps
T33 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.742234522 May 12 03:12:16 PM PDT 24 May 12 03:17:50 PM PDT 24 3345182100 ps
T272 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.858484594 May 12 03:36:38 PM PDT 24 May 12 03:48:29 PM PDT 24 8401547550 ps
T219 /workspace/coverage/default/0.chip_sw_power_sleep_load.3690817635 May 12 03:16:18 PM PDT 24 May 12 03:21:31 PM PDT 24 4418141828 ps
T966 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.922638648 May 12 03:15:06 PM PDT 24 May 12 03:18:03 PM PDT 24 2837718949 ps
T614 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2792673473 May 12 03:14:04 PM PDT 24 May 12 03:22:57 PM PDT 24 5771313981 ps
T967 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3710795251 May 12 03:28:44 PM PDT 24 May 12 03:38:57 PM PDT 24 4785333940 ps
T106 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1809102049 May 12 03:32:01 PM PDT 24 May 12 04:29:01 PM PDT 24 19759064367 ps
T968 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3727693572 May 12 03:30:52 PM PDT 24 May 12 03:35:10 PM PDT 24 2449363760 ps
T969 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3756024359 May 12 03:15:32 PM PDT 24 May 12 03:26:53 PM PDT 24 4328516040 ps
T970 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3036966163 May 12 03:18:32 PM PDT 24 May 12 03:39:06 PM PDT 24 7626392344 ps
T971 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.168321793 May 12 03:40:33 PM PDT 24 May 12 03:52:10 PM PDT 24 9690294285 ps
T972 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2039332845 May 12 03:33:23 PM PDT 24 May 12 03:43:15 PM PDT 24 3409029054 ps
T973 /workspace/coverage/default/2.chip_sw_example_flash.165887747 May 12 03:32:16 PM PDT 24 May 12 03:35:29 PM PDT 24 2135252580 ps
T974 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2941590334 May 12 03:26:37 PM PDT 24 May 12 03:31:54 PM PDT 24 3029959693 ps
T680 /workspace/coverage/default/48.chip_sw_all_escalation_resets.279149445 May 12 03:48:09 PM PDT 24 May 12 03:57:34 PM PDT 24 5494821840 ps
T975 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1169012878 May 12 03:39:28 PM PDT 24 May 12 03:43:18 PM PDT 24 3092704648 ps
T201 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2288149548 May 12 03:33:11 PM PDT 24 May 12 05:02:58 PM PDT 24 49361515044 ps
T126 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1921572988 May 12 03:36:16 PM PDT 24 May 12 03:50:57 PM PDT 24 6438788000 ps
T976 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2292889878 May 12 03:33:32 PM PDT 24 May 12 03:45:38 PM PDT 24 4290035400 ps
T644 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1185669730 May 12 03:24:27 PM PDT 24 May 12 03:49:54 PM PDT 24 22650544120 ps
T977 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3672774047 May 12 03:20:48 PM PDT 24 May 12 03:28:58 PM PDT 24 3861152680 ps
T978 /workspace/coverage/default/1.chip_sw_uart_smoketest.3984879976 May 12 03:35:17 PM PDT 24 May 12 03:39:14 PM PDT 24 3320062840 ps
T979 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.598907953 May 12 03:40:24 PM PDT 24 May 12 03:43:34 PM PDT 24 2398966776 ps
T633 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.505286229 May 12 03:24:40 PM PDT 24 May 12 03:28:35 PM PDT 24 2854452376 ps
T980 /workspace/coverage/default/2.chip_sw_power_sleep_load.1098919620 May 12 03:39:15 PM PDT 24 May 12 03:50:06 PM PDT 24 9800910234 ps
T981 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.594094992 May 12 03:25:59 PM PDT 24 May 12 03:30:15 PM PDT 24 2969783716 ps
T982 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.429609326 May 12 03:13:33 PM PDT 24 May 12 03:23:34 PM PDT 24 5619338600 ps
T725 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515869600 May 12 03:49:07 PM PDT 24 May 12 03:57:37 PM PDT 24 3839249280 ps
T983 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2193997919 May 12 03:30:22 PM PDT 24 May 12 03:35:47 PM PDT 24 3210983950 ps
T984 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1106861766 May 12 03:43:50 PM PDT 24 May 12 03:55:43 PM PDT 24 3717020780 ps
T985 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1548324810 May 12 03:46:54 PM PDT 24 May 12 03:52:16 PM PDT 24 4042999400 ps
T986 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1633342303 May 12 03:41:42 PM PDT 24 May 12 03:52:29 PM PDT 24 4232584854 ps
T987 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.315128855 May 12 03:12:57 PM PDT 24 May 12 03:49:21 PM PDT 24 9122865720 ps
T195 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1536896986 May 12 03:15:11 PM PDT 24 May 12 04:34:47 PM PDT 24 17580430398 ps
T988 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2017965153 May 12 03:15:15 PM PDT 24 May 12 04:09:12 PM PDT 24 12002809396 ps
T989 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2156869111 May 12 03:16:11 PM PDT 24 May 12 03:19:58 PM PDT 24 2848399182 ps
T87 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3372368127 May 12 03:45:36 PM PDT 24 May 12 03:52:43 PM PDT 24 3092787758 ps
T990 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3916992614 May 12 03:27:33 PM PDT 24 May 12 03:36:26 PM PDT 24 4203945392 ps
T991 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1530640285 May 12 03:33:16 PM PDT 24 May 12 03:41:47 PM PDT 24 7748358656 ps
T222 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.878498435 May 12 03:39:10 PM PDT 24 May 12 03:50:21 PM PDT 24 4740015820 ps
T992 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3317590962 May 12 03:32:41 PM PDT 24 May 12 03:36:10 PM PDT 24 2797931362 ps
T731 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137643236 May 12 03:51:02 PM PDT 24 May 12 03:58:44 PM PDT 24 4298457774 ps
T993 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.839586110 May 12 03:34:50 PM PDT 24 May 12 03:48:15 PM PDT 24 6052664075 ps
T994 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3790972970 May 12 03:22:02 PM PDT 24 May 12 03:28:19 PM PDT 24 4939520760 ps
T995 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1592959578 May 12 03:15:46 PM PDT 24 May 12 03:34:35 PM PDT 24 11536920913 ps
T996 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1393263543 May 12 03:23:20 PM PDT 24 May 12 03:39:57 PM PDT 24 9330014056 ps
T299 /workspace/coverage/default/0.chip_plic_all_irqs_20.315245405 May 12 03:15:20 PM PDT 24 May 12 03:26:18 PM PDT 24 4606989218 ps
T997 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3104214949 May 12 03:24:11 PM PDT 24 May 12 04:06:52 PM PDT 24 19764482994 ps
T707 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241130076 May 12 03:47:56 PM PDT 24 May 12 03:55:25 PM PDT 24 3400592458 ps
T645 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3162540581 May 12 03:14:05 PM PDT 24 May 12 03:48:17 PM PDT 24 24460471048 ps
T998 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.278481283 May 12 03:32:39 PM PDT 24 May 12 03:37:01 PM PDT 24 2393883118 ps
T999 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1258142103 May 12 03:24:55 PM PDT 24 May 12 03:36:55 PM PDT 24 6411363092 ps
T1000 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2338243991 May 12 03:19:33 PM PDT 24 May 12 03:25:23 PM PDT 24 3324429964 ps
T331 /workspace/coverage/default/1.chip_sw_hmac_enc.1101204310 May 12 03:27:13 PM PDT 24 May 12 03:31:28 PM PDT 24 2752745172 ps
T1001 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1210161014 May 12 03:29:17 PM PDT 24 May 12 03:44:10 PM PDT 24 5013271656 ps
T1002 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1137711682 May 12 03:40:07 PM PDT 24 May 12 03:45:21 PM PDT 24 2765450780 ps
T702 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219561413 May 12 03:45:49 PM PDT 24 May 12 03:52:57 PM PDT 24 3559737368 ps
T1003 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1232123159 May 12 03:29:50 PM PDT 24 May 12 03:52:41 PM PDT 24 7016840820 ps
T1004 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3090602517 May 12 03:22:18 PM PDT 24 May 12 07:11:21 PM PDT 24 76062499810 ps
T617 /workspace/coverage/default/3.chip_tap_straps_dev.3649005221 May 12 03:40:08 PM PDT 24 May 12 04:05:39 PM PDT 24 13437354735 ps
T1005 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1569841024 May 12 03:13:53 PM PDT 24 May 12 03:16:27 PM PDT 24 3403251507 ps
T1006 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2662790110 May 12 03:32:12 PM PDT 24 May 12 03:35:25 PM PDT 24 3028945526 ps
T618 /workspace/coverage/default/4.chip_tap_straps_dev.3192068687 May 12 03:41:22 PM PDT 24 May 12 03:59:53 PM PDT 24 11298749815 ps
T1007 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2526010704 May 12 03:24:25 PM PDT 24 May 12 03:43:00 PM PDT 24 6371461880 ps
T55 /workspace/coverage/default/1.chip_sw_alert_test.2856442464 May 12 03:26:48 PM PDT 24 May 12 03:31:40 PM PDT 24 2930958900 ps
T1008 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1533026668 May 12 03:34:11 PM PDT 24 May 12 03:41:54 PM PDT 24 6639132564 ps
T1009 /workspace/coverage/default/0.chip_sw_aes_enc.2516038601 May 12 03:14:57 PM PDT 24 May 12 03:19:31 PM PDT 24 3289857940 ps
T1010 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4141247182 May 12 03:33:01 PM PDT 24 May 12 03:37:41 PM PDT 24 3066165804 ps
T1011 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2561115306 May 12 03:28:42 PM PDT 24 May 12 03:35:32 PM PDT 24 3146009142 ps
T719 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665664609 May 12 03:44:16 PM PDT 24 May 12 03:50:02 PM PDT 24 2928831080 ps
T641 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3407345701 May 12 03:27:00 PM PDT 24 May 12 03:41:56 PM PDT 24 4645081476 ps
T246 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1524702631 May 12 03:17:44 PM PDT 24 May 12 03:31:08 PM PDT 24 5378988434 ps
T1012 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1937845164 May 12 03:37:29 PM PDT 24 May 12 03:46:53 PM PDT 24 4620524686 ps
T1013 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.480290140 May 12 03:31:37 PM PDT 24 May 12 03:51:01 PM PDT 24 6157987364 ps
T634 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3891566354 May 12 03:13:59 PM PDT 24 May 12 03:17:48 PM PDT 24 3307758890 ps
T1014 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1237044940 May 12 03:34:11 PM PDT 24 May 12 03:43:26 PM PDT 24 4181617848 ps
T1015 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3914508606 May 12 03:41:28 PM PDT 24 May 12 03:53:37 PM PDT 24 4387197184 ps
T1016 /workspace/coverage/default/2.chip_sw_otbn_smoketest.4049823382 May 12 03:41:16 PM PDT 24 May 12 04:22:20 PM PDT 24 11579415288 ps
T26 /workspace/coverage/default/2.chip_sw_gpio.2582293317 May 12 03:31:36 PM PDT 24 May 12 03:38:21 PM PDT 24 3935308098 ps
T1017 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2817090729 May 12 03:37:11 PM PDT 24 May 12 03:45:45 PM PDT 24 3263922096 ps
T721 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130340094 May 12 03:44:50 PM PDT 24 May 12 03:52:00 PM PDT 24 3365822680 ps
T1018 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3432370817 May 12 03:13:31 PM PDT 24 May 12 03:18:06 PM PDT 24 3179105000 ps
T1019 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3028160200 May 12 03:43:48 PM PDT 24 May 12 03:51:32 PM PDT 24 5640767504 ps
T1020 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.141439989 May 12 03:41:49 PM PDT 24 May 12 03:49:01 PM PDT 24 7289241696 ps
T1021 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.871912108 May 12 03:26:24 PM PDT 24 May 12 03:31:55 PM PDT 24 3358924648 ps
T1022 /workspace/coverage/default/1.chip_tap_straps_rma.3386469483 May 12 03:28:39 PM PDT 24 May 12 03:33:13 PM PDT 24 3355899054 ps
T1023 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1706290711 May 12 03:35:47 PM PDT 24 May 12 03:53:08 PM PDT 24 6534864236 ps
T1024 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2303116440 May 12 03:15:27 PM PDT 24 May 12 03:42:14 PM PDT 24 8556795704 ps
T247 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2816517483 May 12 03:26:59 PM PDT 24 May 12 03:37:34 PM PDT 24 4509588905 ps
T88 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3385639646 May 12 03:52:12 PM PDT 24 May 12 04:00:45 PM PDT 24 4858562996 ps
T1025 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3107062547 May 12 03:46:05 PM PDT 24 May 12 03:58:33 PM PDT 24 5278465340 ps
T158 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1803698959 May 12 03:50:56 PM PDT 24 May 12 04:00:54 PM PDT 24 5035798136 ps
T711 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661501080 May 12 03:48:54 PM PDT 24 May 12 03:55:16 PM PDT 24 3883829648 ps
T176 /workspace/coverage/default/1.chip_jtag_csr_rw.2280788383 May 12 03:21:06 PM PDT 24 May 12 03:46:34 PM PDT 24 12179031965 ps
T648 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4063097436 May 12 03:46:32 PM PDT 24 May 12 03:54:00 PM PDT 24 3982090352 ps
T722 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3250949515 May 12 03:47:40 PM PDT 24 May 12 03:55:08 PM PDT 24 3840333580 ps
T308 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.81937317 May 12 03:32:46 PM PDT 24 May 12 03:46:26 PM PDT 24 4882976560 ps
T1026 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.778693532 May 12 03:35:08 PM PDT 24 May 12 03:39:34 PM PDT 24 3080930184 ps
T1027 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1067472600 May 12 03:28:09 PM PDT 24 May 12 03:38:02 PM PDT 24 4776499858 ps
T1028 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1600553086 May 12 03:32:42 PM PDT 24 May 12 03:44:45 PM PDT 24 3979662684 ps
T732 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4214856760 May 12 03:47:46 PM PDT 24 May 12 03:58:38 PM PDT 24 4800223624 ps
T1029 /workspace/coverage/default/3.chip_tap_straps_prod.564510614 May 12 03:40:48 PM PDT 24 May 12 03:44:09 PM PDT 24 3313998839 ps
T248 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1790679806 May 12 03:26:39 PM PDT 24 May 12 03:36:11 PM PDT 24 3713440566 ps
T1030 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3332467395 May 12 03:28:38 PM PDT 24 May 12 03:39:39 PM PDT 24 6919899160 ps
T1031 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2961574791 May 12 03:20:48 PM PDT 24 May 12 03:54:09 PM PDT 24 34345168125 ps
T1032 /workspace/coverage/default/1.chip_sw_kmac_app_rom.4124299829 May 12 03:28:37 PM PDT 24 May 12 03:33:20 PM PDT 24 2508362104 ps
T1033 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3387246070 May 12 03:14:41 PM PDT 24 May 12 03:21:35 PM PDT 24 3315579504 ps
T1034 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2933350398 May 12 03:20:44 PM PDT 24 May 12 03:25:43 PM PDT 24 2500433028 ps
T655 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1878675064 May 12 03:50:18 PM PDT 24 May 12 03:59:55 PM PDT 24 5065971768 ps
T410 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3786204045 May 12 03:16:15 PM PDT 24 May 12 03:22:09 PM PDT 24 3721594455 ps
T1035 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2012073253 May 12 03:25:04 PM PDT 24 May 12 04:24:20 PM PDT 24 17572074968 ps
T249 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1331754422 May 12 03:14:02 PM PDT 24 May 12 03:21:34 PM PDT 24 3673124860 ps
T681 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2370819496 May 12 03:47:31 PM PDT 24 May 12 03:53:44 PM PDT 24 3327672496 ps
T1036 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.139840663 May 12 03:42:49 PM PDT 24 May 12 03:50:14 PM PDT 24 3846130184 ps
T677 /workspace/coverage/default/77.chip_sw_all_escalation_resets.4197549870 May 12 03:49:31 PM PDT 24 May 12 04:00:35 PM PDT 24 4755636644 ps
T1037 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3797724836 May 12 03:40:32 PM PDT 24 May 12 03:53:46 PM PDT 24 8219799165 ps
T1038 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050062654 May 12 03:44:10 PM PDT 24 May 12 03:50:53 PM PDT 24 3327316976 ps
T1039 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4039613948 May 12 03:13:26 PM PDT 24 May 12 03:23:18 PM PDT 24 5233869544 ps
T250 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2841966037 May 12 03:15:29 PM PDT 24 May 12 03:25:42 PM PDT 24 3941312406 ps
T1040 /workspace/coverage/default/0.chip_sw_csrng_kat_test.60213015 May 12 03:14:28 PM PDT 24 May 12 03:18:16 PM PDT 24 2382500218 ps
T590 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1443147446 May 12 03:27:24 PM PDT 24 May 12 03:35:45 PM PDT 24 3753854642 ps
T1041 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2258719746 May 12 03:32:40 PM PDT 24 May 12 03:39:50 PM PDT 24 4316665408 ps
T1042 /workspace/coverage/default/62.chip_sw_all_escalation_resets.968686251 May 12 03:48:58 PM PDT 24 May 12 04:01:02 PM PDT 24 5905995496 ps
T1043 /workspace/coverage/default/1.chip_sw_aon_timer_irq.950549569 May 12 03:25:21 PM PDT 24 May 12 03:31:17 PM PDT 24 3330554396 ps
T1044 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3621660136 May 12 03:21:59 PM PDT 24 May 12 03:39:28 PM PDT 24 5765487790 ps
T1045 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2422493629 May 12 03:13:18 PM PDT 24 May 12 03:22:08 PM PDT 24 6494657200 ps
T1046 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.43893397 May 12 03:42:13 PM PDT 24 May 12 03:49:22 PM PDT 24 7024145157 ps
T1047 /workspace/coverage/default/0.chip_sw_aes_idle.2523135616 May 12 03:15:43 PM PDT 24 May 12 03:19:17 PM PDT 24 2083332614 ps
T1048 /workspace/coverage/default/2.chip_sw_otbn_randomness.618220373 May 12 03:34:24 PM PDT 24 May 12 03:49:49 PM PDT 24 5289913472 ps
T46 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.489867923 May 12 03:15:00 PM PDT 24 May 12 03:22:56 PM PDT 24 4515530332 ps
T390 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.941438028 May 12 03:37:14 PM PDT 24 May 12 03:40:36 PM PDT 24 1835083180 ps
T391 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3348019510 May 12 03:49:47 PM PDT 24 May 12 03:57:15 PM PDT 24 3769302976 ps
T89 /workspace/coverage/default/43.chip_sw_all_escalation_resets.4215237254 May 12 03:48:58 PM PDT 24 May 12 03:57:51 PM PDT 24 5399086150 ps
T392 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4176270828 May 12 03:27:44 PM PDT 24 May 12 03:37:28 PM PDT 24 4615461796 ps
T393 /workspace/coverage/default/29.chip_sw_all_escalation_resets.4228730674 May 12 03:46:13 PM PDT 24 May 12 03:56:53 PM PDT 24 5636583740 ps
T394 /workspace/coverage/default/4.chip_tap_straps_prod.618835308 May 12 03:41:44 PM PDT 24 May 12 03:43:53 PM PDT 24 2425435853 ps
T395 /workspace/coverage/default/2.chip_sw_uart_smoketest.4187924192 May 12 03:39:54 PM PDT 24 May 12 03:44:26 PM PDT 24 2589797900 ps
T396 /workspace/coverage/default/0.rom_keymgr_functest.1879043080 May 12 03:20:43 PM PDT 24 May 12 03:28:29 PM PDT 24 4849801380 ps
T344 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.172327913 May 12 03:28:30 PM PDT 24 May 12 03:33:06 PM PDT 24 2846028992 ps
T1049 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3903132782 May 12 03:15:03 PM PDT 24 May 12 03:59:13 PM PDT 24 25658763570 ps
T1050 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.39940126 May 12 03:18:16 PM PDT 24 May 12 03:21:59 PM PDT 24 2940578229 ps
T296 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1116109424 May 12 03:16:03 PM PDT 24 May 12 03:28:15 PM PDT 24 3735526244 ps
T206 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3560823138 May 12 03:14:59 PM PDT 24 May 12 04:49:38 PM PDT 24 45881441898 ps
T179 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3034732975 May 12 03:14:01 PM PDT 24 May 12 03:22:18 PM PDT 24 4787807532 ps
T615 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3141404370 May 12 03:28:28 PM PDT 24 May 12 03:39:09 PM PDT 24 5097247982 ps
T1051 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.610016247 May 12 03:36:46 PM PDT 24 May 12 03:48:55 PM PDT 24 6885438020 ps
T734 /workspace/coverage/default/75.chip_sw_all_escalation_resets.2243889134 May 12 03:50:18 PM PDT 24 May 12 04:01:22 PM PDT 24 5987881176 ps
T690 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2323507388 May 12 03:49:47 PM PDT 24 May 12 04:02:53 PM PDT 24 4991786504 ps
T1052 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1013481524 May 12 03:15:14 PM PDT 24 May 12 03:45:19 PM PDT 24 8608121477 ps
T616 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.935566519 May 12 03:38:22 PM PDT 24 May 12 03:48:42 PM PDT 24 4279138239 ps
T1053 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1739112158 May 12 03:38:32 PM PDT 24 May 12 04:14:40 PM PDT 24 14041353170 ps
T1054 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4023586948 May 12 03:16:47 PM PDT 24 May 12 03:22:33 PM PDT 24 2930725536 ps
T314 /workspace/coverage/default/0.chip_sw_pattgen_ios.4118971249 May 12 03:14:07 PM PDT 24 May 12 03:18:39 PM PDT 24 2704948170 ps
T1055 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.442436547 May 12 03:43:55 PM PDT 24 May 12 04:00:27 PM PDT 24 13285952669 ps
T1056 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3711659785 May 12 03:45:06 PM PDT 24 May 12 03:55:30 PM PDT 24 4360980334 ps
T1057 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2934791465 May 12 03:47:52 PM PDT 24 May 12 03:58:10 PM PDT 24 4591654102 ps
T1058 /workspace/coverage/default/0.chip_sw_example_concurrency.2901959451 May 12 03:15:57 PM PDT 24 May 12 03:19:30 PM PDT 24 2610521076 ps
T1059 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1193000254 May 12 03:13:04 PM PDT 24 May 12 03:25:29 PM PDT 24 5816336656 ps
T1060 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2314758855 May 12 03:32:44 PM PDT 24 May 12 03:54:05 PM PDT 24 9069305684 ps
T1061 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3268629698 May 12 03:15:01 PM PDT 24 May 12 03:25:59 PM PDT 24 4417400950 ps
T1062 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3452311686 May 12 03:43:56 PM PDT 24 May 12 04:26:17 PM PDT 24 13011923772 ps
T404 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851794255 May 12 03:49:01 PM PDT 24 May 12 03:55:49 PM PDT 24 3842518418 ps
T1063 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1055540665 May 12 03:34:01 PM PDT 24 May 12 04:14:25 PM PDT 24 10286991164 ps
T319 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3088831349 May 12 03:20:27 PM PDT 24 May 12 03:33:01 PM PDT 24 5255172976 ps
T724 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.573806694 May 12 03:44:35 PM PDT 24 May 12 03:53:18 PM PDT 24 3798966124 ps
T1064 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1092150135 May 12 03:17:03 PM PDT 24 May 12 03:38:41 PM PDT 24 10397912400 ps
T1065 /workspace/coverage/default/0.chip_sival_flash_info_access.449683891 May 12 03:15:26 PM PDT 24 May 12 03:19:44 PM PDT 24 2249164528 ps
T236 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.103048966 May 12 03:42:35 PM PDT 24 May 12 03:59:36 PM PDT 24 5799706362 ps
T1066 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2168069895 May 12 03:40:49 PM PDT 24 May 12 03:45:52 PM PDT 24 2959486022 ps
T1067 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2242516666 May 12 03:14:13 PM PDT 24 May 12 03:21:33 PM PDT 24 3061862266 ps
T1068 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3933204782 May 12 03:16:44 PM PDT 24 May 12 03:24:06 PM PDT 24 4088051068 ps
T170 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.673166720 May 12 03:28:59 PM PDT 24 May 12 03:34:19 PM PDT 24 2457936580 ps
T1069 /workspace/coverage/default/0.chip_tap_straps_dev.3842895029 May 12 03:14:17 PM PDT 24 May 12 03:39:38 PM PDT 24 15349538802 ps
T1070 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1605714488 May 12 03:15:32 PM PDT 24 May 12 03:42:37 PM PDT 24 8448202508 ps
T1071 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4006455474 May 12 03:20:14 PM PDT 24 May 12 03:31:04 PM PDT 24 4800665376 ps
T1072 /workspace/coverage/default/1.chip_sw_aes_idle.337854479 May 12 03:24:58 PM PDT 24 May 12 03:29:24 PM PDT 24 2899007480 ps
T1073 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3174936441 May 12 03:25:01 PM PDT 24 May 12 03:55:36 PM PDT 24 17415951100 ps
T1074 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1014909668 May 12 03:18:21 PM PDT 24 May 12 03:27:24 PM PDT 24 6935134068 ps
T1075 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2763659119 May 12 03:28:21 PM PDT 24 May 12 03:36:14 PM PDT 24 3755834104 ps
T1076 /workspace/coverage/default/80.chip_sw_all_escalation_resets.233905585 May 12 03:48:38 PM PDT 24 May 12 03:56:39 PM PDT 24 4406800704 ps
T1077 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4171440436 May 12 03:29:44 PM PDT 24 May 12 03:34:34 PM PDT 24 3076982776 ps
T699 /workspace/coverage/default/6.chip_sw_all_escalation_resets.548746495 May 12 03:42:36 PM PDT 24 May 12 03:54:01 PM PDT 24 5413084440 ps
T1078 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2790075702 May 12 03:15:15 PM PDT 24 May 12 03:22:14 PM PDT 24 5102018494 ps
T263 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4199621216 May 12 03:14:56 PM PDT 24 May 12 03:18:53 PM PDT 24 2233228992 ps
T1079 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3073402425 May 12 03:30:27 PM PDT 24 May 12 03:35:47 PM PDT 24 2957688381 ps
T223 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.788242928 May 12 03:17:58 PM PDT 24 May 12 03:26:30 PM PDT 24 5148569940 ps
T685 /workspace/coverage/default/40.chip_sw_all_escalation_resets.3646639602 May 12 03:47:44 PM PDT 24 May 12 03:57:59 PM PDT 24 5663723500 ps
T1080 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2433098468 May 12 03:14:20 PM PDT 24 May 12 03:22:40 PM PDT 24 5231486390 ps
T1081 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.990943340 May 12 03:41:20 PM PDT 24 May 12 04:11:40 PM PDT 24 8197656793 ps
T1082 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4092114526 May 12 03:13:29 PM PDT 24 May 12 03:25:59 PM PDT 24 6096340220 ps
T715 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328408739 May 12 03:44:57 PM PDT 24 May 12 03:51:45 PM PDT 24 4222716152 ps
T1083 /workspace/coverage/default/1.chip_tap_straps_dev.30939055 May 12 03:29:00 PM PDT 24 May 12 03:56:25 PM PDT 24 15585312772 ps
T1084 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1040074709 May 12 03:32:09 PM PDT 24 May 12 04:11:52 PM PDT 24 12959510588 ps
T1085 /workspace/coverage/default/1.chip_sw_aes_smoketest.2733185459 May 12 03:31:41 PM PDT 24 May 12 03:36:51 PM PDT 24 2557891976 ps
T606 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3495548279 May 12 03:18:38 PM PDT 24 May 12 03:26:34 PM PDT 24 2702771664 ps
T1086 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3880096497 May 12 03:49:24 PM PDT 24 May 12 03:57:35 PM PDT 24 3544188800 ps
T1087 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3777031516 May 12 03:46:47 PM PDT 24 May 12 03:57:20 PM PDT 24 5482920312 ps
T205 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3304344784 May 12 03:23:08 PM PDT 24 May 12 04:49:45 PM PDT 24 46130739137 ps
T159 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1294779940 May 12 03:49:38 PM PDT 24 May 12 04:04:06 PM PDT 24 5358837596 ps
T1088 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1105211688 May 12 03:14:20 PM PDT 24 May 12 03:22:49 PM PDT 24 4605122278 ps
T1089 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3729183260 May 12 03:32:10 PM PDT 24 May 12 03:41:25 PM PDT 24 5703714011 ps
T1090 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3753178272 May 12 03:37:24 PM PDT 24 May 12 03:49:01 PM PDT 24 4142569882 ps
T180 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1584111375 May 12 03:21:22 PM PDT 24 May 12 03:31:32 PM PDT 24 4571564226 ps
T1091 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3019132476 May 12 03:41:09 PM PDT 24 May 12 03:52:07 PM PDT 24 3869173380 ps
T1092 /workspace/coverage/default/1.chip_sw_kmac_idle.3791905484 May 12 03:27:20 PM PDT 24 May 12 03:31:17 PM PDT 24 2261133584 ps
T1093 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3359144140 May 12 03:27:55 PM PDT 24 May 12 03:38:34 PM PDT 24 5805747602 ps
T730 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3516349198 May 12 03:52:52 PM PDT 24 May 12 04:04:43 PM PDT 24 5919182240 ps
T1094 /workspace/coverage/default/2.chip_sw_power_idle_load.2888597628 May 12 03:39:08 PM PDT 24 May 12 03:51:39 PM PDT 24 3882021612 ps
T1095 /workspace/coverage/default/2.chip_sw_kmac_smoketest.465558649 May 12 03:44:29 PM PDT 24 May 12 03:49:16 PM PDT 24 2567694658 ps
T204 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1188930148 May 12 03:31:11 PM PDT 24 May 12 04:07:45 PM PDT 24 21402619267 ps
T649 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227964712 May 12 03:49:48 PM PDT 24 May 12 03:56:56 PM PDT 24 3575331672 ps
T1096 /workspace/coverage/default/0.chip_sw_usbdev_stream.3325102705 May 12 03:19:28 PM PDT 24 May 12 04:37:02 PM PDT 24 19356167740 ps
T50 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1408249983 May 12 03:21:01 PM PDT 24 May 12 03:27:44 PM PDT 24 5028638416 ps
T379 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.689772042 May 12 03:36:56 PM PDT 24 May 12 03:46:59 PM PDT 24 5153006850 ps
T380 /workspace/coverage/default/1.chip_jtag_mem_access.3915317850 May 12 03:21:24 PM PDT 24 May 12 03:49:05 PM PDT 24 13063429304 ps
T381 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.498680670 May 12 03:13:11 PM PDT 24 May 12 03:21:15 PM PDT 24 7161071760 ps
T382 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2812267971 May 12 03:19:44 PM PDT 24 May 12 03:23:17 PM PDT 24 2372235698 ps
T383 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1861918940 May 12 03:15:35 PM PDT 24 May 12 03:32:36 PM PDT 24 5567734580 ps
T173 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3741874700 May 12 03:12:23 PM PDT 24 May 12 04:38:29 PM PDT 24 45016576882 ps
T302 /workspace/coverage/default/2.chip_plic_all_irqs_0.2415782454 May 12 03:36:10 PM PDT 24 May 12 03:55:02 PM PDT 24 5951694350 ps
T384 /workspace/coverage/default/1.chip_sw_otbn_smoketest.964221484 May 12 03:31:55 PM PDT 24 May 12 03:55:47 PM PDT 24 6146055818 ps
T385 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.176085098 May 12 03:49:17 PM PDT 24 May 12 03:56:00 PM PDT 24 3712579748 ps
T1097 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3048958389 May 12 03:20:32 PM PDT 24 May 12 03:24:20 PM PDT 24 2534566840 ps
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