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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.37 93.88 95.58 94.49 97.38 99.54


Total test records in report: 2783
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T1098 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2583834565 May 12 03:20:48 PM PDT 24 May 12 03:35:02 PM PDT 24 5265355512 ps
T1099 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2542743200 May 12 03:35:28 PM PDT 24 May 12 03:55:40 PM PDT 24 10672123408 ps
T339 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2708060954 May 12 03:43:39 PM PDT 24 May 12 03:54:21 PM PDT 24 5059872584 ps
T726 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2749142630 May 12 03:49:39 PM PDT 24 May 12 03:57:12 PM PDT 24 3992283852 ps
T67 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2453588971 May 12 03:15:12 PM PDT 24 May 12 03:19:51 PM PDT 24 2602066816 ps
T303 /workspace/coverage/default/0.chip_plic_all_irqs_0.1327869097 May 12 03:17:06 PM PDT 24 May 12 03:35:57 PM PDT 24 5690125612 ps
T51 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.989923448 May 12 03:14:42 PM PDT 24 May 12 03:44:58 PM PDT 24 19928223848 ps
T1100 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3137579654 May 12 03:33:12 PM PDT 24 May 12 03:40:10 PM PDT 24 6433847432 ps
T698 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270783397 May 12 03:45:06 PM PDT 24 May 12 03:51:31 PM PDT 24 3692632132 ps
T1101 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2167347122 May 12 03:48:12 PM PDT 24 May 12 03:58:59 PM PDT 24 5245363324 ps
T682 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1647271971 May 12 03:48:19 PM PDT 24 May 12 03:57:54 PM PDT 24 5006730454 ps
T1102 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1165091750 May 12 03:42:13 PM PDT 24 May 12 04:09:40 PM PDT 24 8077039080 ps
T1103 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3164129863 May 12 03:28:47 PM PDT 24 May 12 03:38:52 PM PDT 24 4594192246 ps
T1104 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1353141956 May 12 03:20:23 PM PDT 24 May 12 03:30:45 PM PDT 24 4529160800 ps
T301 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1215833106 May 12 03:17:11 PM PDT 24 May 12 03:38:19 PM PDT 24 6072756008 ps
T49 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2030563695 May 12 03:16:40 PM PDT 24 May 12 03:20:46 PM PDT 24 2607178126 ps
T371 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1694542375 May 12 03:25:03 PM PDT 24 May 12 04:23:26 PM PDT 24 18110217056 ps
T43 /workspace/coverage/default/0.rom_e2e_smoke.3074660466 May 12 03:21:51 PM PDT 24 May 12 04:43:17 PM PDT 24 17703558870 ps
T372 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3790788519 May 12 03:14:45 PM PDT 24 May 12 03:28:13 PM PDT 24 7789072234 ps
T373 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2132887512 May 12 03:14:57 PM PDT 24 May 12 03:27:51 PM PDT 24 5970003508 ps
T374 /workspace/coverage/default/0.chip_sw_example_manufacturer.963449587 May 12 03:14:12 PM PDT 24 May 12 03:18:30 PM PDT 24 2817118756 ps
T375 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.51653880 May 12 03:23:33 PM PDT 24 May 12 03:28:04 PM PDT 24 2683077120 ps
T328 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2981884040 May 12 03:33:36 PM PDT 24 May 12 03:43:56 PM PDT 24 3940015656 ps
T376 /workspace/coverage/default/90.chip_sw_all_escalation_resets.836308259 May 12 03:52:26 PM PDT 24 May 12 04:01:52 PM PDT 24 6199394300 ps
T377 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3991132 May 12 03:13:25 PM PDT 24 May 12 03:26:30 PM PDT 24 4231045128 ps
T264 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.609865312 May 12 03:38:39 PM PDT 24 May 12 03:42:52 PM PDT 24 2150909660 ps
T1105 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.414501360 May 12 03:28:36 PM PDT 24 May 12 03:39:44 PM PDT 24 4814024376 ps
T1106 /workspace/coverage/default/0.chip_sw_edn_kat.2550206870 May 12 03:15:36 PM PDT 24 May 12 03:26:01 PM PDT 24 3572618998 ps
T207 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2047949111 May 12 03:23:09 PM PDT 24 May 12 04:48:43 PM PDT 24 47484812814 ps
T695 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831252356 May 12 03:48:18 PM PDT 24 May 12 03:55:34 PM PDT 24 3194393074 ps
T1107 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.205061650 May 12 03:25:21 PM PDT 24 May 12 03:45:09 PM PDT 24 5236607928 ps
T1108 /workspace/coverage/default/0.chip_sw_uart_tx_rx.3063784999 May 12 03:14:14 PM PDT 24 May 12 03:25:43 PM PDT 24 4362888850 ps
T1109 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1333849102 May 12 03:19:17 PM PDT 24 May 12 03:23:52 PM PDT 24 2580480000 ps
T1110 /workspace/coverage/default/2.chip_tap_straps_rma.762241017 May 12 03:38:21 PM PDT 24 May 12 03:45:38 PM PDT 24 5334612814 ps
T229 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2957072639 May 12 03:43:12 PM PDT 24 May 12 03:53:08 PM PDT 24 4861910220 ps
T1111 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1153860183 May 12 03:43:39 PM PDT 24 May 12 03:52:14 PM PDT 24 6503995788 ps
T1112 /workspace/coverage/default/0.chip_sw_aes_masking_off.2777957239 May 12 03:13:11 PM PDT 24 May 12 03:17:31 PM PDT 24 2692226987 ps
T1113 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1731633922 May 12 03:13:40 PM PDT 24 May 12 03:19:26 PM PDT 24 2883618424 ps
T1114 /workspace/coverage/default/2.chip_sw_example_rom.3352132425 May 12 03:30:25 PM PDT 24 May 12 03:32:37 PM PDT 24 2335151824 ps
T1115 /workspace/coverage/default/3.chip_tap_straps_testunlock0.2141363996 May 12 03:40:11 PM PDT 24 May 12 03:45:19 PM PDT 24 3652824466 ps
T1116 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2074588956 May 12 03:46:56 PM PDT 24 May 12 03:59:19 PM PDT 24 5907684270 ps
T1117 /workspace/coverage/default/2.chip_sw_flash_init.327329081 May 12 03:32:02 PM PDT 24 May 12 04:04:46 PM PDT 24 18212381750 ps
T1118 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.32891824 May 12 03:44:07 PM PDT 24 May 12 04:08:12 PM PDT 24 8319416748 ps
T1119 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2650126760 May 12 03:13:34 PM PDT 24 May 12 03:19:23 PM PDT 24 4053446000 ps
T1120 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.408786673 May 12 03:43:41 PM PDT 24 May 12 03:51:58 PM PDT 24 4864532494 ps
T1121 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2225368639 May 12 03:37:44 PM PDT 24 May 12 03:48:50 PM PDT 24 4212610520 ps
T716 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879601189 May 12 03:44:39 PM PDT 24 May 12 03:50:09 PM PDT 24 3877097540 ps
T1122 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.426869343 May 12 03:13:19 PM PDT 24 May 12 03:17:42 PM PDT 24 3002089960 ps
T720 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2853606785 May 12 03:47:33 PM PDT 24 May 12 03:54:04 PM PDT 24 4041053312 ps
T1123 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043184681 May 12 03:41:52 PM PDT 24 May 12 03:47:49 PM PDT 24 3993118628 ps
T701 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2307209301 May 12 03:47:58 PM PDT 24 May 12 03:55:01 PM PDT 24 4141901678 ps
T727 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3288069931 May 12 03:43:09 PM PDT 24 May 12 03:50:17 PM PDT 24 3814398584 ps
T1124 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1620425908 May 12 03:20:37 PM PDT 24 May 12 03:25:32 PM PDT 24 2885321136 ps
T1125 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3703986004 May 12 03:32:39 PM PDT 24 May 12 03:38:07 PM PDT 24 4955137012 ps
T1126 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1327119326 May 12 03:14:44 PM PDT 24 May 12 03:19:21 PM PDT 24 3054245648 ps
T1127 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2460884471 May 12 03:32:36 PM PDT 24 May 12 03:55:26 PM PDT 24 9195617199 ps
T1128 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1029370213 May 12 03:14:01 PM PDT 24 May 12 03:16:09 PM PDT 24 2844692080 ps
T191 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1914576871 May 12 03:35:53 PM PDT 24 May 12 04:07:09 PM PDT 24 10228036040 ps
T1129 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2472586467 May 12 03:29:05 PM PDT 24 May 12 03:34:51 PM PDT 24 2693242315 ps
T1130 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2849069663 May 12 03:21:03 PM PDT 24 May 12 03:53:12 PM PDT 24 8060570863 ps
T1131 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4056672917 May 12 03:48:03 PM PDT 24 May 12 03:54:48 PM PDT 24 3173294004 ps
T1132 /workspace/coverage/default/2.chip_sw_aes_enc.2555729656 May 12 03:35:37 PM PDT 24 May 12 03:39:41 PM PDT 24 2928901670 ps
T1133 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3417247130 May 12 03:13:26 PM PDT 24 May 12 03:22:56 PM PDT 24 19717042500 ps
T1134 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1126405373 May 12 03:35:33 PM PDT 24 May 12 03:44:49 PM PDT 24 5186647488 ps
T192 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1441450203 May 12 03:27:28 PM PDT 24 May 12 03:54:45 PM PDT 24 8713142624 ps
T1135 /workspace/coverage/default/0.chip_sw_uart_smoketest.2847785727 May 12 03:19:26 PM PDT 24 May 12 03:22:41 PM PDT 24 1998456660 ps
T1136 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3130158860 May 12 03:13:41 PM PDT 24 May 12 04:05:37 PM PDT 24 28904055432 ps
T657 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.58494904 May 12 03:45:42 PM PDT 24 May 12 03:53:44 PM PDT 24 3932300588 ps
T692 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557068957 May 12 03:45:33 PM PDT 24 May 12 03:51:16 PM PDT 24 3674293448 ps
T305 /workspace/coverage/default/2.chip_plic_all_irqs_20.3292338430 May 12 03:36:13 PM PDT 24 May 12 03:48:39 PM PDT 24 4019558750 ps
T1137 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3679007352 May 12 03:20:43 PM PDT 24 May 12 03:28:05 PM PDT 24 5642634630 ps
T1138 /workspace/coverage/default/0.chip_sw_kmac_idle.2430383809 May 12 03:14:56 PM PDT 24 May 12 03:19:05 PM PDT 24 2448180772 ps
T1139 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.269628774 May 12 03:20:41 PM PDT 24 May 12 03:46:14 PM PDT 24 8343490580 ps
T1140 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2321983676 May 12 03:31:40 PM PDT 24 May 12 03:41:06 PM PDT 24 4194084520 ps
T320 /workspace/coverage/default/2.chip_sw_pattgen_ios.1841126062 May 12 03:32:31 PM PDT 24 May 12 03:37:34 PM PDT 24 2924280148 ps
T602 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3195541777 May 12 03:42:21 PM PDT 24 May 12 04:42:26 PM PDT 24 24808822039 ps
T1141 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.637690416 May 12 03:42:21 PM PDT 24 May 12 03:53:07 PM PDT 24 6580147682 ps
T47 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2068839181 May 12 03:28:51 PM PDT 24 May 12 03:35:43 PM PDT 24 4529750982 ps
T1142 /workspace/coverage/default/0.chip_sw_flash_init.3937800017 May 12 03:17:02 PM PDT 24 May 12 03:48:52 PM PDT 24 16507459284 ps
T1143 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2768350749 May 12 03:23:14 PM PDT 24 May 12 03:30:52 PM PDT 24 4593971396 ps
T346 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.794375098 May 12 03:13:45 PM PDT 24 May 12 03:26:00 PM PDT 24 5226873768 ps
T703 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3095485584 May 12 03:47:47 PM PDT 24 May 12 03:54:48 PM PDT 24 3676082760 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.3462333388 May 12 03:13:09 PM PDT 24 May 12 03:21:35 PM PDT 24 4479577810 ps
T1144 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2870609112 May 12 03:30:20 PM PDT 24 May 12 03:34:09 PM PDT 24 2576762909 ps
T1145 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2757783831 May 12 03:44:49 PM PDT 24 May 12 03:53:27 PM PDT 24 4395141784 ps
T130 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4265253699 May 12 03:28:13 PM PDT 24 May 12 03:35:12 PM PDT 24 5516741000 ps
T1146 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1966677631 May 12 03:39:58 PM PDT 24 May 12 03:44:40 PM PDT 24 3093245040 ps
T1147 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4007914540 May 12 03:29:05 PM PDT 24 May 12 03:40:08 PM PDT 24 4978810866 ps
T700 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3309533130 May 12 03:47:20 PM PDT 24 May 12 03:56:08 PM PDT 24 4664275736 ps
T1148 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2672503779 May 12 03:25:11 PM PDT 24 May 12 03:29:23 PM PDT 24 3006573246 ps
T1149 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.87584744 May 12 03:13:24 PM PDT 24 May 12 03:29:37 PM PDT 24 5495193931 ps
T1150 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1596201371 May 12 03:35:05 PM PDT 24 May 12 03:57:14 PM PDT 24 6320793824 ps
T1151 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2561125033 May 12 03:12:49 PM PDT 24 May 12 03:29:44 PM PDT 24 6149785696 ps
T329 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.323976198 May 12 03:29:06 PM PDT 24 May 12 03:40:42 PM PDT 24 4931645416 ps
T1152 /workspace/coverage/default/13.chip_sw_all_escalation_resets.382823544 May 12 03:44:24 PM PDT 24 May 12 03:54:00 PM PDT 24 4905305640 ps
T1153 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4278666298 May 12 03:43:17 PM PDT 24 May 12 03:50:07 PM PDT 24 3807020914 ps
T256 /workspace/coverage/default/23.chip_sw_all_escalation_resets.172657223 May 12 03:44:32 PM PDT 24 May 12 03:55:27 PM PDT 24 4561738800 ps
T1154 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3383741721 May 12 03:35:14 PM PDT 24 May 12 04:25:11 PM PDT 24 20869110489 ps
T718 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3893583340 May 12 03:44:23 PM PDT 24 May 12 03:55:01 PM PDT 24 5609711772 ps
T1155 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2275805568 May 12 03:33:10 PM PDT 24 May 12 03:44:29 PM PDT 24 5107084237 ps
T1156 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1312828344 May 12 03:48:26 PM PDT 24 May 12 04:00:41 PM PDT 24 6455906618 ps
T1157 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.559865643 May 12 03:43:39 PM PDT 24 May 12 03:51:14 PM PDT 24 3334348562 ps
T1158 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.795943458 May 12 03:42:42 PM PDT 24 May 12 03:49:29 PM PDT 24 3704660732 ps
T1159 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.964956666 May 12 03:14:13 PM PDT 24 May 12 03:23:39 PM PDT 24 4780685158 ps
T369 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3922446371 May 12 03:37:53 PM PDT 24 May 12 03:44:13 PM PDT 24 7601021296 ps
T1160 /workspace/coverage/default/2.chip_sw_aes_idle.2428545950 May 12 03:35:15 PM PDT 24 May 12 03:39:07 PM PDT 24 2248296078 ps
T1161 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3297759676 May 12 03:42:47 PM PDT 24 May 12 03:49:30 PM PDT 24 6598465408 ps
T1162 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3767126755 May 12 03:43:59 PM PDT 24 May 12 04:04:05 PM PDT 24 8727953481 ps
T1163 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1583726908 May 12 03:37:08 PM PDT 24 May 12 03:45:42 PM PDT 24 6379020512 ps
T1164 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2682817259 May 12 03:13:39 PM PDT 24 May 12 03:25:01 PM PDT 24 5472836776 ps
T1165 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4086492543 May 12 03:36:28 PM PDT 24 May 12 03:40:46 PM PDT 24 3134639896 ps
T1166 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.100629772 May 12 03:27:23 PM PDT 24 May 12 03:35:07 PM PDT 24 9739075195 ps
T1167 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4225783221 May 12 03:37:41 PM PDT 24 May 12 03:52:03 PM PDT 24 5252358960 ps
T1168 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2857346415 May 12 03:32:34 PM PDT 24 May 12 03:51:31 PM PDT 24 13966199174 ps
T1169 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2709849758 May 12 03:38:35 PM PDT 24 May 12 03:50:53 PM PDT 24 4627077460 ps
T378 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3777210456 May 12 03:13:27 PM PDT 24 May 12 03:19:44 PM PDT 24 7212609288 ps
T265 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.364413566 May 12 03:37:36 PM PDT 24 May 12 03:41:42 PM PDT 24 2474016499 ps
T1170 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2323600776 May 12 03:26:56 PM PDT 24 May 12 03:31:54 PM PDT 24 3339679484 ps
T1171 /workspace/coverage/default/4.chip_tap_straps_rma.788058980 May 12 03:41:13 PM PDT 24 May 12 03:52:59 PM PDT 24 6480947374 ps
T1172 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332833768 May 12 03:52:30 PM PDT 24 May 12 03:57:54 PM PDT 24 4283874872 ps
T1173 /workspace/coverage/default/1.chip_sw_otbn_randomness.2978564097 May 12 03:25:43 PM PDT 24 May 12 03:41:17 PM PDT 24 6457762578 ps
T1174 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2181665736 May 12 03:26:41 PM PDT 24 May 12 03:31:57 PM PDT 24 3479730736 ps
T1175 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.539401537 May 12 03:40:59 PM PDT 24 May 12 03:43:56 PM PDT 24 2281732897 ps
T1176 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2677174948 May 12 03:20:43 PM PDT 24 May 12 03:25:40 PM PDT 24 3422441724 ps
T1177 /workspace/coverage/default/2.chip_tap_straps_prod.4146233720 May 12 03:37:40 PM PDT 24 May 12 03:40:45 PM PDT 24 3410784066 ps
T1178 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2982382227 May 12 03:37:52 PM PDT 24 May 12 03:52:17 PM PDT 24 6597743451 ps
T1179 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2416468178 May 12 03:36:07 PM PDT 24 May 12 03:41:12 PM PDT 24 3027632966 ps
T1180 /workspace/coverage/default/2.chip_sw_aes_smoketest.2433001777 May 12 03:39:38 PM PDT 24 May 12 03:42:47 PM PDT 24 2299859144 ps
T1181 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3181229962 May 12 03:21:12 PM PDT 24 May 12 03:40:32 PM PDT 24 6335950480 ps
T1182 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2446721170 May 12 03:29:17 PM PDT 24 May 12 03:40:11 PM PDT 24 4412408044 ps
T705 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3630856983 May 12 03:49:22 PM PDT 24 May 12 04:00:43 PM PDT 24 5142443482 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1116431570 May 12 03:12:55 PM PDT 24 May 12 03:20:22 PM PDT 24 5221972764 ps
T68 /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3617961936 May 12 04:01:37 PM PDT 24 May 12 04:01:44 PM PDT 24 55957824 ps
T69 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.254771142 May 12 03:58:37 PM PDT 24 May 12 03:58:52 PM PDT 24 124294544 ps
T70 /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.803026636 May 12 04:05:41 PM PDT 24 May 12 04:05:56 PM PDT 24 262197712 ps
T76 /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2029726211 May 12 04:05:24 PM PDT 24 May 12 04:06:29 PM PDT 24 3455444195 ps
T75 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.252184519 May 12 04:05:31 PM PDT 24 May 12 04:11:06 PM PDT 24 6674487463 ps
T135 /workspace/coverage/cover_reg_top/4.chip_csr_rw.2289291365 May 12 03:51:12 PM PDT 24 May 12 03:58:32 PM PDT 24 5853616496 ps
T335 /workspace/coverage/cover_reg_top/7.chip_csr_rw.1737167045 May 12 03:52:22 PM PDT 24 May 12 03:58:20 PM PDT 24 4474664140 ps
T345 /workspace/coverage/cover_reg_top/61.xbar_smoke.1546261523 May 12 04:01:45 PM PDT 24 May 12 04:01:53 PM PDT 24 54119693 ps
T414 /workspace/coverage/cover_reg_top/21.xbar_random.2634013545 May 12 03:55:38 PM PDT 24 May 12 03:56:28 PM PDT 24 525808298 ps
T412 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1349369374 May 12 03:59:56 PM PDT 24 May 12 04:03:00 PM PDT 24 2791873959 ps
T503 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.29337430 May 12 04:07:23 PM PDT 24 May 12 04:21:07 PM PDT 24 47801626384 ps
T427 /workspace/coverage/cover_reg_top/20.xbar_random.1866740018 May 12 03:55:20 PM PDT 24 May 12 03:56:40 PM PDT 24 2270272023 ps
T512 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.823260676 May 12 04:02:03 PM PDT 24 May 12 04:04:46 PM PDT 24 1231064029 ps
T413 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.586897072 May 12 03:52:12 PM PDT 24 May 12 04:00:45 PM PDT 24 6412980585 ps
T502 /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1001696640 May 12 04:02:01 PM PDT 24 May 12 04:07:11 PM PDT 24 26653757254 ps
T509 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.4029529122 May 12 04:07:00 PM PDT 24 May 12 04:09:04 PM PDT 24 555022618 ps
T504 /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2865622263 May 12 04:06:09 PM PDT 24 May 12 04:06:24 PM PDT 24 103362201 ps
T483 /workspace/coverage/cover_reg_top/29.xbar_same_source.3392505364 May 12 03:57:10 PM PDT 24 May 12 03:57:24 PM PDT 24 325492460 ps
T397 /workspace/coverage/cover_reg_top/34.xbar_same_source.2894428420 May 12 03:58:01 PM PDT 24 May 12 03:58:35 PM PDT 24 464603954 ps
T514 /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2282592378 May 12 04:00:23 PM PDT 24 May 12 04:03:35 PM PDT 24 9926066153 ps
T741 /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.745124372 May 12 04:01:44 PM PDT 24 May 12 04:05:34 PM PDT 24 12013409858 ps
T398 /workspace/coverage/cover_reg_top/31.xbar_stress_all.2113600600 May 12 03:57:36 PM PDT 24 May 12 04:02:25 PM PDT 24 6439098397 ps
T399 /workspace/coverage/cover_reg_top/50.xbar_random.2742212247 May 12 04:00:20 PM PDT 24 May 12 04:01:49 PM PDT 24 2237665348 ps
T1183 /workspace/coverage/cover_reg_top/56.xbar_smoke.2648047557 May 12 04:01:06 PM PDT 24 May 12 04:01:17 PM PDT 24 213662599 ps
T505 /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2899756230 May 12 03:54:27 PM PDT 24 May 12 03:56:15 PM PDT 24 8800607019 ps
T136 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2219917460 May 12 03:52:15 PM PDT 24 May 12 04:51:23 PM PDT 24 31149749536 ps
T422 /workspace/coverage/cover_reg_top/14.xbar_stress_all.3374780385 May 12 03:54:01 PM PDT 24 May 12 03:59:27 PM PDT 24 7190750035 ps
T511 /workspace/coverage/cover_reg_top/98.xbar_random.1854106828 May 12 04:07:14 PM PDT 24 May 12 04:07:42 PM PDT 24 309366211 ps
T441 /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3207901554 May 12 04:00:39 PM PDT 24 May 12 04:09:39 PM PDT 24 34494425573 ps
T515 /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.617007827 May 12 04:00:38 PM PDT 24 May 12 04:01:15 PM PDT 24 378590398 ps
T507 /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3133993577 May 12 04:04:01 PM PDT 24 May 12 04:05:33 PM PDT 24 8296925501 ps
T501 /workspace/coverage/cover_reg_top/15.chip_tl_errors.1003352449 May 12 03:54:06 PM PDT 24 May 12 03:58:17 PM PDT 24 3543602758 ps
T558 /workspace/coverage/cover_reg_top/79.xbar_smoke.2435015386 May 12 04:04:23 PM PDT 24 May 12 04:04:33 PM PDT 24 242077386 ps
T508 /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3902781073 May 12 04:02:46 PM PDT 24 May 12 04:03:38 PM PDT 24 530423923 ps
T510 /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.4030608570 May 12 03:51:12 PM PDT 24 May 12 03:52:00 PM PDT 24 1035427307 ps
T591 /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2944607472 May 12 04:06:40 PM PDT 24 May 12 04:08:09 PM PDT 24 7997636393 ps
T506 /workspace/coverage/cover_reg_top/28.xbar_random.3483263683 May 12 03:56:51 PM PDT 24 May 12 03:57:16 PM PDT 24 648061024 ps
T774 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2776687791 May 12 03:57:22 PM PDT 24 May 12 03:58:20 PM PDT 24 181481460 ps
T607 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1161322831 May 12 03:57:57 PM PDT 24 May 12 04:00:27 PM PDT 24 1920731731 ps
T748 /workspace/coverage/cover_reg_top/49.xbar_access_same_device.4121522838 May 12 04:00:14 PM PDT 24 May 12 04:00:54 PM PDT 24 570200289 ps
T1184 /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1394555602 May 12 03:55:51 PM PDT 24 May 12 03:57:14 PM PDT 24 6995527595 ps
T756 /workspace/coverage/cover_reg_top/86.xbar_access_same_device.110753557 May 12 04:05:33 PM PDT 24 May 12 04:06:38 PM PDT 24 1467398303 ps
T1185 /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3211506846 May 12 03:54:18 PM PDT 24 May 12 03:54:42 PM PDT 24 495839660 ps
T473 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.428692630 May 12 03:53:00 PM PDT 24 May 12 03:57:51 PM PDT 24 782201690 ps
T554 /workspace/coverage/cover_reg_top/99.xbar_smoke.369856581 May 12 04:07:40 PM PDT 24 May 12 04:07:49 PM PDT 24 166739819 ps
T550 /workspace/coverage/cover_reg_top/5.xbar_same_source.2572779226 May 12 03:51:15 PM PDT 24 May 12 03:51:45 PM PDT 24 927523337 ps
T1186 /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1429066376 May 12 03:57:24 PM PDT 24 May 12 03:57:31 PM PDT 24 54314653 ps
T137 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1419395367 May 12 03:53:13 PM PDT 24 May 12 04:21:39 PM PDT 24 15447455911 ps
T513 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.4157816130 May 12 03:59:10 PM PDT 24 May 12 04:09:13 PM PDT 24 15808604517 ps
T1187 /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2493987527 May 12 04:06:44 PM PDT 24 May 12 04:08:24 PM PDT 24 9074642941 ps
T416 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1960553530 May 12 03:54:40 PM PDT 24 May 12 04:04:19 PM PDT 24 11663855634 ps
T601 /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1740157254 May 12 04:02:42 PM PDT 24 May 12 04:03:01 PM PDT 24 131152915 ps
T545 /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2386815453 May 12 04:03:10 PM PDT 24 May 12 04:04:42 PM PDT 24 7680836008 ps
T770 /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1929592323 May 12 04:00:07 PM PDT 24 May 12 04:01:37 PM PDT 24 5025684986 ps
T772 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.198703671 May 12 03:58:28 PM PDT 24 May 12 04:00:17 PM PDT 24 5837142369 ps
T746 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2584443025 May 12 04:07:00 PM PDT 24 May 12 04:08:42 PM PDT 24 389310050 ps
T439 /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3917650682 May 12 04:02:20 PM PDT 24 May 12 04:02:58 PM PDT 24 406201177 ps
T609 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1542864441 May 12 03:57:31 PM PDT 24 May 12 04:10:32 PM PDT 24 16375316849 ps
T1188 /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2407639457 May 12 03:55:20 PM PDT 24 May 12 03:56:37 PM PDT 24 4246291385 ps
T579 /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2344247813 May 12 03:55:32 PM PDT 24 May 12 03:55:38 PM PDT 24 31722458 ps
T587 /workspace/coverage/cover_reg_top/76.xbar_same_source.2448448199 May 12 04:04:02 PM PDT 24 May 12 04:04:24 PM PDT 24 627906080 ps
T751 /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1952182750 May 12 04:02:58 PM PDT 24 May 12 04:04:22 PM PDT 24 1757952824 ps
T1189 /workspace/coverage/cover_reg_top/88.xbar_smoke.1924220146 May 12 04:05:45 PM PDT 24 May 12 04:05:55 PM PDT 24 229719039 ps
T557 /workspace/coverage/cover_reg_top/75.xbar_same_source.3676206154 May 12 04:03:53 PM PDT 24 May 12 04:04:33 PM PDT 24 535087472 ps
T531 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.421987923 May 12 04:01:54 PM PDT 24 May 12 04:07:12 PM PDT 24 4938651112 ps
T737 /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.783584408 May 12 04:06:28 PM PDT 24 May 12 04:08:06 PM PDT 24 5496678664 ps
T585 /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1316186443 May 12 04:03:22 PM PDT 24 May 12 04:04:47 PM PDT 24 8114008330 ps
T570 /workspace/coverage/cover_reg_top/77.xbar_stress_all.3304893041 May 12 04:04:13 PM PDT 24 May 12 04:05:16 PM PDT 24 528142863 ps
T333 /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3394940283 May 12 03:51:07 PM PDT 24 May 12 04:46:24 PM PDT 24 30393168624 ps
T1190 /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1340665879 May 12 03:53:25 PM PDT 24 May 12 03:53:50 PM PDT 24 512956820 ps
T434 /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3364595485 May 12 04:03:50 PM PDT 24 May 12 04:05:41 PM PDT 24 2052378730 ps
T336 /workspace/coverage/cover_reg_top/17.chip_csr_rw.472297325 May 12 03:54:50 PM PDT 24 May 12 04:05:25 PM PDT 24 5295097750 ps
T1191 /workspace/coverage/cover_reg_top/84.xbar_random.3689469249 May 12 04:05:21 PM PDT 24 May 12 04:05:34 PM PDT 24 255597694 ps
T581 /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.4267185112 May 12 03:52:00 PM PDT 24 May 12 03:52:10 PM PDT 24 77124463 ps
T1192 /workspace/coverage/cover_reg_top/57.xbar_smoke.3167363931 May 12 04:01:14 PM PDT 24 May 12 04:01:24 PM PDT 24 202360751 ps
T1193 /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1288401147 May 12 04:03:05 PM PDT 24 May 12 04:04:19 PM PDT 24 6924587815 ps
T795 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2921277813 May 12 04:03:01 PM PDT 24 May 12 04:03:14 PM PDT 24 90941642 ps
T592 /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2876916066 May 12 04:01:31 PM PDT 24 May 12 04:02:59 PM PDT 24 8454752512 ps
T444 /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2626665603 May 12 04:03:20 PM PDT 24 May 12 04:03:44 PM PDT 24 169076166 ps
T484 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.4146906508 May 12 04:02:18 PM PDT 24 May 12 04:09:24 PM PDT 24 2891753445 ps
T523 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3210292896 May 12 04:01:30 PM PDT 24 May 12 04:03:21 PM PDT 24 1086381193 ps
T538 /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2156809564 May 12 03:52:21 PM PDT 24 May 12 03:59:13 PM PDT 24 38973448814 ps
T743 /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.824424185 May 12 03:58:19 PM PDT 24 May 12 04:19:37 PM PDT 24 74864612715 ps
T646 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2145873651 May 12 04:00:04 PM PDT 24 May 12 04:04:07 PM PDT 24 840084772 ps
T462 /workspace/coverage/cover_reg_top/25.xbar_stress_all.2299618473 May 12 03:56:32 PM PDT 24 May 12 03:57:25 PM PDT 24 596967772 ps
T529 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3412362766 May 12 04:05:59 PM PDT 24 May 12 04:06:23 PM PDT 24 176224433 ps
T777 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.650205359 May 12 04:00:42 PM PDT 24 May 12 04:01:34 PM PDT 24 173140363 ps
T564 /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2917450332 May 12 04:05:46 PM PDT 24 May 12 04:05:53 PM PDT 24 45894787 ps
T423 /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3242208153 May 12 04:01:15 PM PDT 24 May 12 04:01:50 PM PDT 24 336841354 ps
T742 /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1550972706 May 12 03:56:29 PM PDT 24 May 12 03:56:51 PM PDT 24 359865499 ps
T488 /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.878329850 May 12 04:06:00 PM PDT 24 May 12 04:29:09 PM PDT 24 74865405404 ps
T769 /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.100090637 May 12 03:55:55 PM PDT 24 May 12 03:57:06 PM PDT 24 1385300245 ps
T1194 /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.1334135335 May 12 03:52:41 PM PDT 24 May 12 03:52:50 PM PDT 24 105030675 ps
T1195 /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2191923447 May 12 03:56:06 PM PDT 24 May 12 03:58:45 PM PDT 24 9142867057 ps
T749 /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1709414607 May 12 03:55:08 PM PDT 24 May 12 03:55:37 PM PDT 24 279042016 ps
T361 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3798715309 May 12 03:51:16 PM PDT 24 May 12 04:11:16 PM PDT 24 13989562230 ps
T491 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.4133417080 May 12 03:55:19 PM PDT 24 May 12 04:05:49 PM PDT 24 53513185389 ps
T494 /workspace/coverage/cover_reg_top/37.xbar_random.1890740738 May 12 03:58:26 PM PDT 24 May 12 03:59:47 PM PDT 24 2317072196 ps
T431 /workspace/coverage/cover_reg_top/4.xbar_same_source.3613502415 May 12 03:51:11 PM PDT 24 May 12 03:52:33 PM PDT 24 2522856815 ps
T533 /workspace/coverage/cover_reg_top/73.xbar_random.2023656888 May 12 04:03:36 PM PDT 24 May 12 04:04:31 PM PDT 24 609430564 ps
T541 /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1171390966 May 12 04:06:05 PM PDT 24 May 12 04:06:21 PM PDT 24 140633384 ps
T642 /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1135158161 May 12 03:54:44 PM PDT 24 May 12 04:40:07 PM PDT 24 147017097929 ps
T588 /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.2176079161 May 12 03:51:26 PM PDT 24 May 12 03:53:02 PM PDT 24 9751821339 ps
T757 /workspace/coverage/cover_reg_top/33.xbar_access_same_device.644747267 May 12 03:57:50 PM PDT 24 May 12 03:59:56 PM PDT 24 2950864448 ps
T738 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2678206151 May 12 04:05:45 PM PDT 24 May 12 04:41:50 PM PDT 24 119279195907 ps
T428 /workspace/coverage/cover_reg_top/65.xbar_stress_all.44579262 May 12 04:02:27 PM PDT 24 May 12 04:03:55 PM PDT 24 2273723462 ps
T420 /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1203457304 May 12 04:04:48 PM PDT 24 May 12 04:46:51 PM PDT 24 134773709819 ps
T534 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3252356100 May 12 04:06:16 PM PDT 24 May 12 04:24:52 PM PDT 24 95673905930 ps
T589 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3765297518 May 12 04:07:13 PM PDT 24 May 12 04:08:22 PM PDT 24 5618996268 ps
T1196 /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3090130329 May 12 03:58:35 PM PDT 24 May 12 03:58:43 PM PDT 24 43677397 ps
T1197 /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3745123219 May 12 03:59:57 PM PDT 24 May 12 04:02:03 PM PDT 24 6511627463 ps
T739 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2354558097 May 12 03:58:54 PM PDT 24 May 12 04:00:36 PM PDT 24 1339991682 ps
T744 /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3869932198 May 12 04:05:26 PM PDT 24 May 12 04:35:33 PM PDT 24 101357313385 ps
T569 /workspace/coverage/cover_reg_top/13.xbar_same_source.3045834312 May 12 03:53:48 PM PDT 24 May 12 03:54:23 PM PDT 24 1055433597 ps
T568 /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1956956316 May 12 03:50:42 PM PDT 24 May 12 03:56:44 PM PDT 24 19808768893 ps
T418 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1804745879 May 12 04:06:43 PM PDT 24 May 12 04:19:38 PM PDT 24 45603846111 ps
T542 /workspace/coverage/cover_reg_top/53.xbar_random.2656600487 May 12 04:00:40 PM PDT 24 May 12 04:01:13 PM PDT 24 817464786 ps
T532 /workspace/coverage/cover_reg_top/11.xbar_same_source.2287706854 May 12 03:53:16 PM PDT 24 May 12 03:54:17 PM PDT 24 1797633747 ps
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