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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.41 95.32 93.80 91.97 94.43 97.38 99.54


Total test records in report: 2731
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T233 /workspace/coverage/default/1.chip_sw_power_sleep_load.3309320384 May 14 03:39:02 PM PDT 24 May 14 03:46:46 PM PDT 24 4484491200 ps
T679 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1769461998 May 14 03:48:17 PM PDT 24 May 14 03:56:45 PM PDT 24 3063136554 ps
T1032 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.531539388 May 14 03:51:21 PM PDT 24 May 14 03:55:45 PM PDT 24 2945099180 ps
T1033 /workspace/coverage/default/0.chip_sw_example_concurrency.2346343153 May 14 03:32:39 PM PDT 24 May 14 03:36:59 PM PDT 24 2477008640 ps
T1034 /workspace/coverage/default/4.chip_tap_straps_rma.2002260918 May 14 03:52:59 PM PDT 24 May 14 03:56:31 PM PDT 24 3147344287 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3581000121 May 14 03:31:38 PM PDT 24 May 14 03:36:56 PM PDT 24 2645539711 ps
T104 /workspace/coverage/default/0.chip_sw_alert_test.916597433 May 14 03:37:52 PM PDT 24 May 14 03:42:47 PM PDT 24 3598288372 ps
T1035 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3483487874 May 14 03:48:40 PM PDT 24 May 14 03:56:59 PM PDT 24 3836392208 ps
T773 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366361534 May 14 03:59:22 PM PDT 24 May 14 04:06:44 PM PDT 24 3573100070 ps
T658 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1813527398 May 14 03:34:11 PM PDT 24 May 14 03:43:07 PM PDT 24 5032407248 ps
T732 /workspace/coverage/default/27.chip_sw_all_escalation_resets.805092864 May 14 03:55:50 PM PDT 24 May 14 04:09:42 PM PDT 24 4769143168 ps
T1036 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2313408828 May 14 03:36:27 PM PDT 24 May 14 03:40:24 PM PDT 24 2427538781 ps
T819 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.962298874 May 14 03:59:32 PM PDT 24 May 14 04:05:15 PM PDT 24 3578799400 ps
T275 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.655515109 May 14 03:32:53 PM PDT 24 May 14 07:02:00 PM PDT 24 76334246776 ps
T758 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3272284670 May 14 04:00:00 PM PDT 24 May 14 04:14:08 PM PDT 24 6236886378 ps
T1037 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1118459833 May 14 03:49:36 PM PDT 24 May 14 03:59:05 PM PDT 24 5103192272 ps
T170 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3372783161 May 14 03:50:34 PM PDT 24 May 14 04:57:39 PM PDT 24 19905557798 ps
T1038 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1736417511 May 14 03:41:34 PM PDT 24 May 14 03:51:06 PM PDT 24 3738876874 ps
T1039 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1805185843 May 14 03:31:35 PM PDT 24 May 14 03:40:52 PM PDT 24 4836609764 ps
T1040 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3814394851 May 14 03:54:36 PM PDT 24 May 14 04:02:34 PM PDT 24 3522152448 ps
T1041 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2816196460 May 14 03:37:38 PM PDT 24 May 14 04:03:49 PM PDT 24 7413371048 ps
T1042 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3559466825 May 14 03:40:47 PM PDT 24 May 14 03:49:04 PM PDT 24 2894067314 ps
T1043 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3848058458 May 14 04:00:09 PM PDT 24 May 14 04:10:18 PM PDT 24 5427429832 ps
T1044 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.54771256 May 14 03:50:05 PM PDT 24 May 14 03:54:11 PM PDT 24 2623537944 ps
T1045 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1014596023 May 14 03:38:44 PM PDT 24 May 14 03:49:31 PM PDT 24 3992038830 ps
T1046 /workspace/coverage/default/2.chip_sw_aes_enc.3458552190 May 14 03:51:02 PM PDT 24 May 14 03:56:51 PM PDT 24 3676947204 ps
T1047 /workspace/coverage/default/3.chip_tap_straps_testunlock0.979558333 May 14 03:51:29 PM PDT 24 May 14 04:01:39 PM PDT 24 5319891338 ps
T794 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1081698688 May 14 03:59:02 PM PDT 24 May 14 04:07:43 PM PDT 24 4912039888 ps
T1048 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3837659790 May 14 03:33:53 PM PDT 24 May 14 03:37:37 PM PDT 24 2565105755 ps
T805 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908444512 May 14 03:59:45 PM PDT 24 May 14 04:05:46 PM PDT 24 3407163836 ps
T1049 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1124862836 May 14 03:54:06 PM PDT 24 May 14 04:32:46 PM PDT 24 13354773184 ps
T1050 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4236609249 May 14 03:46:45 PM PDT 24 May 14 04:08:09 PM PDT 24 7415171540 ps
T56 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3374251857 May 14 03:36:20 PM PDT 24 May 14 03:41:53 PM PDT 24 3970569216 ps
T1051 /workspace/coverage/default/2.chip_sw_aes_idle.4155316633 May 14 03:47:06 PM PDT 24 May 14 03:51:38 PM PDT 24 2707254800 ps
T1052 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1467602919 May 14 03:32:49 PM PDT 24 May 14 03:54:12 PM PDT 24 7904926520 ps
T41 /workspace/coverage/default/1.rom_e2e_smoke.3608872319 May 14 03:44:10 PM PDT 24 May 14 04:53:35 PM PDT 24 17267393012 ps
T1053 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3067151658 May 14 04:01:06 PM PDT 24 May 14 04:09:44 PM PDT 24 3712104232 ps
T269 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3996001048 May 14 03:34:01 PM PDT 24 May 14 03:37:22 PM PDT 24 2064138893 ps
T1054 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1052528299 May 14 03:40:06 PM PDT 24 May 14 03:50:31 PM PDT 24 4820573906 ps
T759 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1905779232 May 14 03:55:09 PM PDT 24 May 14 04:03:03 PM PDT 24 3948394786 ps
T1055 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3619243722 May 14 03:33:11 PM PDT 24 May 14 03:42:34 PM PDT 24 3126411644 ps
T781 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.757181644 May 14 03:52:44 PM PDT 24 May 14 03:59:51 PM PDT 24 4211436788 ps
T1056 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.590296526 May 14 03:36:25 PM PDT 24 May 14 03:45:56 PM PDT 24 4736231550 ps
T1057 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.927234378 May 14 03:34:59 PM PDT 24 May 14 03:40:47 PM PDT 24 3612821259 ps
T1058 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.122270671 May 14 03:36:27 PM PDT 24 May 14 03:41:18 PM PDT 24 2502295176 ps
T204 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2646327428 May 14 03:34:18 PM PDT 24 May 14 03:44:39 PM PDT 24 4694330026 ps
T1059 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.19510731 May 14 03:43:28 PM PDT 24 May 14 03:51:48 PM PDT 24 4734867644 ps
T1060 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1612669459 May 14 03:39:34 PM PDT 24 May 14 04:34:53 PM PDT 24 11966265096 ps
T1061 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3934580550 May 14 03:46:39 PM PDT 24 May 14 03:52:31 PM PDT 24 3844575554 ps
T1062 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2373386808 May 14 03:49:09 PM PDT 24 May 14 03:59:47 PM PDT 24 4221458264 ps
T310 /workspace/coverage/default/2.chip_sw_pattgen_ios.4204121299 May 14 03:42:35 PM PDT 24 May 14 03:46:45 PM PDT 24 2629900232 ps
T1063 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2733831268 May 14 03:32:49 PM PDT 24 May 14 03:39:45 PM PDT 24 3415244038 ps
T1064 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1091888755 May 14 03:37:19 PM PDT 24 May 14 03:57:29 PM PDT 24 9956116612 ps
T97 /workspace/coverage/default/0.chip_sw_flash_init.735078525 May 14 03:32:43 PM PDT 24 May 14 04:16:34 PM PDT 24 26259069780 ps
T1065 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3011214155 May 14 03:32:57 PM PDT 24 May 14 03:43:40 PM PDT 24 3806788144 ps
T1066 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2463765930 May 14 03:35:15 PM PDT 24 May 14 03:39:59 PM PDT 24 3095703960 ps
T58 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4213801830 May 14 03:35:46 PM PDT 24 May 14 04:04:09 PM PDT 24 21026226092 ps
T1067 /workspace/coverage/default/4.chip_tap_straps_prod.730623318 May 14 03:52:29 PM PDT 24 May 14 04:21:47 PM PDT 24 17701390410 ps
T74 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3510759726 May 14 03:47:11 PM PDT 24 May 14 03:58:10 PM PDT 24 6697094700 ps
T1068 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3713382176 May 14 03:55:20 PM PDT 24 May 14 03:59:16 PM PDT 24 2795638020 ps
T234 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2973813861 May 14 03:49:26 PM PDT 24 May 14 03:54:17 PM PDT 24 2540848040 ps
T1069 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.212328590 May 14 03:31:35 PM PDT 24 May 14 03:34:48 PM PDT 24 1860687228 ps
T1070 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.636832974 May 14 03:47:29 PM PDT 24 May 14 04:45:05 PM PDT 24 17216106656 ps
T112 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3518027479 May 14 03:30:15 PM PDT 24 May 14 03:38:41 PM PDT 24 3855489960 ps
T1071 /workspace/coverage/default/76.chip_sw_all_escalation_resets.328830874 May 14 04:00:25 PM PDT 24 May 14 04:09:39 PM PDT 24 4095147884 ps
T821 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1291351138 May 14 03:39:20 PM PDT 24 May 14 03:46:04 PM PDT 24 3722203816 ps
T1072 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1616450807 May 14 03:30:36 PM PDT 24 May 14 03:34:35 PM PDT 24 2952824248 ps
T1073 /workspace/coverage/default/2.chip_sw_example_rom.2903609010 May 14 03:41:35 PM PDT 24 May 14 03:43:42 PM PDT 24 2335600528 ps
T710 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1634704027 May 14 03:35:46 PM PDT 24 May 14 03:40:42 PM PDT 24 3014974730 ps
T829 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2583778363 May 14 03:58:03 PM PDT 24 May 14 04:11:05 PM PDT 24 6271171480 ps
T1074 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4058562958 May 14 03:51:31 PM PDT 24 May 14 03:56:58 PM PDT 24 3188388950 ps
T1075 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3040506374 May 14 03:47:58 PM PDT 24 May 14 03:52:11 PM PDT 24 2750846990 ps
T1076 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1469739973 May 14 03:52:10 PM PDT 24 May 14 03:59:59 PM PDT 24 4689495324 ps
T800 /workspace/coverage/default/82.chip_sw_all_escalation_resets.2993741444 May 14 04:01:09 PM PDT 24 May 14 04:11:47 PM PDT 24 4813592176 ps
T1077 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.435459341 May 14 03:55:59 PM PDT 24 May 14 04:03:35 PM PDT 24 3352578096 ps
T1078 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.485049036 May 14 03:40:51 PM PDT 24 May 14 03:52:24 PM PDT 24 5087944936 ps
T1079 /workspace/coverage/default/34.chip_sw_all_escalation_resets.4157129405 May 14 03:54:29 PM PDT 24 May 14 04:06:21 PM PDT 24 5088221350 ps
T1080 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3839063678 May 14 03:32:45 PM PDT 24 May 14 03:47:47 PM PDT 24 6462628965 ps
T677 /workspace/coverage/default/2.chip_sw_edn_auto_mode.4014235175 May 14 03:47:16 PM PDT 24 May 14 04:17:38 PM PDT 24 5760275338 ps
T1081 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.582633682 May 14 04:00:05 PM PDT 24 May 14 04:06:11 PM PDT 24 3308606904 ps
T1082 /workspace/coverage/default/1.chip_sw_kmac_app_rom.645081420 May 14 03:36:41 PM PDT 24 May 14 03:40:37 PM PDT 24 2561902680 ps
T320 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3866069144 May 14 03:43:37 PM PDT 24 May 14 03:57:38 PM PDT 24 4851989048 ps
T729 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1633376450 May 14 03:37:26 PM PDT 24 May 14 04:06:11 PM PDT 24 23709913282 ps
T276 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2017993106 May 14 03:34:37 PM PDT 24 May 14 06:51:43 PM PDT 24 62801687266 ps
T1083 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3539752236 May 14 03:33:28 PM PDT 24 May 14 03:50:36 PM PDT 24 8635389400 ps
T1084 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3729061342 May 14 03:33:21 PM PDT 24 May 14 03:50:59 PM PDT 24 7156503307 ps
T68 /workspace/coverage/default/0.chip_jtag_mem_access.1500280025 May 14 03:23:14 PM PDT 24 May 14 03:48:32 PM PDT 24 12913693969 ps
T42 /workspace/coverage/default/0.rom_e2e_smoke.3772540827 May 14 03:40:25 PM PDT 24 May 14 04:54:46 PM PDT 24 17616656082 ps
T1085 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.479196999 May 14 03:44:30 PM PDT 24 May 14 03:54:02 PM PDT 24 3569263472 ps
T1086 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.956758183 May 14 03:52:16 PM PDT 24 May 14 04:01:05 PM PDT 24 7800556600 ps
T69 /workspace/coverage/default/2.chip_jtag_mem_access.2001839484 May 14 03:41:48 PM PDT 24 May 14 04:10:04 PM PDT 24 13126878733 ps
T1087 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1576813596 May 14 03:55:48 PM PDT 24 May 14 04:04:03 PM PDT 24 4486578744 ps
T246 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1658540381 May 14 03:33:36 PM PDT 24 May 14 03:48:37 PM PDT 24 6304434120 ps
T245 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1336434990 May 14 03:48:00 PM PDT 24 May 14 03:57:07 PM PDT 24 8393921708 ps
T247 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1148628307 May 14 03:55:03 PM PDT 24 May 14 04:02:24 PM PDT 24 4077303646 ps
T248 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4189616471 May 14 03:40:00 PM PDT 24 May 14 03:44:19 PM PDT 24 3264856999 ps
T249 /workspace/coverage/default/97.chip_sw_all_escalation_resets.795457690 May 14 04:00:37 PM PDT 24 May 14 04:08:43 PM PDT 24 5570390456 ps
T250 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2515173054 May 14 03:51:50 PM PDT 24 May 14 03:58:41 PM PDT 24 3347133262 ps
T251 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2077678890 May 14 03:59:31 PM PDT 24 May 14 04:06:01 PM PDT 24 3859063306 ps
T252 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1196016337 May 14 03:32:24 PM PDT 24 May 14 03:37:56 PM PDT 24 3098534488 ps
T253 /workspace/coverage/default/1.chip_plic_all_irqs_20.1276937523 May 14 03:39:47 PM PDT 24 May 14 03:52:41 PM PDT 24 4650251154 ps
T254 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.240370246 May 14 03:35:40 PM PDT 24 May 14 03:41:25 PM PDT 24 2739019572 ps
T1088 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1979305294 May 14 03:54:02 PM PDT 24 May 14 04:05:20 PM PDT 24 5625422120 ps
T811 /workspace/coverage/default/32.chip_sw_all_escalation_resets.301339847 May 14 03:56:22 PM PDT 24 May 14 04:10:51 PM PDT 24 5787727960 ps
T1089 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1440795346 May 14 03:33:19 PM PDT 24 May 14 03:53:57 PM PDT 24 7424327956 ps
T1090 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3353074136 May 14 03:36:29 PM PDT 24 May 14 04:00:47 PM PDT 24 6233717064 ps
T774 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2364886895 May 14 03:55:16 PM PDT 24 May 14 04:02:36 PM PDT 24 3943438286 ps
T828 /workspace/coverage/default/19.chip_sw_all_escalation_resets.255163059 May 14 03:54:26 PM PDT 24 May 14 04:02:51 PM PDT 24 3841291690 ps
T217 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3191181863 May 14 03:32:27 PM PDT 24 May 14 04:24:26 PM PDT 24 20886257000 ps
T1091 /workspace/coverage/default/1.chip_sw_uart_smoketest.3579681388 May 14 03:41:33 PM PDT 24 May 14 03:47:15 PM PDT 24 3206121888 ps
T1092 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4034198927 May 14 03:44:21 PM PDT 24 May 14 03:48:56 PM PDT 24 2602507416 ps
T171 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3465756693 May 14 03:40:30 PM PDT 24 May 14 04:20:37 PM PDT 24 14408901614 ps
T302 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3146710639 May 14 03:32:59 PM PDT 24 May 14 03:44:12 PM PDT 24 4619641372 ps
T1093 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3291966775 May 14 03:33:04 PM PDT 24 May 14 03:46:55 PM PDT 24 5987958500 ps
T1094 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3340286826 May 14 03:46:36 PM PDT 24 May 14 03:53:11 PM PDT 24 5929278388 ps
T1095 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1336636187 May 14 03:35:19 PM PDT 24 May 14 04:27:18 PM PDT 24 24774180608 ps
T675 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3280272649 May 14 03:33:11 PM PDT 24 May 14 04:42:20 PM PDT 24 25710041166 ps
T1096 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3071026301 May 14 03:49:06 PM PDT 24 May 14 03:53:24 PM PDT 24 2272360399 ps
T1097 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2447699960 May 14 03:35:21 PM PDT 24 May 14 03:39:34 PM PDT 24 2316308256 ps
T1098 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2082709705 May 14 03:46:54 PM PDT 24 May 14 04:05:03 PM PDT 24 6271306546 ps
T221 /workspace/coverage/default/2.chip_sw_flash_init.4140085152 May 14 03:44:20 PM PDT 24 May 14 04:16:33 PM PDT 24 17885296448 ps
T813 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4013150219 May 14 03:57:38 PM PDT 24 May 14 04:05:03 PM PDT 24 3476050170 ps
T795 /workspace/coverage/default/90.chip_sw_all_escalation_resets.511583342 May 14 03:59:42 PM PDT 24 May 14 04:09:28 PM PDT 24 6369251202 ps
T748 /workspace/coverage/default/83.chip_sw_all_escalation_resets.426416575 May 14 03:59:53 PM PDT 24 May 14 04:10:16 PM PDT 24 5223747880 ps
T1099 /workspace/coverage/default/1.chip_tap_straps_rma.63115017 May 14 03:37:57 PM PDT 24 May 14 03:44:08 PM PDT 24 5033809302 ps
T1100 /workspace/coverage/default/2.chip_sw_aes_entropy.4162044374 May 14 03:48:05 PM PDT 24 May 14 03:52:41 PM PDT 24 2988709032 ps
T1101 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.38004006 May 14 03:35:02 PM PDT 24 May 14 03:40:52 PM PDT 24 7251545862 ps
T156 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.621918679 May 14 03:36:38 PM PDT 24 May 14 03:50:50 PM PDT 24 8117635671 ps
T1102 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1148750938 May 14 03:46:07 PM PDT 24 May 14 04:03:36 PM PDT 24 6950457614 ps
T1103 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2671828179 May 14 03:42:05 PM PDT 24 May 14 03:45:00 PM PDT 24 2388646388 ps
T1104 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2789454192 May 14 03:49:25 PM PDT 24 May 14 04:22:59 PM PDT 24 25819850378 ps
T1105 /workspace/coverage/default/2.chip_tap_straps_testunlock0.1818383590 May 14 03:50:15 PM PDT 24 May 14 03:53:23 PM PDT 24 2158227958 ps
T1106 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1497909487 May 14 03:50:21 PM PDT 24 May 14 04:07:42 PM PDT 24 10593965774 ps
T783 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3875820736 May 14 03:59:15 PM PDT 24 May 14 04:04:43 PM PDT 24 3294804412 ps
T1107 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3111919903 May 14 03:37:21 PM PDT 24 May 14 03:51:09 PM PDT 24 5372421912 ps
T1108 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.629052547 May 14 03:56:03 PM PDT 24 May 14 04:06:13 PM PDT 24 4161234490 ps
T1109 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3851410259 May 14 03:46:12 PM PDT 24 May 14 04:49:04 PM PDT 24 18559557501 ps
T1110 /workspace/coverage/default/60.chip_sw_all_escalation_resets.4112630146 May 14 03:57:24 PM PDT 24 May 14 04:08:28 PM PDT 24 6087973820 ps
T289 /workspace/coverage/default/1.chip_plic_all_irqs_0.2598563005 May 14 03:35:56 PM PDT 24 May 14 03:56:39 PM PDT 24 5879098000 ps
T1111 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1941044723 May 14 03:34:01 PM PDT 24 May 14 03:54:37 PM PDT 24 7496161718 ps
T1112 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2047329471 May 14 03:33:11 PM PDT 24 May 14 06:52:24 PM PDT 24 64230647673 ps
T1113 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.503113613 May 14 03:53:15 PM PDT 24 May 14 04:00:24 PM PDT 24 3501299640 ps
T1114 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3340455220 May 14 03:52:13 PM PDT 24 May 14 04:02:01 PM PDT 24 6076546264 ps
T1115 /workspace/coverage/default/1.chip_sw_aes_entropy.3592686808 May 14 03:33:26 PM PDT 24 May 14 03:37:43 PM PDT 24 3396404966 ps
T771 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3636960797 May 14 03:59:30 PM PDT 24 May 14 04:08:22 PM PDT 24 4435456892 ps
T1116 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3104219929 May 14 03:33:09 PM PDT 24 May 14 03:37:02 PM PDT 24 3258844160 ps
T1117 /workspace/coverage/default/0.chip_tap_straps_prod.30729433 May 14 03:33:10 PM PDT 24 May 14 03:36:11 PM PDT 24 3066616963 ps
T767 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005866704 May 14 03:52:47 PM PDT 24 May 14 04:01:51 PM PDT 24 3505349516 ps
T325 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3247872985 May 14 03:33:12 PM PDT 24 May 14 03:45:10 PM PDT 24 19421791528 ps
T1118 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1601675402 May 14 03:38:52 PM PDT 24 May 14 03:47:03 PM PDT 24 3708106968 ps
T1119 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.30502389 May 14 03:54:03 PM PDT 24 May 14 04:03:56 PM PDT 24 5724666216 ps
T1120 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3079812977 May 14 03:36:52 PM PDT 24 May 14 03:40:26 PM PDT 24 2868082008 ps
T80 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.845202705 May 14 03:39:50 PM PDT 24 May 14 03:47:11 PM PDT 24 4802852944 ps
T231 /workspace/coverage/default/1.chip_jtag_mem_access.710310461 May 14 03:30:00 PM PDT 24 May 14 03:55:09 PM PDT 24 13278004024 ps
T1121 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.240972991 May 14 03:44:50 PM PDT 24 May 14 03:53:44 PM PDT 24 3894261362 ps
T92 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3323172455 May 14 03:58:04 PM PDT 24 May 14 04:09:04 PM PDT 24 4825106826 ps
T808 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.747197834 May 14 03:59:46 PM PDT 24 May 14 04:06:23 PM PDT 24 3921679240 ps
T141 /workspace/coverage/default/0.chip_plic_all_irqs_10.3255061684 May 14 03:33:22 PM PDT 24 May 14 03:46:05 PM PDT 24 4603657000 ps
T815 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.31732570 May 14 03:58:35 PM PDT 24 May 14 04:03:58 PM PDT 24 4037943842 ps
T1122 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1440645080 May 14 03:36:00 PM PDT 24 May 14 03:44:31 PM PDT 24 3700619346 ps
T1123 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2664768855 May 14 03:34:31 PM PDT 24 May 14 03:46:03 PM PDT 24 5886605302 ps
T760 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1934435713 May 14 04:00:04 PM PDT 24 May 14 04:10:00 PM PDT 24 4845617208 ps
T1124 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1187445964 May 14 03:34:57 PM PDT 24 May 14 03:45:06 PM PDT 24 4215773592 ps
T296 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.375806184 May 14 03:32:45 PM PDT 24 May 14 03:45:52 PM PDT 24 4372118408 ps
T1125 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2706884763 May 14 03:35:06 PM PDT 24 May 14 03:46:50 PM PDT 24 6650112290 ps
T727 /workspace/coverage/default/0.chip_sw_pattgen_ios.1139148612 May 14 03:33:05 PM PDT 24 May 14 03:37:50 PM PDT 24 2302030848 ps
T1126 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.975056439 May 14 03:34:51 PM PDT 24 May 14 03:43:45 PM PDT 24 4529491382 ps
T1127 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3205319612 May 14 03:34:18 PM PDT 24 May 14 03:52:00 PM PDT 24 4893927604 ps
T1128 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3092235101 May 14 03:43:19 PM PDT 24 May 14 04:08:34 PM PDT 24 8776935148 ps
T1129 /workspace/coverage/default/0.chip_sw_otbn_randomness.2965858118 May 14 03:33:29 PM PDT 24 May 14 03:48:01 PM PDT 24 5975415972 ps
T1130 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3374807348 May 14 03:33:39 PM PDT 24 May 14 03:50:28 PM PDT 24 5544418844 ps
T1131 /workspace/coverage/default/4.chip_tap_straps_dev.2737911958 May 14 03:52:52 PM PDT 24 May 14 04:07:04 PM PDT 24 9168189773 ps
T1132 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2452529612 May 14 03:47:45 PM PDT 24 May 14 03:54:42 PM PDT 24 3204994876 ps
T691 /workspace/coverage/default/2.chip_tap_straps_dev.4095124637 May 14 03:50:16 PM PDT 24 May 14 04:02:42 PM PDT 24 6757765182 ps
T1133 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1837565674 May 14 03:59:07 PM PDT 24 May 14 04:09:33 PM PDT 24 5483736088 ps
T1134 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2920552075 May 14 03:48:17 PM PDT 24 May 14 03:58:56 PM PDT 24 6569965638 ps
T1135 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4251504404 May 14 03:33:26 PM PDT 24 May 14 03:56:16 PM PDT 24 8127244556 ps
T1136 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1441126393 May 14 03:43:24 PM PDT 24 May 14 03:47:22 PM PDT 24 2538508840 ps
T81 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2015880085 May 14 03:31:19 PM PDT 24 May 14 03:42:44 PM PDT 24 5014807224 ps
T1137 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2568533328 May 14 03:52:21 PM PDT 24 May 14 03:58:02 PM PDT 24 4546720200 ps
T75 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.24427258 May 14 03:33:37 PM PDT 24 May 14 03:45:17 PM PDT 24 6059458513 ps
T1138 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.197079735 May 14 03:38:27 PM PDT 24 May 14 03:42:36 PM PDT 24 2807096488 ps
T1139 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3505570411 May 14 03:33:57 PM PDT 24 May 14 03:46:19 PM PDT 24 4757140760 ps
T240 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.18824994 May 14 03:41:23 PM PDT 24 May 14 03:49:47 PM PDT 24 5120101860 ps
T824 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3845754352 May 14 03:57:22 PM PDT 24 May 14 04:05:12 PM PDT 24 3454772760 ps
T1140 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4120079589 May 14 03:32:53 PM PDT 24 May 14 03:39:00 PM PDT 24 4922409590 ps
T1141 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2135889018 May 14 03:31:22 PM PDT 24 May 14 03:50:34 PM PDT 24 8646113532 ps
T1142 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3719331035 May 14 03:49:06 PM PDT 24 May 14 04:04:04 PM PDT 24 5580476124 ps
T1143 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3884815410 May 14 03:31:32 PM PDT 24 May 14 03:41:48 PM PDT 24 4274226632 ps
T1144 /workspace/coverage/default/2.chip_sw_power_sleep_load.30739173 May 14 03:50:02 PM PDT 24 May 14 03:59:50 PM PDT 24 9664477336 ps
T796 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3573452647 May 14 03:59:47 PM PDT 24 May 14 04:09:12 PM PDT 24 4437528420 ps
T33 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1681739809 May 14 03:33:33 PM PDT 24 May 14 03:39:01 PM PDT 24 3311077584 ps
T1145 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3340936010 May 14 03:32:05 PM PDT 24 May 14 03:49:29 PM PDT 24 7186583800 ps
T725 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4252895134 May 14 03:36:19 PM PDT 24 May 14 03:53:21 PM PDT 24 5025548344 ps
T39 /workspace/coverage/default/1.chip_sw_spi_device_tpm.2337864380 May 14 03:33:53 PM PDT 24 May 14 03:38:48 PM PDT 24 3254965100 ps
T1146 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3374819133 May 14 03:51:34 PM PDT 24 May 14 03:56:42 PM PDT 24 3419039466 ps
T53 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.839771768 May 14 03:33:35 PM PDT 24 May 14 03:41:53 PM PDT 24 5397693092 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2580989102 May 14 03:31:56 PM PDT 24 May 14 03:38:30 PM PDT 24 5679016260 ps
T309 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.753330256 May 14 03:33:54 PM PDT 24 May 14 03:41:49 PM PDT 24 3638087526 ps
T381 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2565685607 May 14 03:32:34 PM PDT 24 May 14 03:43:50 PM PDT 24 5035506548 ps
T382 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3858052326 May 14 03:53:18 PM PDT 24 May 14 04:01:24 PM PDT 24 4841868889 ps
T383 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3001210917 May 14 03:56:06 PM PDT 24 May 14 04:04:44 PM PDT 24 4154549704 ps
T384 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1608490809 May 14 03:53:10 PM PDT 24 May 14 04:05:09 PM PDT 24 4425649290 ps
T270 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2281619169 May 14 03:39:15 PM PDT 24 May 14 03:42:55 PM PDT 24 2981084275 ps
T385 /workspace/coverage/default/0.chip_sw_aon_timer_irq.142687073 May 14 03:33:46 PM PDT 24 May 14 03:41:50 PM PDT 24 3884995740 ps
T386 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2723088313 May 14 03:48:05 PM PDT 24 May 14 03:52:36 PM PDT 24 2726150997 ps
T1147 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3586967475 May 14 03:33:25 PM PDT 24 May 14 03:58:39 PM PDT 24 14001644479 ps
T1148 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497493476 May 14 03:59:04 PM PDT 24 May 14 04:07:12 PM PDT 24 4207366000 ps
T1149 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1657707928 May 14 03:51:12 PM PDT 24 May 14 04:12:46 PM PDT 24 8013252550 ps
T1150 /workspace/coverage/default/1.chip_sw_example_flash.114839232 May 14 03:33:43 PM PDT 24 May 14 03:36:32 PM PDT 24 2385750998 ps
T1151 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.558289287 May 14 03:49:24 PM PDT 24 May 14 04:00:31 PM PDT 24 4578920598 ps
T1152 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2831821854 May 14 03:32:43 PM PDT 24 May 14 03:43:05 PM PDT 24 4268006934 ps
T1153 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.286260208 May 14 03:49:25 PM PDT 24 May 14 03:58:06 PM PDT 24 4131260658 ps
T195 /workspace/coverage/default/1.chip_jtag_csr_rw.377295572 May 14 03:29:52 PM PDT 24 May 14 03:49:32 PM PDT 24 10756732790 ps
T1154 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2151159293 May 14 03:33:07 PM PDT 24 May 14 03:44:35 PM PDT 24 5121680570 ps
T1155 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.611640749 May 14 03:38:18 PM PDT 24 May 14 03:59:46 PM PDT 24 10258560900 ps
T1156 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3611227346 May 14 03:46:44 PM PDT 24 May 14 03:57:06 PM PDT 24 5216923798 ps
T1157 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4027440217 May 14 03:34:39 PM PDT 24 May 14 04:03:37 PM PDT 24 20718376748 ps
T1158 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2062633187 May 14 03:30:37 PM PDT 24 May 14 03:42:11 PM PDT 24 3978301828 ps
T367 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4099090996 May 14 03:38:48 PM PDT 24 May 14 04:08:04 PM PDT 24 17714949570 ps
T784 /workspace/coverage/default/13.chip_sw_all_escalation_resets.823049259 May 14 03:52:15 PM PDT 24 May 14 03:59:30 PM PDT 24 5932723228 ps
T777 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3819880153 May 14 03:53:52 PM PDT 24 May 14 04:00:20 PM PDT 24 4334974476 ps
T1159 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3230714678 May 14 03:38:05 PM PDT 24 May 14 03:46:34 PM PDT 24 4903466032 ps
T1160 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.4247561196 May 14 03:35:41 PM PDT 24 May 14 03:50:46 PM PDT 24 7237128946 ps
T1161 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2377202756 May 14 03:36:23 PM PDT 24 May 14 03:44:03 PM PDT 24 4244201936 ps
T1162 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3899796093 May 14 03:41:26 PM PDT 24 May 14 03:48:13 PM PDT 24 3029045364 ps
T1163 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350760667 May 14 03:55:27 PM PDT 24 May 14 04:02:00 PM PDT 24 3592270450 ps
T1164 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3402301872 May 14 03:30:59 PM PDT 24 May 14 03:52:26 PM PDT 24 8476661910 ps
T1165 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2424914571 May 14 03:36:29 PM PDT 24 May 14 03:54:41 PM PDT 24 8087530600 ps
T733 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2881579989 May 14 03:57:20 PM PDT 24 May 14 04:07:35 PM PDT 24 6250812708 ps
T1166 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3072914663 May 14 03:53:07 PM PDT 24 May 14 04:18:04 PM PDT 24 8295055680 ps
T1167 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.770811600 May 14 03:52:22 PM PDT 24 May 14 04:02:55 PM PDT 24 4223616650 ps
T1168 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1788244789 May 14 03:51:18 PM PDT 24 May 14 03:56:10 PM PDT 24 2556487240 ps
T1169 /workspace/coverage/default/0.chip_sw_gpio_smoketest.4039091001 May 14 03:33:09 PM PDT 24 May 14 03:37:58 PM PDT 24 2691612269 ps
T1170 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.902556667 May 14 03:47:23 PM PDT 24 May 14 04:02:24 PM PDT 24 7316352556 ps
T1171 /workspace/coverage/default/0.chip_sw_aes_masking_off.2389476577 May 14 03:34:32 PM PDT 24 May 14 03:39:25 PM PDT 24 2419122302 ps
T1172 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1201949598 May 14 03:52:18 PM PDT 24 May 14 04:03:59 PM PDT 24 3999330668 ps
T676 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1144478008 May 14 03:40:07 PM PDT 24 May 14 04:45:33 PM PDT 24 25030157797 ps
T1173 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.639192345 May 14 03:50:09 PM PDT 24 May 14 04:06:13 PM PDT 24 6886192600 ps
T1174 /workspace/coverage/default/2.chip_sw_uart_smoketest.777038198 May 14 03:51:17 PM PDT 24 May 14 03:57:16 PM PDT 24 2701381816 ps
T1175 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3982461418 May 14 03:46:20 PM PDT 24 May 14 03:53:40 PM PDT 24 3188615468 ps
T1176 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1605752938 May 14 03:42:50 PM PDT 24 May 14 03:54:07 PM PDT 24 5722549768 ps
T1177 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1689283455 May 14 03:48:27 PM PDT 24 May 14 03:52:40 PM PDT 24 2817142280 ps
T218 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2529469786 May 14 03:48:06 PM PDT 24 May 14 04:13:54 PM PDT 24 8108937688 ps
T1178 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3115477122 May 14 03:42:53 PM PDT 24 May 14 06:42:08 PM PDT 24 63877903636 ps
T1179 /workspace/coverage/default/2.chip_sw_uart_tx_rx.182121692 May 14 03:43:13 PM PDT 24 May 14 03:53:02 PM PDT 24 4108718320 ps
T761 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2972521155 May 14 03:57:44 PM PDT 24 May 14 04:10:21 PM PDT 24 4413804616 ps
T762 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3256780917 May 14 03:58:03 PM PDT 24 May 14 04:07:25 PM PDT 24 4924444460 ps
T1180 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3235767779 May 14 03:45:39 PM PDT 24 May 14 03:49:36 PM PDT 24 2608463774 ps
T1181 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2473143310 May 14 03:32:40 PM PDT 24 May 14 03:42:50 PM PDT 24 3719104648 ps
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