Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.41 95.32 93.80 91.97 94.43 97.38 99.54


Total test records in report: 2731
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html
T25 /workspace/coverage/default/1.chip_sw_gpio.2779300877 May 14 03:32:26 PM PDT 24 May 14 03:38:51 PM PDT 24 3752568026 ps
T1182 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1216788200 May 14 03:34:05 PM PDT 24 May 14 03:40:10 PM PDT 24 2870751406 ps
T1183 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2430703813 May 14 03:45:55 PM PDT 24 May 14 04:08:21 PM PDT 24 5702422383 ps
T1184 /workspace/coverage/default/1.chip_sw_aes_idle.3972259256 May 14 03:35:32 PM PDT 24 May 14 03:39:44 PM PDT 24 3156227480 ps
T223 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3605256739 May 14 03:50:31 PM PDT 24 May 14 04:24:06 PM PDT 24 17829487549 ps
T818 /workspace/coverage/default/7.chip_sw_all_escalation_resets.4230509593 May 14 03:52:30 PM PDT 24 May 14 04:03:57 PM PDT 24 4302410120 ps
T1185 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2382453707 May 14 03:43:30 PM PDT 24 May 14 03:48:19 PM PDT 24 2751333280 ps
T1186 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1320743309 May 14 03:33:25 PM PDT 24 May 14 03:39:36 PM PDT 24 4917112020 ps
T802 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1168704827 May 14 03:55:21 PM PDT 24 May 14 04:06:38 PM PDT 24 5577293080 ps
T1187 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3700048417 May 14 03:55:04 PM PDT 24 May 14 04:04:31 PM PDT 24 4109326472 ps
T1188 /workspace/coverage/default/23.chip_sw_all_escalation_resets.100487673 May 14 03:55:36 PM PDT 24 May 14 04:08:16 PM PDT 24 5818335258 ps
T1189 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3049578152 May 14 03:52:28 PM PDT 24 May 14 04:32:21 PM PDT 24 12194246710 ps
T1190 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.778764729 May 14 03:50:54 PM PDT 24 May 14 03:59:31 PM PDT 24 4388239447 ps
T1191 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1143796149 May 14 03:37:35 PM PDT 24 May 14 03:44:54 PM PDT 24 3944306368 ps
T1192 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1078457166 May 14 03:48:15 PM PDT 24 May 14 03:57:51 PM PDT 24 4655813468 ps
T1193 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4176914086 May 14 03:33:40 PM PDT 24 May 14 03:55:52 PM PDT 24 6499471736 ps
T1194 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1452520490 May 14 04:01:11 PM PDT 24 May 14 04:10:23 PM PDT 24 4268220176 ps
T1195 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.879561839 May 14 03:48:47 PM PDT 24 May 14 04:08:25 PM PDT 24 11557552568 ps
T1196 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3158829786 May 14 03:34:36 PM PDT 24 May 14 03:59:33 PM PDT 24 7714913760 ps
T316 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3457116151 May 14 03:45:05 PM PDT 24 May 14 03:54:11 PM PDT 24 3667716456 ps
T1197 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1315704819 May 14 03:38:17 PM PDT 24 May 14 03:41:26 PM PDT 24 2573133348 ps
T308 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2770384573 May 14 03:43:07 PM PDT 24 May 14 04:00:24 PM PDT 24 5463457432 ps
T765 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2277134030 May 14 03:59:12 PM PDT 24 May 14 04:04:48 PM PDT 24 3500088088 ps
T822 /workspace/coverage/default/43.chip_sw_all_escalation_resets.848497467 May 14 03:59:16 PM PDT 24 May 14 04:12:56 PM PDT 24 6200665570 ps
T1198 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1980654086 May 14 03:34:32 PM PDT 24 May 14 03:40:13 PM PDT 24 3412538011 ps
T1199 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2465392308 May 14 03:52:43 PM PDT 24 May 14 04:32:16 PM PDT 24 13474007700 ps
T1200 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2450722573 May 14 03:44:36 PM PDT 24 May 14 03:54:05 PM PDT 24 4049112104 ps
T1201 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.96357941 May 14 03:32:38 PM PDT 24 May 14 04:25:48 PM PDT 24 28391620449 ps
T782 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1599643220 May 14 03:56:47 PM PDT 24 May 14 04:07:33 PM PDT 24 4757382656 ps
T1202 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860912260 May 14 03:55:47 PM PDT 24 May 14 04:01:34 PM PDT 24 3240627112 ps
T327 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3629438526 May 14 03:34:29 PM PDT 24 May 14 03:46:08 PM PDT 24 3915170233 ps
T196 /workspace/coverage/default/0.chip_jtag_csr_rw.840617706 May 14 03:23:19 PM PDT 24 May 14 03:58:36 PM PDT 24 18782402700 ps
T1203 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.152257244 May 14 03:33:53 PM PDT 24 May 14 03:43:14 PM PDT 24 4020280548 ps
T1204 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2398166117 May 14 03:47:16 PM PDT 24 May 14 04:07:08 PM PDT 24 5904761432 ps
T1205 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2893380181 May 14 03:44:45 PM PDT 24 May 14 03:51:10 PM PDT 24 2739833680 ps
T326 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.789048645 May 14 03:36:27 PM PDT 24 May 14 03:46:49 PM PDT 24 18460447400 ps
T222 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.332597644 May 14 03:31:35 PM PDT 24 May 14 04:08:05 PM PDT 24 25821453907 ps
T1206 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1215232499 May 14 03:39:08 PM PDT 24 May 14 04:37:26 PM PDT 24 17151180280 ps
T1207 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3489386764 May 14 03:33:01 PM PDT 24 May 14 03:44:28 PM PDT 24 4530713960 ps
T1208 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2579545400 May 14 03:51:10 PM PDT 24 May 14 03:53:45 PM PDT 24 2523446600 ps
T1209 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2136938237 May 14 03:35:47 PM PDT 24 May 14 03:45:08 PM PDT 24 6879138093 ps
T678 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1873338984 May 14 03:37:30 PM PDT 24 May 14 03:55:59 PM PDT 24 4987306436 ps
T1210 /workspace/coverage/default/0.chip_sw_kmac_entropy.3628647931 May 14 03:31:27 PM PDT 24 May 14 03:35:39 PM PDT 24 3228575400 ps
T178 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2990815076 May 14 03:39:50 PM PDT 24 May 14 03:47:25 PM PDT 24 4791989144 ps
T1211 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2598033131 May 14 03:33:03 PM PDT 24 May 14 04:26:33 PM PDT 24 11609615784 ps
T810 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.390043954 May 14 03:58:46 PM PDT 24 May 14 04:06:09 PM PDT 24 3392023318 ps
T1212 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3494461611 May 14 03:38:44 PM PDT 24 May 14 04:06:32 PM PDT 24 11429157256 ps
T701 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2369639656 May 14 04:00:22 PM PDT 24 May 14 04:08:47 PM PDT 24 4053380372 ps
T1213 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3870586467 May 14 03:35:01 PM PDT 24 May 14 03:40:25 PM PDT 24 2970024424 ps
T1214 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1737930663 May 14 03:45:54 PM PDT 24 May 14 04:08:26 PM PDT 24 9039050510 ps
T52 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.364188866 May 14 03:36:14 PM PDT 24 May 14 03:44:55 PM PDT 24 4656701876 ps
T57 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1923417105 May 14 03:43:15 PM PDT 24 May 14 03:48:04 PM PDT 24 3777555080 ps
T763 /workspace/coverage/default/45.chip_sw_all_escalation_resets.345831957 May 14 03:58:22 PM PDT 24 May 14 04:07:48 PM PDT 24 4174981240 ps
T1215 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1129338490 May 14 03:34:17 PM PDT 24 May 14 03:39:53 PM PDT 24 4114356404 ps
T1216 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1641196904 May 14 03:36:05 PM PDT 24 May 14 03:42:23 PM PDT 24 7100596856 ps
T1217 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.991808909 May 14 03:52:31 PM PDT 24 May 14 03:57:45 PM PDT 24 2311353700 ps
T1218 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2356946689 May 14 03:54:18 PM PDT 24 May 14 04:06:21 PM PDT 24 4905791234 ps
T1219 /workspace/coverage/default/0.chip_sw_csrng_kat_test.925410043 May 14 03:34:20 PM PDT 24 May 14 03:39:19 PM PDT 24 3236326594 ps
T1220 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1177788554 May 14 03:48:56 PM PDT 24 May 14 03:55:38 PM PDT 24 4530079400 ps
T1221 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1478616227 May 14 03:31:49 PM PDT 24 May 14 03:59:31 PM PDT 24 12076132084 ps
T702 /workspace/coverage/default/17.chip_sw_all_escalation_resets.398952471 May 14 03:53:33 PM PDT 24 May 14 04:04:05 PM PDT 24 4304935804 ps
T1222 /workspace/coverage/default/2.chip_sw_kmac_idle.2740324843 May 14 03:48:58 PM PDT 24 May 14 03:52:26 PM PDT 24 2130293960 ps
T343 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2644625923 May 14 03:44:15 PM PDT 24 May 14 03:55:09 PM PDT 24 4466859216 ps
T1223 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3489098389 May 14 03:34:08 PM PDT 24 May 14 04:12:36 PM PDT 24 28974388822 ps
T1224 /workspace/coverage/default/0.chip_tap_straps_dev.251575588 May 14 03:31:33 PM PDT 24 May 14 03:34:36 PM PDT 24 2676576883 ps
T298 /workspace/coverage/default/0.chip_plic_all_irqs_0.2218559825 May 14 03:32:02 PM PDT 24 May 14 03:53:58 PM PDT 24 5984436432 ps
T1225 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4073670177 May 14 03:34:36 PM PDT 24 May 14 03:42:11 PM PDT 24 4206279048 ps
T1226 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.565849305 May 14 03:51:51 PM PDT 24 May 14 03:58:11 PM PDT 24 4351581284 ps
T1227 /workspace/coverage/default/0.chip_sw_aes_enc.83252583 May 14 03:34:58 PM PDT 24 May 14 03:40:44 PM PDT 24 3428185528 ps
T1228 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3655025750 May 14 03:39:46 PM PDT 24 May 14 03:50:20 PM PDT 24 4193746130 ps
T1229 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1735317651 May 14 03:31:49 PM PDT 24 May 14 04:02:55 PM PDT 24 8392373800 ps
T241 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3514041440 May 14 03:49:59 PM PDT 24 May 14 04:02:12 PM PDT 24 6336481884 ps
T1230 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578340134 May 14 03:57:56 PM PDT 24 May 14 04:05:14 PM PDT 24 3878704600 ps
T378 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4148552488 May 14 03:37:16 PM PDT 24 May 14 04:04:38 PM PDT 24 22712513128 ps
T230 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1343247609 May 14 03:59:33 PM PDT 24 May 14 04:05:06 PM PDT 24 3653558706 ps
T1231 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2849871801 May 14 03:51:14 PM PDT 24 May 14 04:02:43 PM PDT 24 4545216856 ps
T1232 /workspace/coverage/default/2.chip_sw_aes_masking_off.2172000468 May 14 03:51:09 PM PDT 24 May 14 03:55:37 PM PDT 24 2767707187 ps
T1233 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1948841490 May 14 03:38:13 PM PDT 24 May 14 04:11:34 PM PDT 24 8178937616 ps
T1234 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3529652862 May 14 03:57:54 PM PDT 24 May 14 04:04:57 PM PDT 24 4330977384 ps
T285 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1904438404 May 14 03:44:58 PM PDT 24 May 14 04:15:25 PM PDT 24 14945163480 ps
T63 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2717052639 May 14 04:01:34 PM PDT 24 May 14 04:02:51 PM PDT 24 4038583680 ps
T64 /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.529990990 May 14 04:11:16 PM PDT 24 May 14 04:12:06 PM PDT 24 521513350 ps
T65 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4088632454 May 14 04:04:00 PM PDT 24 May 14 04:05:10 PM PDT 24 1571596646 ps
T70 /workspace/coverage/cover_reg_top/44.xbar_smoke.2203835483 May 14 04:08:58 PM PDT 24 May 14 04:09:09 PM PDT 24 211651828 ps
T79 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2991289926 May 14 04:16:13 PM PDT 24 May 14 04:18:46 PM PDT 24 301886252 ps
T113 /workspace/coverage/cover_reg_top/61.xbar_error_random.2051912590 May 14 04:11:27 PM PDT 24 May 14 04:12:17 PM PDT 24 1384742895 ps
T399 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.684582504 May 14 04:11:44 PM PDT 24 May 14 04:21:04 PM PDT 24 8738621536 ps
T401 /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3204291280 May 14 04:09:48 PM PDT 24 May 14 04:09:55 PM PDT 24 48271819 ps
T482 /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.879556651 May 14 04:12:59 PM PDT 24 May 14 04:13:14 PM PDT 24 98548970 ps
T746 /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3286361529 May 14 04:05:06 PM PDT 24 May 14 04:06:00 PM PDT 24 2883762984 ps
T479 /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1020674236 May 14 04:11:44 PM PDT 24 May 14 04:12:34 PM PDT 24 1216241047 ps
T400 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.166047362 May 14 04:14:11 PM PDT 24 May 14 04:18:30 PM PDT 24 3531698531 ps
T379 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3113901523 May 14 04:00:14 PM PDT 24 May 14 04:09:33 PM PDT 24 5309671781 ps
T478 /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3758074229 May 14 04:13:42 PM PDT 24 May 14 04:14:14 PM PDT 24 755290164 ps
T475 /workspace/coverage/cover_reg_top/62.xbar_error_random.1332427850 May 14 04:11:28 PM PDT 24 May 14 04:12:40 PM PDT 24 1957474800 ps
T484 /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3994070333 May 14 04:14:41 PM PDT 24 May 14 04:14:49 PM PDT 24 48897608 ps
T476 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3375251898 May 14 04:16:30 PM PDT 24 May 14 04:17:10 PM PDT 24 479046529 ps
T608 /workspace/coverage/cover_reg_top/10.xbar_smoke.3741508570 May 14 04:01:49 PM PDT 24 May 14 04:02:01 PM PDT 24 237146114 ps
T477 /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1842969400 May 14 04:14:40 PM PDT 24 May 14 04:23:05 PM PDT 24 13511090010 ps
T546 /workspace/coverage/cover_reg_top/71.xbar_smoke.2002829350 May 14 04:13:00 PM PDT 24 May 14 04:13:12 PM PDT 24 227536607 ps
T481 /workspace/coverage/cover_reg_top/96.xbar_random.2148054777 May 14 04:16:13 PM PDT 24 May 14 04:16:39 PM PDT 24 233261034 ps
T187 /workspace/coverage/cover_reg_top/14.chip_csr_rw.3261450755 May 14 04:03:37 PM PDT 24 May 14 04:13:14 PM PDT 24 5323638934 ps
T598 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.4085386121 May 14 04:08:49 PM PDT 24 May 14 04:09:58 PM PDT 24 3687204325 ps
T1235 /workspace/coverage/cover_reg_top/57.xbar_smoke.2576240035 May 14 04:10:48 PM PDT 24 May 14 04:10:55 PM PDT 24 50404225 ps
T412 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3804952960 May 14 04:15:44 PM PDT 24 May 14 04:18:41 PM PDT 24 479019167 ps
T468 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3312196593 May 14 04:10:45 PM PDT 24 May 14 04:26:26 PM PDT 24 77232583454 ps
T394 /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2373760027 May 14 04:02:24 PM PDT 24 May 14 04:02:32 PM PDT 24 49765349 ps
T483 /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.454743632 May 14 04:13:07 PM PDT 24 May 14 04:26:45 PM PDT 24 67993600921 ps
T398 /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1315187434 May 14 04:12:59 PM PDT 24 May 14 04:19:11 PM PDT 24 18748278169 ps
T181 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3994835792 May 14 03:59:49 PM PDT 24 May 14 04:03:28 PM PDT 24 4232670117 ps
T1236 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1100840447 May 14 04:16:17 PM PDT 24 May 14 04:16:31 PM PDT 24 206656590 ps
T403 /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1649107064 May 14 04:07:23 PM PDT 24 May 14 04:09:07 PM PDT 24 1922872915 ps
T892 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2226610976 May 14 04:07:26 PM PDT 24 May 14 04:07:40 PM PDT 24 7137508 ps
T480 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3059344215 May 14 04:01:28 PM PDT 24 May 14 04:06:36 PM PDT 24 8116428429 ps
T502 /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3543477387 May 14 04:03:06 PM PDT 24 May 14 04:03:34 PM PDT 24 182933014 ps
T853 /workspace/coverage/cover_reg_top/67.xbar_error_random.1782944814 May 14 04:12:03 PM PDT 24 May 14 04:13:18 PM PDT 24 1807257295 ps
T396 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3021930899 May 14 04:07:12 PM PDT 24 May 14 04:07:50 PM PDT 24 355371004 ps
T397 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.344526933 May 14 04:15:48 PM PDT 24 May 14 04:33:56 PM PDT 24 17250443662 ps
T891 /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.761834192 May 14 04:10:46 PM PDT 24 May 14 04:12:24 PM PDT 24 8435395650 ps
T599 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2410794453 May 14 04:11:11 PM PDT 24 May 14 04:13:18 PM PDT 24 1571874934 ps
T1237 /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1954753354 May 14 04:16:20 PM PDT 24 May 14 04:17:55 PM PDT 24 5045369946 ps
T730 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2067054772 May 14 04:04:50 PM PDT 24 May 14 04:07:55 PM PDT 24 471883322 ps
T462 /workspace/coverage/cover_reg_top/2.xbar_random.2620016034 May 14 03:59:52 PM PDT 24 May 14 04:01:33 PM PDT 24 2550042644 ps
T688 /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.4226382037 May 14 04:06:49 PM PDT 24 May 14 04:14:15 PM PDT 24 11817070674 ps
T724 /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3363588267 May 14 04:10:18 PM PDT 24 May 14 04:12:00 PM PDT 24 6013920994 ps
T844 /workspace/coverage/cover_reg_top/61.xbar_access_same_device.978162246 May 14 04:11:25 PM PDT 24 May 14 04:12:01 PM PDT 24 393976780 ps
T387 /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3504179982 May 14 04:05:59 PM PDT 24 May 14 04:06:20 PM PDT 24 180129662 ps
T703 /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3332363687 May 14 04:11:18 PM PDT 24 May 14 04:11:25 PM PDT 24 39844243 ps
T556 /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.1860043916 May 14 04:10:02 PM PDT 24 May 14 04:11:06 PM PDT 24 1299995709 ps
T830 /workspace/coverage/cover_reg_top/51.xbar_stress_all.1706274892 May 14 04:10:04 PM PDT 24 May 14 04:11:32 PM PDT 24 2089054286 ps
T1238 /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2681062741 May 14 04:05:44 PM PDT 24 May 14 04:06:21 PM PDT 24 771359180 ps
T1239 /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.288958422 May 14 03:59:58 PM PDT 24 May 14 04:04:53 PM PDT 24 8100767349 ps
T455 /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.4088854085 May 14 04:14:36 PM PDT 24 May 14 04:16:22 PM PDT 24 9704467811 ps
T1240 /workspace/coverage/cover_reg_top/4.xbar_error_random.1921080934 May 14 04:00:11 PM PDT 24 May 14 04:00:33 PM PDT 24 507294548 ps
T517 /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.293525392 May 14 04:04:58 PM PDT 24 May 14 04:09:25 PM PDT 24 22049804685 ps
T498 /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2977201637 May 14 04:03:41 PM PDT 24 May 14 04:23:24 PM PDT 24 108497262464 ps
T501 /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.158293301 May 14 04:13:34 PM PDT 24 May 14 04:24:31 PM PDT 24 33895180430 ps
T524 /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1512581198 May 14 04:15:56 PM PDT 24 May 14 04:19:22 PM PDT 24 19387309767 ps
T422 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1291515427 May 14 04:08:34 PM PDT 24 May 14 04:15:33 PM PDT 24 3006719636 ps
T491 /workspace/coverage/cover_reg_top/24.chip_tl_errors.4246661655 May 14 04:05:53 PM PDT 24 May 14 04:08:26 PM PDT 24 3223312152 ps
T831 /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2963823182 May 14 04:05:37 PM PDT 24 May 14 04:34:10 PM PDT 24 98698592847 ps
T518 /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3007986899 May 14 04:07:23 PM PDT 24 May 14 04:17:58 PM PDT 24 37105927803 ps
T1241 /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3930918714 May 14 03:59:52 PM PDT 24 May 14 04:01:22 PM PDT 24 8218254871 ps
T832 /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.4030919493 May 14 04:15:40 PM PDT 24 May 14 04:28:50 PM PDT 24 44137484378 ps
T1242 /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.838201813 May 14 04:05:47 PM PDT 24 May 14 04:07:34 PM PDT 24 9598609437 ps
T561 /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4226631629 May 14 04:06:22 PM PDT 24 May 14 04:08:05 PM PDT 24 8997161524 ps
T529 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.867781266 May 14 04:13:11 PM PDT 24 May 14 04:15:09 PM PDT 24 10652767331 ps
T850 /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3514813065 May 14 04:12:57 PM PDT 24 May 14 04:28:00 PM PDT 24 46515907082 ps
T395 /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1195979036 May 14 04:10:42 PM PDT 24 May 14 04:11:28 PM PDT 24 965845249 ps
T446 /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1428871562 May 14 04:15:27 PM PDT 24 May 14 04:22:26 PM PDT 24 20899589745 ps
T1243 /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2018525972 May 14 04:05:16 PM PDT 24 May 14 04:06:44 PM PDT 24 7369799288 ps
T1244 /workspace/coverage/cover_reg_top/16.xbar_smoke.2461951254 May 14 04:03:44 PM PDT 24 May 14 04:03:54 PM PDT 24 168989304 ps
T459 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3317868661 May 14 04:04:25 PM PDT 24 May 14 04:09:00 PM PDT 24 1295888010 ps
T610 /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3633299763 May 14 04:13:14 PM PDT 24 May 14 04:13:59 PM PDT 24 959827941 ps
T188 /workspace/coverage/cover_reg_top/0.chip_csr_rw.3313811567 May 14 03:59:40 PM PDT 24 May 14 04:11:32 PM PDT 24 6330829928 ps
T589 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2883473692 May 14 03:59:41 PM PDT 24 May 14 04:00:20 PM PDT 24 428490436 ps
T436 /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2907432023 May 14 04:03:45 PM PDT 24 May 14 04:16:37 PM PDT 24 41697894562 ps
T564 /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3745270818 May 14 04:10:02 PM PDT 24 May 14 04:28:57 PM PDT 24 107146089246 ps
T423 /workspace/coverage/cover_reg_top/80.xbar_stress_all.3015270119 May 14 04:13:59 PM PDT 24 May 14 04:20:55 PM PDT 24 10587993561 ps
T723 /workspace/coverage/cover_reg_top/11.xbar_same_source.372710884 May 14 04:02:54 PM PDT 24 May 14 04:03:18 PM PDT 24 695163197 ps
T463 /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1871082171 May 14 04:01:18 PM PDT 24 May 14 04:17:21 PM PDT 24 79748362181 ps
T416 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.445531347 May 14 04:08:19 PM PDT 24 May 14 04:09:45 PM PDT 24 1690492434 ps
T726 /workspace/coverage/cover_reg_top/38.xbar_access_same_device.527223843 May 14 04:08:20 PM PDT 24 May 14 04:09:16 PM PDT 24 683320116 ps
T562 /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.400890118 May 14 04:10:25 PM PDT 24 May 14 04:11:13 PM PDT 24 500170309 ps
T590 /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1066338163 May 14 04:04:27 PM PDT 24 May 14 04:25:13 PM PDT 24 106268510948 ps
T189 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1877744050 May 14 04:03:35 PM PDT 24 May 14 04:30:48 PM PDT 24 15304096580 ps
T1245 /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2525141649 May 14 04:00:50 PM PDT 24 May 14 04:04:45 PM PDT 24 21078987137 ps
T848 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3339601822 May 14 04:13:09 PM PDT 24 May 14 04:17:10 PM PDT 24 4039271396 ps
T858 /workspace/coverage/cover_reg_top/64.xbar_access_same_device.4092609341 May 14 04:11:46 PM PDT 24 May 14 04:12:12 PM PDT 24 248850106 ps
T514 /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3913009162 May 14 04:10:04 PM PDT 24 May 14 04:10:15 PM PDT 24 66917568 ps
T1246 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2731617022 May 14 04:10:02 PM PDT 24 May 14 04:10:26 PM PDT 24 118952755 ps
T847 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.241297093 May 14 04:08:47 PM PDT 24 May 14 04:26:37 PM PDT 24 58675276458 ps
T627 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.713428355 May 14 04:13:24 PM PDT 24 May 14 04:17:52 PM PDT 24 8084364859 ps
T1247 /workspace/coverage/cover_reg_top/57.xbar_error_random.3420448235 May 14 04:10:47 PM PDT 24 May 14 04:11:11 PM PDT 24 531028457 ps
T861 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2144679802 May 14 04:16:13 PM PDT 24 May 14 04:17:08 PM PDT 24 2911909989 ps
T337 /workspace/coverage/cover_reg_top/9.chip_csr_rw.3209575205 May 14 04:01:42 PM PDT 24 May 14 04:07:47 PM PDT 24 4458757200 ps
T470 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.971958118 May 14 04:11:18 PM PDT 24 May 14 04:22:28 PM PDT 24 36202316412 ps
T588 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3287612529 May 14 04:10:36 PM PDT 24 May 14 04:16:43 PM PDT 24 9067118859 ps
T557 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.4222293450 May 14 04:08:22 PM PDT 24 May 14 04:09:09 PM PDT 24 487110935 ps
T492 /workspace/coverage/cover_reg_top/84.xbar_random.1790188150 May 14 04:14:24 PM PDT 24 May 14 04:15:54 PM PDT 24 2220183980 ps
T849 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1434876806 May 14 04:13:27 PM PDT 24 May 14 04:28:08 PM PDT 24 51894245834 ps
T485 /workspace/coverage/cover_reg_top/12.chip_tl_errors.2992968008 May 14 04:03:02 PM PDT 24 May 14 04:10:10 PM PDT 24 4339719623 ps
T1248 /workspace/coverage/cover_reg_top/73.xbar_error_random.3987367050 May 14 04:13:25 PM PDT 24 May 14 04:13:55 PM PDT 24 753144909 ps
T432 /workspace/coverage/cover_reg_top/11.xbar_random.43813 May 14 04:02:23 PM PDT 24 May 14 04:02:49 PM PDT 24 233924419 ps
T1249 /workspace/coverage/cover_reg_top/29.xbar_error_random.554456560 May 14 04:06:39 PM PDT 24 May 14 04:07:27 PM PDT 24 574888707 ps
T1250 /workspace/coverage/cover_reg_top/83.xbar_smoke.3253896236 May 14 04:14:21 PM PDT 24 May 14 04:14:28 PM PDT 24 43097214 ps
T654 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.4239740325 May 14 04:15:00 PM PDT 24 May 14 04:20:30 PM PDT 24 2874418734 ps
T1251 /workspace/coverage/cover_reg_top/83.xbar_error_random.3844783223 May 14 04:14:23 PM PDT 24 May 14 04:14:35 PM PDT 24 217728562 ps
T409 /workspace/coverage/cover_reg_top/72.xbar_random.1114413992 May 14 04:13:04 PM PDT 24 May 14 04:13:43 PM PDT 24 397720653 ps
T441 /workspace/coverage/cover_reg_top/65.xbar_smoke.603077442 May 14 04:11:44 PM PDT 24 May 14 04:11:54 PM PDT 24 173039521 ps
T404 /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1251259612 May 14 04:15:25 PM PDT 24 May 14 04:16:41 PM PDT 24 724050173 ps
T435 /workspace/coverage/cover_reg_top/97.xbar_stress_all.3859601908 May 14 04:16:13 PM PDT 24 May 14 04:21:29 PM PDT 24 8474238864 ps
T410 /workspace/coverage/cover_reg_top/79.xbar_stress_all.3579656453 May 14 04:13:54 PM PDT 24 May 14 04:14:58 PM PDT 24 830335188 ps
T530 /workspace/coverage/cover_reg_top/21.xbar_same_source.2542950664 May 14 04:05:11 PM PDT 24 May 14 04:06:35 PM PDT 24 2209650438 ps
T671 /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.972471870 May 14 04:03:37 PM PDT 24 May 14 04:16:59 PM PDT 24 43581017937 ps
T592 /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1779740806 May 14 04:08:34 PM PDT 24 May 14 04:10:07 PM PDT 24 8210336898 ps
T1252 /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3215898433 May 14 04:08:48 PM PDT 24 May 14 04:08:55 PM PDT 24 51295244 ps
T616 /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.271214088 May 14 04:16:10 PM PDT 24 May 14 04:16:39 PM PDT 24 289536002 ps
T835 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3163773291 May 14 04:11:30 PM PDT 24 May 14 04:15:08 PM PDT 24 2976822556 ps
T839 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3775744456 May 14 04:09:01 PM PDT 24 May 14 04:23:20 PM PDT 24 16735882544 ps
T889 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2297221294 May 14 04:13:17 PM PDT 24 May 14 04:13:52 PM PDT 24 116131247 ps
T503 /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2821349056 May 14 04:10:48 PM PDT 24 May 14 04:11:32 PM PDT 24 1005639065 ps
T845 /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.537989509 May 14 04:15:15 PM PDT 24 May 14 04:40:35 PM PDT 24 91570213356 ps
T1253 /workspace/coverage/cover_reg_top/20.xbar_smoke.1828318167 May 14 04:04:46 PM PDT 24 May 14 04:04:54 PM PDT 24 159760969 ps
T618 /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3605258007 May 14 04:05:40 PM PDT 24 May 14 04:13:39 PM PDT 24 43199186414 ps
T424 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2302744039 May 14 04:06:41 PM PDT 24 May 14 04:07:37 PM PDT 24 531844896 ps
T584 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2503567109 May 14 04:02:24 PM PDT 24 May 14 04:04:29 PM PDT 24 6827058997 ps
T1254 /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1273436950 May 14 04:15:36 PM PDT 24 May 14 04:21:12 PM PDT 24 18318567856 ps
T428 /workspace/coverage/cover_reg_top/68.xbar_smoke.3056576987 May 14 04:12:20 PM PDT 24 May 14 04:12:27 PM PDT 24 47079494 ps
T1255 /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1016927626 May 14 04:11:17 PM PDT 24 May 14 04:12:22 PM PDT 24 5664280569 ps
T857 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1924532988 May 14 04:12:12 PM PDT 24 May 14 04:21:13 PM PDT 24 4538951018 ps
T431 /workspace/coverage/cover_reg_top/6.xbar_stress_all.4026665304 May 14 04:00:34 PM PDT 24 May 14 04:05:26 PM PDT 24 2821216455 ps
T1256 /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2121362541 May 14 04:04:50 PM PDT 24 May 14 04:06:44 PM PDT 24 10428431273 ps
T1257 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.506594893 May 14 04:03:28 PM PDT 24 May 14 04:04:07 PM PDT 24 107369002 ps
T1258 /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1623168807 May 14 04:04:34 PM PDT 24 May 14 04:04:41 PM PDT 24 51318021 ps
T643 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2960523308 May 14 04:09:57 PM PDT 24 May 14 04:10:11 PM PDT 24 110750930 ps
T357 /workspace/coverage/cover_reg_top/15.chip_csr_rw.2592595347 May 14 04:03:46 PM PDT 24 May 14 04:09:39 PM PDT 24 3352983572 ps
T429 /workspace/coverage/cover_reg_top/0.xbar_stress_all.3655230404 May 14 03:59:45 PM PDT 24 May 14 04:10:17 PM PDT 24 16414712115 ps
T569 /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1471908821 May 14 04:08:07 PM PDT 24 May 14 04:24:43 PM PDT 24 53893880744 ps
T1259 /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2136655530 May 14 04:15:41 PM PDT 24 May 14 04:16:05 PM PDT 24 176200904 ps
T637 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1185356678 May 14 04:06:05 PM PDT 24 May 14 04:07:06 PM PDT 24 170738480 ps
T633 /workspace/coverage/cover_reg_top/22.xbar_random.779236486 May 14 04:05:16 PM PDT 24 May 14 04:05:55 PM PDT 24 995503038 ps
T457 /workspace/coverage/cover_reg_top/80.xbar_same_source.1046045252 May 14 04:14:00 PM PDT 24 May 14 04:15:04 PM PDT 24 1879218690 ps
T1260 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2013327580 May 14 04:03:42 PM PDT 24 May 14 04:05:13 PM PDT 24 861678625 ps
T533 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3508230333 May 14 04:05:58 PM PDT 24 May 14 04:13:51 PM PDT 24 3098048382 ps
T860 /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.613549597 May 14 03:59:45 PM PDT 24 May 14 04:19:36 PM PDT 24 67999522356 ps
T335 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.42093064 May 14 04:02:56 PM PDT 24 May 14 04:54:23 PM PDT 24 28492106232 ps
T1261 /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4069393886 May 14 04:08:27 PM PDT 24 May 14 04:08:35 PM PDT 24 53098621 ps
T1262 /workspace/coverage/cover_reg_top/26.xbar_error_random.3562071568 May 14 04:06:07 PM PDT 24 May 14 04:07:01 PM PDT 24 1344417811 ps
T833 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.882570576 May 14 03:59:48 PM PDT 24 May 14 04:09:46 PM PDT 24 13794115675 ps
T494 /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.784636306 May 14 04:05:48 PM PDT 24 May 14 04:06:15 PM PDT 24 296693992 ps
T411 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1864002100 May 14 04:05:45 PM PDT 24 May 14 04:11:49 PM PDT 24 5704610011 ps
T1263 /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1110449131 May 14 04:10:33 PM PDT 24 May 14 04:12:08 PM PDT 24 8053084823 ps
T456 /workspace/coverage/cover_reg_top/64.xbar_random.1152779676 May 14 04:11:44 PM PDT 24 May 14 04:12:30 PM PDT 24 517033405 ps
T840 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1688593923 May 14 04:11:58 PM PDT 24 May 14 04:18:24 PM PDT 24 10080033202 ps
T604 /workspace/coverage/cover_reg_top/86.xbar_same_source.2488476338 May 14 04:14:58 PM PDT 24 May 14 04:16:08 PM PDT 24 2176210179 ps
T471 /workspace/coverage/cover_reg_top/41.xbar_random.3256125378 May 14 04:08:27 PM PDT 24 May 14 04:09:08 PM PDT 24 405703366 ps
T1264 /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.370577212 May 14 04:01:00 PM PDT 24 May 14 04:01:49 PM PDT 24 1290303597 ps
T1265 /workspace/coverage/cover_reg_top/92.xbar_smoke.103734388 May 14 04:15:34 PM PDT 24 May 14 04:15:44 PM PDT 24 167991325 ps
T1266 /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2917491413 May 14 04:09:52 PM PDT 24 May 14 04:10:10 PM PDT 24 120551867 ps
T407 /workspace/coverage/cover_reg_top/6.xbar_same_source.1840761266 May 14 04:00:28 PM PDT 24 May 14 04:01:13 PM PDT 24 1487106964 ps
T541 /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1136298007 May 14 04:04:29 PM PDT 24 May 14 04:04:50 PM PDT 24 225582785 ps
T433 /workspace/coverage/cover_reg_top/88.xbar_stress_all.1346081700 May 14 04:15:06 PM PDT 24 May 14 04:20:51 PM PDT 24 9150024782 ps
T1267 /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3104226517 May 14 04:13:53 PM PDT 24 May 14 04:14:01 PM PDT 24 51420526 ps
T1268 /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2730891901 May 14 04:08:54 PM PDT 24 May 14 04:09:31 PM PDT 24 2047607606 ps
T574 /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3792679809 May 14 04:14:42 PM PDT 24 May 14 04:28:59 PM PDT 24 46969225571 ps
T338 /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1880576169 May 14 04:03:26 PM PDT 24 May 14 04:50:52 PM PDT 24 28972590570 ps
T1269 /workspace/coverage/cover_reg_top/2.xbar_error_random.3023691658 May 14 03:59:54 PM PDT 24 May 14 04:00:36 PM PDT 24 559556326 ps
T425 /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2724170132 May 14 04:11:51 PM PDT 24 May 14 04:28:39 PM PDT 24 59037831433 ps
T527 /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2512258918 May 14 04:12:14 PM PDT 24 May 14 04:24:11 PM PDT 24 63847684068 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%