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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.47 100.00 93.88 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 97.14 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.91 97.37 78.26 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.30 94.29 76.54 86.36 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.82 100.00 71.27 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 83.23 96.15 74.29 62.50 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.46 100.00 97.83 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 97.14 98.77 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.93 99.75 99.51 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.91 100.00 95.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 97.14 97.53 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.92 100.00 99.68 100.00 100.00 u_reg_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
TotalCoveredPercent
Conditions494693.88
Logical494693.88
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T47
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT42,T499,T500
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T66,T67
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T66,T67

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T63,T64
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T242,T396
11CoveredT1,T2,T3

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010Not Covered
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT499,T500,T501
10CoveredT499,T500,T501

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T19,T47
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01CoveredT177,T368,T586
10CoveredT1,T2,T3
11CoveredT17,T19,T47

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010CoveredT494,T587,T588
00100CoveredT1,T2,T3
01000Not Covered
10000CoveredT63,T64,T191

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2735 2735 0 0
MatchedWidthAssert 2735 2735 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL383797.37
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 0 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
TotalCoveredPercent
Conditions463678.26
Logical463678.26
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT170,T30,T31
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T156,T19

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T66,T67
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T66,T67

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T156,T19
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT17,T156,T19

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT17,T156,T19
10Not Covered
11CoveredT1,T2,T3

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT17,T156,T19
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T156,T19

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T156,T19
010Not Covered
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT1,T2,T3
01000Not Covered
10000Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T17,T156,T19
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T17,T156,T19
0 Covered T17,T156,T19


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T17,T156,T19
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 846 846 0 0
MatchedWidthAssert 846 846 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 846 846 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 846 846 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
TotalCoveredPercent
Conditions464597.83
Logical464597.83
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT177,T178,T347
11CoveredT1,T3,T59

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT177,T178,T347
11CoveredT1,T3,T59

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T59
11CoveredT1,T3,T59

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T59
01CoveredT62,T63,T64
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T59
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T63,T64

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT177,T178,T347
10CoveredT1,T3,T59
11CoveredT1,T3,T59

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T59

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T3,T59
10CoveredT62,T63,T64
11CoveredT1,T3,T59

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T3,T59
10CoveredT62,T242,T396
11CoveredT1,T3,T59

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T3,T59
1CoveredT1,T3,T59

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T3,T59
1CoveredT1,T3,T59

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T3,T59
001CoveredT1,T3,T59
010CoveredT499,T500,T501
100CoveredT584,T585

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T3,T59
01CoveredT499,T500,T501
10CoveredT499,T500,T501

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T59

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T3,T59
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T3,T59
00001Unreachable
00010CoveredT396,T484,T494
00100CoveredT62,T242,T396
01000Not Covered
10000CoveredT63,T64,T191

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T59
0 0 1 Covered T1,T3,T59
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T3,T59
0 1 0 Covered T1,T3,T59
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T3,T59
0 Covered T1,T3,T59


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T3,T59
0 1 0 Covered T1,T3,T59
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2735 2735 0 0
MatchedWidthAssert 2735 2735 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT178,T362,T363
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT364,T177,T178
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT45,T89,T184

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T63,T64
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T63,T64

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT63,T192,T241
10CoveredT45,T89,T184
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T63,T64
11CoveredT45,T89,T184

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT45,T89,T184
10CoveredT62,T242,T396
11CoveredT1,T2,T3

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT45,T89,T184
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T89,T184

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT45,T89,T184
010CoveredT500,T501,T503
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT499,T500,T501
10CoveredT499,T500,T501

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010CoveredT480,T494,T495
00100CoveredT1,T2,T3
01000Not Covered
10000CoveredT63,T64,T191

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T45,T89,T184
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T45,T89,T184
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T45,T89,T184
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2735 2735 0 0
MatchedWidthAssert 2735 2735 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2735 2735 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T33 1 1 0 0
T59 1 1 0 0
T60 1 1 0 0
T98 1 1 0 0
T102 1 1 0 0
T132 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%